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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
AgeCommit message (Expand)Author
2024-04-19drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä
2024-04-19drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä
2024-04-17drm/i915: Pass the PLL hw_state to pll->enable()Ville Syrjälä
2024-04-17drm/i915: Introduce some local PLL state variablesVille Syrjälä
2024-04-17drm/i915: Rename PLL hw_state variables/argumentsVille Syrjälä
2024-03-21drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula
2024-03-18drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed()Jonathon Hall
2024-03-15drm/i915: Convert intel_dpll_dump_hw_state() to drm_printerVille Syrjälä
2024-02-15drm/i915: Add PLL .compare_hw_state() vfuncVille Syrjälä
2024-02-15drm/i915: Reuse ibx_dump_hw_state() for gmch platformsVille Syrjälä
2024-01-26drm/i915: Convert PLL flags to booleansVille Syrjälä
2024-01-26drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLsVille Syrjälä
2024-01-26drm/i915: Include the PLL name in the debug messagesVille Syrjälä
2024-01-23drm/i915: Try to preserve the current shared_dpll for fastset on type-c portsVille Syrjälä
2024-01-19drm/i915: Replace a memset() with zero initializationVille Syrjälä
2023-11-24drm/i915: Stop printing pipe name as hexVille Syrjälä
2023-10-31drm/i915: Extract _intel_{enable,disable}_shared_dpll()Ville Syrjälä
2023-10-31drm/i915: Move the DPLL extra power domain handling up one levelVille Syrjälä
2023-10-31drm/i915: Abstract the extra JSL/EHL DPLL4 power domain betterVille Syrjälä
2023-10-31drm/i915: Use named initializers for DPLL infoVille Syrjälä
2023-10-06drm/i915: Simplify DPLL state checker calling conventionVille Syrjälä
2023-10-06drm/i915: Constify the crtc states in the DPLL checkerVille Syrjälä
2023-10-04drm/i915: s/dev_priv/i915/ in the shared_dpll codeVille Syrjälä
2023-10-04drm/i915: Introduce for_each_shared_dpll()Ville Syrjälä
2023-10-04drm/i915: Decouple I915_NUM_PLLS from PLL IDsVille Syrjälä
2023-10-04drm/i915: Stop requiring PLL index == PLL IDVille Syrjälä
2023-08-30Merge tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
2023-08-18drm/i915: Move abs_diff() to math.hAndy Shevchenko
2023-08-07drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane
2023-08-07drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane
2023-08-07drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane
2023-05-16drm/i915: Make the CRTC state consistent during sanitize-disablingImre Deak
2023-05-16drm/i915: Add helpers to reference/unreference a DPLL for a CRTCImre Deak
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula
2023-05-15drm/i915/dpll: drop a useless I915_STATE_WARN_ON()Jani Nikula
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada
2023-02-16drm/i915/display/dpll: use intel_de_rmw if possibleAndrzej Hajda
2023-01-18drm/i915: move pch_ssc_use to display sub-struct under dpllJani Nikula
2022-11-17drm/i915/hti: abstract hti handlingJani Nikula
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula
2022-10-26drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak
2022-10-26drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak
2022-10-26drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak
2022-10-26drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak
2022-09-26drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä
2022-09-26drm/i915: Always initialize dpll.lockVille Syrjälä
2022-09-26drm/i915: WARN if PLL ref/unref got messed upVille Syrjälä
2022-09-26drm/i915: Pimp DPLL ref/unref debugsVille Syrjälä
2022-09-26drm/i915: Drop pointless 'budget' variableVille Syrjälä
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