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path: root/drivers/gpu/drm/i915/i915_debugfs.c
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2011-08-09drm/i915: show interrupt info on IVBJesse Barnes
IVB uses the same interrupt reg layout as SNB, so add an IS_GEN7 to the interrupt debugfs file. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-08-03drm/i915: allow cache sharing policy controlJesse Barnes
Expose the SNB+ cache sharing policy register in debugfs. The new file, i915_cache_sharing, has 4 values, 0-3, with 0 being "max uncore resources" and 3 being the minimum. Exposing this control should make benchmarking easier and help us choose a good default. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-29Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard
2011-07-29drm/i915: add GPU max frequency control fileJesse Barnes
Mainly for use in debugging and benchmarking, this file allows the user to control the max frequency used by the GPU. Frequency may still vary based on workload (if the frequency is set to higher than the minimum) but won't go over the newly set value. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-29Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard
2011-06-29drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3Jesse Barnes
They use the same register interfaces, so we can simply enable the existing code on IVB. v2: - resolve conflict with ring freq scaling, we can enable it too v3: - resolve conflict again, this time on drm-intel-next Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-29drm/i915: Don't call describe_obj on NULL pointersBen Widawsky
Reported-by: Pavel Roskin <proski@gnu.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38777 Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-28drm/i915: load a ring frequency scaling table v3Jesse Barnes
The ring frequency scaling table tells the PCU to treat certain GPU frequencies as if they were a given CPU frequency for purposes of scaling the ring frequency. Normally the PCU will scale the ring frequency based on the CPU P-state, but with the table present, it will also take the GPU frequency into account. The main downside of keeping the ring frequency high while the CPU is at a low frequency (or asleep altogether) is increased power consumption. But then if you're keeping your GPU busy, you probably want the extra performance. v2: - add units to debug table header (from Eric) - use tsc_khz as a fallback if the cpufreq driver doesn't give us a freq (from Chris) v3: - fix comments & debug output - remove unneeded force wake get/put Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-04drm/i915: Only print out the actual number of fences for i915_error_stateDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-17drm/i915: add fbc enable flag, but disable by defaultJesse Barnes
FBC has too many corner cases that we don't currently deal with, so disable it by default so we can enable more important features like RC6, which conflicts in some configurations. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31742 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13drm/i915: forcewake debugfs fixBen Widawsky
Forcewake needs to register itself with drm to use the remove function. The file also should be read only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10drm/i915: debugfs interface for forcewake reference countBen Widawsky
forcewake is controlled by the open and close of the debugfs file. This assures that buggy applications cannot cause the GT to stay on forever. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10drm/i915: forcewake struct mutex locking fixesBen Widawsky
Found by the new strict checking for the mutex being held whilst manipulating the forcewake status. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10drm/i915: reference counted forcewakeBen Widawsky
Provide a reference count to track the forcewake state of the GPU and give a safe mechanism for userspace to wake the GT. This also potentially saves a UC read if the GT is known to be awake already. The reference count is atomic, but the register access and hardware wake sequence is protected by struct_mutex. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10drm/i915: Rename agp_type to cache_levelChris Wilson
... to clarify just how we use it inside the driver and remove the confusion of the poorly matching agp_type names. We still need to translate through agp_type for interface into the fake AGP driver. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10drm/i915: debugfs for context informationBen Widawsky
Currently this is only useful for the rc6 stuff. But this would also be useful when I finally get around to the logical context + ppgtt stuff. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-03-23drm/i915: report correct render clock frequencies on SNBJesse Barnes
Fix up the debug file to report the right frequencies. On SNB, we program the PCU with a frequency ratio, which is multiplied by 100MHz on the CPU side. But GFX only runs at half that, so report it as such to avoid confusion. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com>
2011-03-07Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Apply the trivial conflicting regression fixes, but keep GPU semaphores enabled. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_execbuffer.c
2011-03-06drm/i915: Do not overflow the MMADDR write FIFOChris Wilson
Whilst the GT is powered down (rc6), writes to MMADDR are placed in a FIFO by the System Agent. This is a limited resource, only 64 entries, of which 20 are reserved for Display and PCH writes, and so we must take care not to queue up too many writes. To avoid this, there is counter which we can poll to ensure there are sufficient free entries in the fifo. "Issuing a write to a full FIFO is not supported; at worst it could result in corruption or a system hang." Reported-and-Tested-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: cleanup per-pipe reg usageJesse Barnes
We had some conversions over to the _PIPE macros, but didn't get everything. So hide the per-pipe regs with an _ (still used in a few places for legacy) and add a few _PIPE based macros, then make sure everyone uses them. [update: remove usage of non-existent no-op macro] [update 2: keep modesetting suspend/resume code, update to new reg names] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: stylistic cleanups for checkpatch and taste] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-28drm/i915: Record all error ringbuffersChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes
These make us increase our frequency much more readily, and decrease them only after significant idle time, resulting in a 20% performance increase for nexuiz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Trivial sparse fixesChris Wilson
Move code around and invoke iomem annotation in a few more places in order to silence sparse. Still a few more iomem annotations to go... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-12drm/i915/debugfs: Correct format after changing type of err object 'size'Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915/debugfs: Show all objects in the gttChris Wilson
Useful for determining the layout. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915: Record AGP memory type upon errorChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915: Record the error batchbuffer on each ringChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes
Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915/debugfs: Show the per-ring IMRChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-18drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes
Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15drm/i915: Add self-refresh support on SandybridgeYuanhan Liu
Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson
The bulk of the change is to convert the growing list of rings into an array so that the relationship between the rings and the semaphore sync registers can be easily computed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Defer accounting until read from debugfsChris Wilson
Simply remove our accounting of objects inside the aperture, keeping only track of what is in the aperture and its current usage. This removes the over-complication of BUGs that were attempting to keep the accounting correct and also removes the overhead of the accounting on the hot-paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24drm/i915: More accurately track last fence usage by the GPUChris Wilson
Based on a patch by Daniel Vetter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Record fence registers on error.Chris Wilson
Having seen the effects of erroneous fencing on the batchbuffer, a useful sanity check is to record the fence registers at the time of an error. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Use drm_i915_gem_object as the preferred typeChris Wilson
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and many characters! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Avoid oops when capturing NULL ring for inactive pinned buffersChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22drm/i915: Capture interesting display registers on errorChris Wilson
When trying to diagnose mysterious errors on resume, capture the display register contents as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22drm/i915: Capture pinned buffers on errorChris Wilson
The pinned buffers are useful for diagnosing errors in setting up state for the chipset, which may not necessarily be 'active' at the time of the error, e.g. the cursor buffer object. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-11drm/i915: Remove the global irq wait queueChris Wilson
... as it has been replaced by per-ring waiters. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01drm/i915/debugfs: Report ring in error stateChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915: Record BSD engine error stateChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915/debugfs: Display the contents of the BLT and BSD status pagesChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915: Record BLT engine error stateChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915: Only enforce fence limits inside the GTT.Chris Wilson
So long as we adhere to the fence registers rules for alignment and no overlaps (including with unfenced accesses to linear memory) and account for the tiled access in our size allocation, we do not have to allocate the full fenced region for the object. This allows us to fight the bloat tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside the GTT we still suffer the additional alignment constraints, so it doesn't magic allow us to render larger scenes without stalls -- we need the expanded GTT and fence pipelining to overcome those...] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915: Capture ERROR register on Sandybridge hangsChris Wilson
This holds error state from the main graphics arbiter mainly involving the DMA engine and address translation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915: add accounting for mappable objects in gtt v2Daniel Vetter
More precisely: For those that _need_ to be mappable. Also add two BUG_ONs in fault and pin to check the consistency of the mappable flag. Changes in v2: - Add tracking of gtt mappable space (to notice mappable/unmappable balancing issues). - Improve the mappable working set tracking by tracking fault and pin separately. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915: Remove the confusing global waiting/irq seqnoChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915/debugfs: Include info for the other ringsChris Wilson
The render ring is not alone any more! And the other rings are just as troublesome... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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