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path: root/drivers/gpu/drm/i915/i915_drv.h
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2010-09-07drm/i915: Include a generation number in the device infoChris Wilson
To simplify the IS_GEN[234] macros and to enable switching. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-08-09drm/i915: Set up a render context on IronlakeZou Nan hai
RC6 power state requires a logical render context in place for saving render context. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Apply i830 errata for cursor alignmentChris Wilson
i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose the alignment parameter to i915_gem_attach_phys_object(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Enable aspect/centering panel fitting for Ironlake.Chris Wilson
v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Implement fair lru eviction across both rings. (v2)Chris Wilson
Based in a large part upon Daniel Vetter's implementation and adapted for handling multiple rings in a single pass. This should lead to better gtt usage and fixes the page-fault-of-doom triggered. The fairness is provided by scanning through the GTT space amalgamating space in rendering order. As soon as we have a contiguous space in the GTT large enough for the new object (and its alignment), evict any object which lies within that space. This should keep more objects resident in the GTT. Doing throughput testing on a PineView machine with cairo-perf-trace indicates that there is very little difference with the new LRU scan, perhaps a small improvement... Except oddly for the poppler trace. Reference: Bug 15911 - Intermittent X crash (freeze) https://bugzilla.kernel.org/show_bug.cgi?id=15911 Bug 20152 - cannot view JPG in firefox when running UXA https://bugs.freedesktop.org/show_bug.cgi?id=20152 Bug 24369 - Hang when scrolling firefox page with window in front https://bugs.freedesktop.org/show_bug.cgi?id=24369 Bug 28478 - Intermittent graphics lockups due to overflow/loop https://bugs.freedesktop.org/show_bug.cgi?id=28478 v2: Attempt to clarify the logic and order of eviction through the use of comments and macros. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Move the eviction logic to its own file.Chris Wilson
The eviction code is the gnarly underbelly of memory management, and is clearer if kept separated from the normal domain management in GEM. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Use a common seqno for all rings.Chris Wilson
This will be used by the eviction logic to maintain fairness between the rings. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Capture the overlay status upon a GPU hang.Chris Wilson
v2: Add the interrupt status and address. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Use an uncommon name for the local dev_priv in macrosChris Wilson
Using dev_priv__ avoids sparse complaining about shadowed variables in the *LP_RING() macros. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09drm/i915: Only emit flushes on active rings.Chris Wilson
This avoids the excess flush and requests on idle rings (and spamming the debug log ;-) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Repeat unbinding during free if interrupted (v6)Chris Wilson
If during the freeing of an object the unbind is interrupted by a system call, which is quite possible if we have outstanding GPU writes that must be flushed, the unbind is silently aborted. This still leaves the AGP region and backing pages allocated, and perhaps more importantly, the object remains upon the various lists exposing us to memory corruption. I think this is the cause behind the use-after-free, such as Bug 15664 - Graphics hang and kernel backtrace when starting Azureus with Compiz enabled https://bugzilla.kernel.org/show_bug.cgi?id=15664 v2: Daniel Vetter reminded me that kernel space programming is never easy. We cannot simply spin to clear the pending signal and so must deferred the freeing of the object until later. v3: Run from the top level retire requests. v4: Tested with P(return -ERESTARTSYS)=.5 from i915_gem_do_wait_request() v5: Rebase against Eric's for-linus tree. v6: Refactor, split and add a comment about avoiding unbounded recursion. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Refactor i915_gem_retire_requests()Chris Wilson
Combine the iteration over active render rings into a common function. This is in preparation for reusing the idle function to also retire deferred free requests. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01Merge remote branch 'origin/master' into drm-intel-nextEric Anholt
This resolves the conflict in the EDP code, which has been rather popular to hack on recently. Conflicts: drivers/gpu/drm/i915/intel_dp.c
2010-08-01drm/i915: Use 128k alignment for untiled display surface on i965 (v2)Chris Wilson
The original i965, including the revised G35 and Q35, requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment is required. (So long as we do not start performing asynchronous flips.) Note the impact of this should be slight as on i965 we should be using a tiled frontbuffer for anything up to a 4096x4096 display. v2: compilation fixes and note that the docs do not exclude the G35 from the extra alignment. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Include instdone[1] in hangcheckChris Wilson
References: Bug 26691 - Spurious hangcheck whilst executing a long shader over a large vertex buffer https://bugs.freedesktop.org/show_bug.cgi?id=26691 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Sparse warns about the incorrect sign for storing bit17Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Silence sparse complaints over insufficient bitfield int types.Chris Wilson
drivers/gpu/drm/i915/i915_drv.h|676 col 19| warning: dubious bitfield without explicit `signed' or `unsigned' drivers/gpu/drm/i915/i915_drv.h|712 col 19| warning: dubious bitfield without explicit `signed' or `unsigned' Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Propagate error from i915_gem_object_flush_gpu_write_domain()Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Add frame buffer compression support on Ironlake mobileZhao Yakui
About 0.2W power can be saved on one HP laptop. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Fix watermark calculation in self-refresh modeZhao Yakui
For self-refresh mode WM calculation's "line time" should use mode's htotal instead of hdisplay. "surface width" is the hdisplay for display plane and 64 for cursor plane. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-26drm/i915: add pipe A force quirks to i915 driverJesse Barnes
Ported over from the old UMS list. Unfortunately they're still necessary especially on older laptop platforms. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=22126. Tested-by: Xavier <shiningxc@gmail.com> Tested-by: Diego Escalante Urrelo <diegoe@gnome.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-26drm/i915: disable FBC when more than one pipe is activeJesse Barnes
We're really supposed to do this to avoid trouble with underflows when multiple planes are active. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=26987. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: fangxun <xunx.fang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-01Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: fix page flip finish vs. prepare on plane B drm/i915: change default panel fitting mode to preserve aspect ratio drm/i915: fix uninitialized variable warning in i915_setup_compression() drm/i915: take struct_mutex in i915_dma_cleanup() drm/i915: Fix CRT hotplug regression in 2.6.35-rc1 i915: fix ironlake edp panel setup (v4) drm/i915: don't access FW_BLC_SELF on 965G drm/i915: Account for space on the ring buffer consumed whilst wrapping. drm/i915: gen3 page flipping fixes drm/i915: don't queue flips during a flip pending event drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer. drm/i915: Turn on 945 self-refresh only if single CRTC is active drm/i915/gen4: Fix interrupt setup ordering drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection. drm/i915: Move non-phys cursors into the GTT Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)." (Included the "fix page flip finish vs. prepare on plane B" patch from Jesse on top of the pull request from Eric. -- Linus)
2010-06-18drm/i915: gen3 page flipping fixesJesse Barnes
Gen3 chips have slightly different flip commands, and also contain a bit that indicates whether a "flip pending" interrupt means the flip has been queued or has been completed. So implement support for the gen3 flip command, and make sure we use the flip pending interrupt correctly depending on the value of ECOSKPD bit 0. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-14drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.Zou Nan hai
The ring_begin API was taking a number of bytes, while all of our other begin/end macros take number of dwords. Change the API over to dwords to prevent future bugs. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-08drm/i915: fix oops on single crtc devices.Dave Airlie
(regression fix since fbdev/kms rework). My fb rework didn't remember about the 84/65s. Reported-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-05-26drm/i915: Clean up leftover bits from hws move to ring structure.Eric Anholt
Fixes /debug/dri/0/i915_gem_interrupt output for status page. Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: Add CxSR support on Pineview DDR3Li Peng
Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: combine all small integers into one single bitfieldDaniel Vetter
This saves a whooping 7 dwords. Zero functional changes. Because some of the refcounts are rather tightly calculated, I've put BUG_ONs in the code to check for overflows. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: add power monitoring supportJesse Barnes
Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Fixed 32-bit compile. stupid obfuscating div_u64()] Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: implement BSD ring buffer V2Zou Nan hai
The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: convert some gem structures to per-ring V2Zou Nan hai
The active list and request list move into the ringbuffer structure, so each can track its active objects in the order they are in that ring. The flushing list does not, as it doesn't matter which ring caused data to end up in the render cache. Objects gain a pointer to the ring they are active on (if any). Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: introduce intel_ring_buffer structure (V2)Zou Nan hai
Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> [anholt: Fixed up whitespace fail and rebased against prep patches] Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26drm/i915: Rename dev_priv->ring to dev_priv->render_ring.Eric Anholt
With the advent of the BSD ring, be clear about which ring this is. The docs are pretty consistent with calling this the Render engine at this point.
2010-05-26drm/i915: Move ringbuffer-related code to intel_ringbuffer.c.Eric Anholt
This is preparation for supporting multiple ringbuffers on Ironlake. The non-copy-and-paste changes are: - de-staticing functions - I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files. - i915_gem_add_request had only half its implementation copy-and-pasted out of the middle of it.
2010-05-10drm/i915: move fence lru to struct drm_i915_fence_regDaniel Vetter
This lru tracks fences, not objects, so move it to where it belongs. As a side effect, this nicely shrinks drm_i915_gem_object by two pointers. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-10drm/i915: Fix DDC bus selection for multifunction SDVOAdam Jackson
Multifunction SDVO cards stopped working after 14571b4, and would report something that looked remarkably like an ADD2 SPD ROM instead of EDID. This appears to be because DDC bus selection was utterly horked by that commit; controlled_output was no longer always a single bit, so intel_sdvo_select_ddc_bus would pick bus 0, which is (unsurprisingly) the SPD ROM bus, not a DDC bus. So, instead of that, let's just use the DDC bus the child device table tells us to use. I'm guessing at the bitmask and shifting from VBIOS dumps, but it can't possibly be worse. cf. https://bugzilla.redhat.com/584229 Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-10Merge remote branch 'origin/master' into drm-intel-nextEric Anholt
Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/radeon/r300.c The BSD ringbuffer support that is landing in this branch significantly conflicts with the Ironlake PIPE_CONTROL fix on master, and requires it to be tested successfully anyway.
2010-05-07drm/i915: Make fbc control wrapper functionsAdam Jackson
Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-22drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy BridgeJesse Barnes
Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver. So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware. https://bugs.freedesktop.org/show_bug.cgi?id=27108 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-22drm/i915: cleanup FBC buffers at unload timeJesse Barnes
This keeps the memory manager from complaining when we take it down. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-20drm/i915: drop pointer to drm_gem_objectDaniel Vetter
Luckily the change is quite a little bit less invasive than I've feared. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20drm/i915: don't use ->driver_private anymoreDaniel Vetter
Thanks to the to_intel_bo helper, this change is rather trivial. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20drm/i915: embed the gem object into drm_i915_gem_objectDaniel Vetter
Just embed it and adjust the pointers, No other changes (that's for later patches). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20drm/i915: introduce i915_gem_alloc_objectDaniel Vetter
Just preparation, no functional change. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20Merge branch 'drm-fbdev-cleanup' into drm-core-nextDave Airlie
* drm-fbdev-cleanup: drm/fb: remove drm_fb_helper_setcolreg drm/kms/fb: use slow work mechanism for normal hotplug also. drm/kms/fb: add polling support for when nothing is connected. drm/kms/fb: provide a 1024x768 fbcon if no outputs found. drm/kms/fb: separate fbdev connector list from core drm connectors drm/kms/fb: move to using fb helper crtc grouping instead of core crtc list drm/fb: fix fbdev object model + cleanup properly. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/nouveau/nouveau_drv.h
2010-04-18drm/i915: Fix 82854 PCI ID, and treat it like other 85XAdam Jackson
pci.ids and the datasheet both say it's 358e, not 35e8. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-12drm/i915: enable DP/eDP for Sandybridge/CougarpointZhenyu Wang
DP on Cougarpoint has new training pattern definitions, and new transcoder DP control register is used to determine the mapping for transcoder and DP digital output. And eDP for Sandybridge has new voltage and pre-emphasis level definitions. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-12drm/i915: Probe for PCH chipset typeZhenyu Wang
PCH is the new name for south bridge from Ironlake/Sandybridge, which contains most of the display outputs except eDP. This one adds a probe function to detect current PCH type, and method to detect Cougarpoint PCH. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-12drm/i915: Sandybridge has no integrated TVZhenyu Wang
Integrated TV is deprecated in new chips from Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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