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path: root/drivers/gpu/drm/i915/i915_irq.c
AgeCommit message (Expand)Author
2016-04-20drm/i915/gen8+: Do not enable DPF interrupt since the handler does not existTvrtko Ursulin
2016-04-14drm/i915: Split gen8_gt_irq_handler into ack+handleVille Syrjälä
2016-04-14drm/i915: Eliminate passing dev+dev_priv to {snb,ilk}_gt_irq_handler()Ville Syrjälä
2016-04-14drm/i915: Move gt/pm irq handling out from irq disabled section on VLVVille Syrjälä
2016-04-14drm/i915: Split VLV/CVH PIPESTAT handling into ack+handlerVille Syrjälä
2016-04-14drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler()Ville Syrjälä
2016-04-14drm/i915: Move variables to narrower scope in VLV/CHV irq handlersVille Syrjälä
2016-04-14drm/i915: Eliminate loop from VLV irq handlerVille Syrjälä
2016-04-14drm/i915: Clear VLV_IER around irq processingVille Syrjälä
2016-04-14drm/i915: Clear VLV_MASTER_IER around irq processingVille Syrjälä
2016-04-14drm/i915: Clear VLV_IIR after PIPESTATVille Syrjälä
2016-04-14drm/i915: Set up VLV_MASTER_IER consistentlyVille Syrjälä
2016-04-14drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistentlyVille Syrjälä
2016-04-14drm/i915: Tighten reset_counter for reset statusChris Wilson
2016-04-14drm/i915: Hide the atomic_read(reset_counter) behind a helperChris Wilson
2016-04-12drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()Ville Syrjälä
2016-04-12drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstallVille Syrjälä
2016-04-12drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()Ville Syrjälä
2016-04-12drm/i915: Clear display interrupt before enabling when turning on the power wellVille Syrjälä
2016-04-12drm/i915: Move vlv/chv display irq code to a more logical placeVille Syrjälä
2016-04-12drm/i915: Skip display irq setup if display irqs aren't flagged as enabledVille Syrjälä
2016-04-12drm/i915: Fix up vlv/chv display irq setupVille Syrjälä
2016-04-12drm/i915: Remove "VLV magic" from irq setupVille Syrjälä
2016-04-09drm/i915: Harden detection of missed interruptsChris Wilson
2016-04-09drm/i915: Separate out the seqno-barrier from engine->get_seqnoChris Wilson
2016-04-08drm/i915: Simplify check for idleness in hangcheckChris Wilson
2016-04-08drm/i915: Apply a mb between emitting the request and hangcheckChris Wilson
2016-04-07drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)Joonas Lahtinen
2016-04-06drm/i915: Set invert bit for hpd based on VBTShubhangi Shrivastava
2016-04-04drm/i915: Move execlists irq handler to a bottom halfTvrtko Ursulin
2016-03-30drm/i915: Exit cherryview_irq_handler() after one passChris Wilson
2016-03-24drm/i915: replace for_each_engine()Dave Gordon
2016-03-24drm/i915: introduce for_each_engine_id()Dave Gordon
2016-03-22drm/i915/tdr: Prepare error handler to accept mask of hung enginesarun.siluvery@linux.intel.com
2016-03-17drm/i915: Move load time IRQ SW init earlierImre Deak
2016-03-16drm/i915: More renaming of rings to enginesTvrtko Ursulin
2016-03-16drm/i915: More intel_engine_cs renamingTvrtko Ursulin
2016-03-16drm/i915: Rename intel_engine_cs struct membersTvrtko Ursulin
2016-03-16drm/i915: Rename intel_engine_cs function parametersTvrtko Ursulin
2016-03-16drm/i915: Rename local struct intel_engine_cs variablesTvrtko Ursulin
2016-03-04drm/i915/hangcheck: Prevent long walks across full-ppgttMika Kuoppala
2016-02-22drm/i915: Add for_each_pipe_masked()Ville Syrjälä
2016-02-22drm/i915: Make sure pipe interrupts are processed before turning off power we...Ville Syrjälä
2016-02-22drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is ...Ville Syrjälä
2016-01-13drm/i915/gen8: Factor out display interrupt handlingTvrtko Ursulin
2016-01-13drm/i915/gen8: Tidy display interrupt processingTvrtko Ursulin
2016-01-08drm/i915: Do one shot unclaimed mmio detection less frequentlyMika Kuoppala
2016-01-08drm/i915: Introduce intel_uncore_unclaimed_mmioMika Kuoppala
2016-01-08drm/i915: Inspect subunit states on hangcheckMika Kuoppala
2016-01-07drm/i915: shut up gen8+ SDE irq dmesg noise, againJani Nikula
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