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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2015-07-06drm/i915: Update WaFlushCoherentL3CacheLinesAtContextSwitchArun Siluvery
2015-07-06drm/i915: Enable Resource Streamer state save/restore on MI_SET_CONTEXTAbdiel Janulgue
2015-07-06drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_STARTAbdiel Janulgue
2015-07-06drm/i915/bxt: BUNs related to port PLLVandana Kannan
2015-06-30drm/i915/bxt: add DDI port HW readout supportImre Deak
2015-06-30drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak
2015-06-30drm/i915/skl: Buffer translation improvementsDavid Weinehall
2015-06-29drm/i915: Compute display FIFO split dynamically for CHVVille Syrjälä
2015-06-26drm/i915: Update rps frequencies for BXTBob Paauwe
2015-06-24drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaroundArun Siluvery
2015-06-23drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery
2015-06-18drm/i915: Reset request handling for gen8+Mika Kuoppala
2015-06-18drm/i915/bxt: eDP Panel Power sequencingVandana Kannan
2015-06-15drm/i915: print FBC compression status on debugfsPaulo Zanoni
2015-06-15drm/i915: Delete duplicate #defines added for DCxChandra Konduru
2015-06-15drm/i915: Send GCP infoframes for deep color HDMI sinksVille Syrjälä
2015-06-15drm/i915: Implement WaEnableHDMI8bpcBefore12bpc:snb, ivbVille Syrjälä
2015-06-12drm/i915/skl: Derive the max CDCLK from DFSMDamien Lespiau
2015-06-12drm/i915: BDW clock change supportVille Syrjälä
2015-05-29drm/i915: Add cdclk extraction for g33, g965gm and g4xVille Syrjälä
2015-05-29drm/i915: Fix i855 get_display_clock_speedVille Syrjälä
2015-05-28drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä
2015-05-28drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä
2015-05-22drm/i915: Enable GTT caching on gen8Ville Syrjälä
2015-05-21drm/i915: Clean up the CPT DP .get_hw_state() port readoutVille Syrjälä
2015-05-21drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau
2015-05-21drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+Imre Deak
2015-05-20drm/i915/bxt: Port PLL programming BUNVandana Kannan
2015-05-20drm/i915: Adding dbuf support for skl nv12 format.Chandra Konduru
2015-05-08drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä
2015-05-08drm/i915: Implement chv display PHY lane stagger setupVille Syrjälä
2015-05-08drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCSDamien Lespiau
2015-05-08drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharingNick Hoath
2015-05-08drm/i915/bxt: BLC implementationVandana Kannan
2015-05-08drm/i915: Merge the GEN9 memory latency PCU opcode with its friendsDamien Lespiau
2015-05-08drm/i915: Re-order the PCU opcodesDamien Lespiau
2015-05-08drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau
2015-05-08drm/i915: Setup static bias for GPUDeepak S
2015-05-08drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath
2015-05-08Merge tag 'drm-intel-next-2015-04-23-fixed' of git://anongit.freedesktop.org/...Dave Airlie
2015-04-28drm/i915/chv: Implement WaDisableShadowRegForCpdDeepak S
2015-04-23drm/i915: cope with large i2c transfersDmitry Torokhov
2015-04-16drm/i915/bxt: VSwing programming sequenceVandana Kannan
2015-04-16drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M
2015-04-16drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath
2015-04-16drm/i915/bxt: add description about the BXT PHYsImre Deak
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan
2015-04-14drm/i915: PSR: Remove wrong LINK_DISABLE.Rodrigo Vivi
2015-04-14drm/i915/bxt: Enable GMBUS IRQShashank Sharma
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