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path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
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2012-10-03drm/nouveau: restructure source tree, split core from drm implementationBen Skeggs
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nouveau/fifo: turn all fifo modules into engine modulesBen Skeggs
Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nv50/fifo: use hardware channel kickoff functionalityBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nv50/fifo: construct playlist from hw context table stateBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nouveau/fifo: remove all the "special" engine hooksBen Skeggs
All the places this stuff is actually needed tends to be chipset-specific anyway, so we're able to just inline the register bashing instead. The parts of the common code that still directly touch PFIFO temporarily have conditionals, these will be removed in subsequent commits that will refactor the fifo modules into engine modules like graph/mpeg etc. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: Fix pushbufs over the 4GB mark.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25drm/nv50: drop explicit yields in favour of smaller PFIFO timesliceBen Skeggs
This gives a small, but noticeable performance gain at lower performance levels, and unchanged at the higher ones. With this commit, we're now using the same timeslice size as the NVIDIA binary driver currently does, and dropping an unknown bit that NVIDIA no longer appear to set. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: import new vm codeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs
The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: Refactor context destruction to avoid a lock ordering issue.Francisco Jerez
The destroy_context() engine hooks call gpuobj management functions to release the channel resources, these functions use HARDIRQ-unsafe locks whereas destroy_context() is called with the HARDIRQ-safe context_switch_lock held, that's a lock ordering violation. Push the engine-specific channel destruction logic into destroy_context() and let the hardware-specific code lock and unlock when it's actually needed. Change the engine destruction order to avoid a race in the small gap between pgraph and pfifo context uninitialization. Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: add more fine-grained locking to channel list + structuresBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-11-18drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hangBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nouveau: tidy ram{ht,fc,ro} a bitBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanityBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nouveau: rebase per-channel pramin heap offsets to 0Ben Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nouveau: modify object accessors, offset in bytes rather than dwordsBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-07-13drm/nv50: fix RAMHT sizeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-07-13drm/nv50: cleanup nv50_fifo.cBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-07-13drm/nouveau: add instmem flush() hookBen Skeggs
This removes the previous prepare_access() and finish_access() hooks, and replaces it with a much simpler flush() hook. All the chipset-specific code before nv50 has its use removed completely, as it's not required there at all. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-02-25drm/nv50: switch to indirect push buffer controlsBen Skeggs
PFIFO on G80 and up has a new mode where the main ring buffer is simply a ring of pointers to indirect buffers containing the actual command/data packets. In order to be able to implement index buffers in the 3D driver we need to be able to submit data-only push buffers right after the cmd packet header, which is only possible using the new command submission method. This commit doesn't make it possible to implement index buffers yet, some userspace interface changes will be required, but it does allow for testing/debugging of the hardware-side support in the meantime. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-02-25drm/nouveau: protect channel create/destroy and irq handler with a spinlockMaarten Maathuis
The nv50 pgraph handler (for example) could reenable pgraph fifo access and that would be bad when pgraph context is being unloaded (we need the guarantee a ctxprog isn't running). Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-02-10drm/nv50: delete ramfc object after disabling fifo, not beforeMaarten Maathuis
ramfc is zero'ed upon destruction, so it's safer to do things in the right order. Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-01-18drm/nv50: fix alignment of per-channel fifo cacheBen Skeggs
GPU pointer to the structure is shifted right by 10 bits, so we need to align to 1024 bytes, not 256. Reported-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-01-11drm/nv50: restore correct cache1 get/put address on fifoctx loadBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2009-12-16drm/nv50: fix two potential suspend/resume oopsesBen Skeggs
This avoids touching the dummy channel 0/127 we have on nv50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2009-12-11drm/nouveau: Add DRM driver for NVIDIA GPUsBen Skeggs
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA. This driver is a KMS-based driver and requires a compatible nouveau userspace libdrm and nouveau X.org driver. This driver requires firmware files not available in this kernel tree, interested parties can find them via the nouveau project git archive. This driver is reverse engineered, and is in no way supported by nVidia. Support for nearly the complete range of nvidia hw from nv04->g80 (nv50) is available, and the kms driver should support driving nearly all output types (displayport is under development still) along with supporting suspend/resume. This work is all from the upstream nouveau project found at nouveau.freedesktop.org. The original authors list from nouveau git tree is: Anssi Hannula <anssi.hannula@iki.fi> Ben Skeggs <bskeggs@redhat.com> Francisco Jerez <currojerez@riseup.net> Maarten Maathuis <madman2003@gmail.com> Marcin Koƛcielnicki <koriakin@0x04.net> Matthew Garrett <mjg@redhat.com> Matt Parnell <mparnell@gmail.com> Patrice Mandin <patmandin@gmail.com> Pekka Paalanen <pq@iki.fi> Xavier Chantry <shiningxc@gmail.com> along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>