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13 daysMerge tag 'drm-msm-next-2026-10-11' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/msm into drm-next Changes for v7.4 CI: - Dropped sc7180 trogdor lazor from the CI Core: - Fixed msm_ioremap for resources without a name - Changed msm.separate_gpu_kms to default to auto selection GPU: - Enable CLX (Current Limit eXtension) for gen8 to avoid exceeding limits on CX/GX rails - New GPUs: a830 (Pakala), a845 (Maili), a850 (Hawi), x2-85 (Mahua) - Fix VBIF halt mask on a306, which was preventing runpm suspend - Enable THP support for GEM buffers - Add modparam to disable waiting on fences in shrinker - Drop use of drm_prime_sg_to_page_array() - a5xx: don't read the GPMU registers on GPUs without a GPMU - a2xx/a3xx/a5xx: hangcheck progress detection - a6xx: gmuwrapper runpm fix - Calculate reported GMEM size based on active slices - Split a6xx/a7xx/a8xx catalog DP: - Picked up some preparation patches for the MST support - Fixed reported status of the link training DPU: - Fixed CRTC bandwidth computation - Fixed DSC programming - Fixed encoder disablement path DSI: - Fixed VM leak in error path - Indention fix MDP5: - Added MSM8952 configuration - Dropped incorrect cursor pipe on MSM8976/56 HDMI: - Small fixes Notes: - Merged qcom-drivers-for-7.4 to pick up UBWC_7_0 support (needed for Hawi/Maili) which in turn depended on qcom-arm64-for-7.4 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV02V-FOzGj71G0ZL7khkYEKWFW4q4biOZR8B8vyWy20PdQ@mail.gmail.com
13 daysdrm/virtio: add ARGB8888 support for primary planesDorinda Bassey
Add DRM_FORMAT_HOST_ARGB8888 to the list of supported formats for virtio-gpu primary planes. Without this, glmark2-drm fails at startup because it selects ARGB visual configs by default, which don't match the XRGB-only plane capabilities. This causes drmModeSetCrtc to fail with EINVAL. The virtio_gpu_translate_format() function already handles ARGB8888 translation to VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM, so this just exposes the existing capability to userspace. Signed-off-by: Dorinda Bassey <dbassey@redhat.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Link: https://patch.msgid.link/20260930132707.500748-1-dbassey@redhat.com
13 daysRevert "drm/virtio: Add pixel blend mode property to cursor plane"Dmitry Osipenko
The cursor blending mode was added twice because the same change was applied by accident from different patches. Revert the second patch. Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/dri-devel/ce84d3d2-e78b-4939-aecf-9ef7267bd42a@samsung.com/ Fixes: 6947b78df4d2 ("drm/virtio: Add pixel blend mode property to cursor plane") Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://patch.msgid.link/20261007222244.295186-1-dmitry.osipenko@collabora.com
2026-10-10drm/msm/a6xx: Split out a7xx/a8xx device tablesRob Clark
This way we can start including generated tables for a8xx GPU snapshot in the device table (without having conflicts with earlier gens if we eventually try to retrofit this approach, or later gens in the future). Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/759096/ Message-ID: <20261010154125.726149-3-robin.clark@oss.qualcomm.com>
2026-10-10drm/msm/a6xx: Move a702/a704 to a6xx listRob Clark
It is a bit more a6xx than a7xx, and this simplifies the next patch. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/759094/ Message-ID: <20261010154125.726149-2-robin.clark@oss.qualcomm.com>
2026-10-10drm/msm/a8xx: report the GMEM size of the active slicesRahul Pon
A8xx GPUs split GMEM evenly between their slices, and parts can have slices fused off: a8xx_gpu_get_slice_info() reads the active slice mask and folds the slice count into the chip ID. The GMEM size reported to userspace (MSM_PARAM_GMEM_SIZE) is still the catalog value for all slices, so on a part with fused-off slices userspace would size its tiles and place its CCU caches past the end of the GMEM that exists. Qualcomm's downstream driver reports GMEM for the active slices: gen8_get_gmem_size() in KGSL divides the GMEM size by the number of physical slices and multiplies it by the number of active ones. Do the same when reading the slice mask. The GMEM protection and UCHE setup still cover the full range, as in KGSL. Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Rahul Pon <theflyingrahul@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/757560/ Message-ID: <20260930183840.1171-1-theflyingrahul@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-10-10rust: drm: Remove unused flags argument from Registration::new()Danilo Krummrich
The flags argument to drm_dev_register() is only passed to the deprecated .load() callback. Rust DRM drivers always set this callback to NULL, so the argument has no effect. Remove the argument from drm::Registration::new(), pass zero to drm_dev_register(), and update the Nova and Tyr callers. Reviewed-by: Alice Ryhl <aliceryhl@google.com> Link: https://patch.msgid.link/20260929190024.2248099-2-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-10-10rust: drm: Return impl PinInit from drm::Registration::new()Danilo Krummrich
Convert drm::Registration to return an impl PinInit<Self, Error> rather than creating a separate allocation. This removes an otherwise unnecessary allocation. Update both in-tree callers (nova, tyr) to construct their bus device private data using try_pin_init!(). Reviewed-by: Alice Ryhl <aliceryhl@google.com> Link: https://patch.msgid.link/20260929190024.2248099-1-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-10-11Merge tag 'amd-drm-next-7.4-2026-10-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-10-08: amdgpu: - Fix direct scanout alpha on some DRM_FORMATs - UserQ fixes - Fix for PSR with tearing flips - GPU reset vblank fix - Debugfs register interface fix - Fix mode patching - Expand Mac reserved memory workaround - GC 12.1 fixes - Clean up MES/HWS vmid mask handling - Make runtime pm more fine grained - A+A SPM fixes - SR-IOV fixes - 3D LUT fixes - HDMI fixes - DCN 4.2 fixes - HDMI VRR fixes - DC tracing fixes - UALink fixes amdkfd: - SDMA doorbell fix - Fix dma-buf reference leak in error path Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20261008212310.2508510-1-alexander.deucher@amd.com
2026-10-11Merge tag 'drm-misc-fixes-2026-10-09' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes A pointer assignment fix for gud, a reference fix and a preallocation size fix for imagination, a suspend fix and an allocation fix when idle for vc4, and a hardware variant fix for nouveau. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <self@mripard.dev> Link: https://patch.msgid.link/asjkbknTHg2t8JGy@houat
2026-10-11Merge tag 'amd-drm-fixes-7.3-2026-10-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-fixes amd-drm-fixes-7.3-2026-10-08: amdgpu: - Fix direct scanout alpha on some DRM_FORMATs - UserQ fixes - Fix tearing flips with PSR - GPU reset vblank fix - Debugfs register interface fix - Fix display mode patching - Expand Mac reserved memory workaround amdkfd: - SDMA doorbell fix - Fix dma-buf reference leak in error path Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20261008174658.2506431-1-alexander.deucher@amd.com
2026-10-11Merge tag 'drm-xe-fixes-2026-10-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Fixes on: - i2c removal (Fan) - system Controller Maibox header handling (Mallesh) - two bo pin/unpin accounting bugs (Thomas) - not emitting a w/a twice (Tvrtko) - xe_mmio_wait32() to honor delay/sleep maximums (Alan) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/asfEfgbIjs0GJ-RF@intel.com
2026-10-09drm/nouveau: prevent NULL deref of gr in GETPARAM_GRAPH_UNITSZhenhao Wan
nouveau_abi16_ioctl_getparam() fetches the graphics engine with gr = nvxx_gr(drm) (i.e. drm->nvkm->gr) and, for the NOUVEAU_GETPARAM_GRAPH_UNITS parameter, passes it straight to nvkm_gr_units(), which dereferences gr->func with no NULL check. When graphics-engine construction returns -ENODEV, NVKM treats it as an optional absent engine: the NVKM_LAYOUT_ONCE device constructor deletes the subdevice, leaves device->gr == NULL and continues probing, and Nouveau still registers a render node. An unprivileged client holding a /dev/dri/renderD* fd can then issue DRM_IOCTL_NOUVEAU_GETPARAM with NOUVEAU_GETPARAM_GRAPH_UNITS and oops the kernel on the NULL gr. Report 0 units when gr is absent. This matches nvkm_gr_units() itself, which already returns 0 when the engine exposes no units callback. Reported-by: Yuhao Jiang <danisjiang@gmail.com> Assisted-by: LLM Signed-off-by: Zhenhao Wan <whi4ed0g@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20260812-nouveau-nvkm-absent-subdev-null-deref-v1-2-7e057f6aeba0@gmail.com
2026-10-09drm/panthor: Fix TOCTOU race between GROUP_REGISTERED check and eraseOsama Abdelkader
panthor_group_destroy() checks the GROUP_REGISTERED mark and then calls xa_erase() without holding the xarray lock across both. If the handle is destroyed by another thread in between, and a concurrent GROUP_CREATE reuses the freed ID, the first destroy erases and releases the new, still-initializing group, leading to a use-after-free in panthor_group_create(). Do the mark check and erase atomically under xa_lock(). Fixes: eec7e23d848d ("drm/panthor: Prevent potential UAF in group creation") Assisted-by: Claude:claude-opus-5.5 Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Osama Abdelkader <osama.abdelkader@gmail.com> Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patch.msgid.link/20261008100935.3059587-1-osama.abdelkader@gmail.com
2026-10-09drm/ttm: return an error when kmapping a BO without pagesJesse Zhang
ttm_tt objects for imported sg tables (ttm_bo_type_sg, set up by ttm_sg_tt_init() with TTM_TT_FLAG_EXTERNAL) only have DMA addresses and no pages array. ttm_bo_kmap() and ttm_bo_vmap() still dereference ttm->pages for them, so a driver that tries to CPU map such a BO oopses instead of getting an error: BUG: kernel NULL pointer dereference, address: 0000000000000000 RIP: 0010:ttm_bo_kmap+0x26c/0x300 [ttm] Call Trace: amdgpu_bo_kmap+0x89/0xb0 [amdgpu] amdgpu_userq_fence_read_wptr+0x116/0x170 [amdgpu] amdgpu_userq_signal_ioctl+0x3fe/0xbb0 [amdgpu] Return -EINVAL in that case, like ttm_bo_kmap_try_from_panic() already checks for a missing pages array. Fixes: 75a57669cbc8 ("drm/ttm: add ttm_sg_tt_init") Cc: stable@vger.kernel.org Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Link: https://patch.msgid.link/20261009103419.4122940-1-Jesse.Zhang@amd.com
2026-10-09Merge tag 'drm-intel-next-2026-10-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next [airlied: add xe fixup] - Vswing / Pre-emphasis Override (Michal) - Enable AS SDP Skip Frames (Uma) - Handle negative configuration index on DP link caps for robustness (Luca) - Perform full wedge on display reset (Ville) - PSR related revert and fix (Nemesa) - Preparation for enabling SDR plane color pipeline (Chaitanya, Pranay) - An eDP quirk for HP Pavilion Plus (Ankit) - DP MST fixes (Imre) - General display fixes and small improvements (Jani, Lalit, Vinod, Sebastian) - Introduce PME (Power Management Event) support on display hotplug (Vinod) - Force eDP sink awake on dpcd init (Arun) - Stop using the configurable fence timeout and other cleanups (Jani) - Add support for Common SDP Transmission Line (Ankit, Arun) - Map AUX power domains to DC_off (Suraj) - Handle VSC SDP revision 7 in unpack (Juasheem) - Disable VRR DC balance by default (Mitul) - Switch to modern drm_dp_dpcd* accessors (Jani) - Lg DPCD access errors (Suraj) - Fixes to make i915 work well with PREEMPT_RT (Maarten, Sebastian) - Update the CMN_SDP_TL in fastset path (Ankit) - Use a shared gtt_view_types.h header (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/asAD6RRGxlbIPdhz@intel.com
2026-10-09drm/bridge: simple: add Chrontel CH7218AXilin Wu
The Chrontel CH7218A automatically boots its embedded firmware and operates without host-side configuration. Add the CH7218A to the simple bridge driver and expose its output as an HDMI Type-A connector. Tested-by: Daniele Briguglio <hello@superkali.me> Signed-off-by: Xilin Wu <sophon@radxa.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20261009-q8b-dts-v2-2-eda11e5dea8b@radxa.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-10-09BackMerge tag 'v7.3-rc6' into drm-nextDave Airlie
Linux 7.3-rc6 This was requested by Thomas to have a new base to start some branch from Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-10-08drm/nouveau: Skip the Turing CE workaround object for non-GR channelsMary Guillemard
This workaround is here for the old Gallium driver and predate async CE and NVDEC. Instead of only skipping it for NVDEC, let's only apply it in case of GR channels. This should make async CE work properly on Turing by stopping the assign of a GRCE. (here CE0) Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20261007-turing-async-ce-fix-v1-1-12ee6ccd1a3c@mary.zone
2026-10-08drm/vc4: Fix binner slot allocation failing on an idle GPUMaíra Canal
A job's binner slots are returned to bin_alloc_used by vc4_complete_exec(), which runs from the job_done workqueue, but the seqno vc4_v3d_get_bin_slot() waits on is incremented earlier, in the function vc4_irq_finish_render_job(). Therefore, a waiter can wake, retry, and still find the pool full because the worker has not run. By then, the job might have left the render_job_list, so no seqno remains to wait on and the allocation fails returning -ENOMEM. This scenario can be reproduced on a Raspberry Pi 3 by using a burst of small jobs (e.g. Piglit's `quick_gl` suite), with userspace seeing a rejected submit for a pool about to become free. Note that the slots are held from validation until the render completes, so the pool can also be exhausted by jobs still queued on bin_job_list, leaving render_job_list empty and nothing to wait on. Release the slots from the FRDONE handler and wait on the pool instead of on one job's seqno. This bounds the wait to the actual resource. Also, by claiming the slot inside the wait condition, another submit is unable to take the slot between the wakeup and the retry. vc4_complete_exec() keeps clearing the slots for jobs that never completed, and now wakes the waiters too. Note that the wait takes a deadline, since the two callers need different ones. The submit path is a user task and can be interrupted, so it waits without one. On the other hand, vc4_overflow_mem_work() runs on a worker and never sees a signal, so it needs a deadline. During a reset, vc4_irq_disable() masks V3D_DRIVER_IRQS before draining the worker, and with those masked nothing can release a slot. This deadlocks: the worker would wait for slots that only the reset can free, while the reset waits in cancel_work_sync() for the worker. Fixes: 553c942f8b2c ("drm/vc4: Allow using more than 256MB of CMA memory.") Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Link: https://patch.msgid.link/20260930182204.1877361-1-mcanal@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-10-08drm/vc4: Disable the V3D interrupt across runtime suspendMaíra Canal
vc4_irq_disable() masks the V3D interrupt sources and then calls synchronize_irq() before the V3D is powered down. However, by itself, this is not enough to quiesce the interrupt handler. synchronize_irq() waits for handlers that have already set IRQD_IRQ_INPROGRESS, and for irqchips reporting IRQCHIP_STATE_ACTIVE. A GIC interrupt chip is able to mark an interrupt active as soon as a CPU acknowledges it, so there these checks cover the whole dispatch path. On RPi 0-3, however, the interrupt controller is ARMCTRL, which has no active state. A CPU that has read the hwirq out of the pending register but has not yet reached handle_level_irq() stays invisible to synchronize_irq(). During a power transition, vc4_irq() may therefore run after the power domain is off, where every V3D register read will return 0xdeadbeef. 0xdeadbeef has FLDONE, FRDONE and OUTOMEM set. This problem doesn't trigger NULL pointer dereference issues only because the functions vc4_irq_finish_bin_job() and vc4_irq_finish_render_job() return early when there is no job pointer, but OUTOMEM is still able to schedule vc4_overflow_mem_work() after vc4_irq_disable() has already cancelled it. Therefore, fix the spurious interrupts by disabling the interrupt line across the PM transition. To preserve the enable/disable balance, move vc4_irq_install() and request the IRQ line disabled before the first runtime resume. Fixes: 9b6f461582e6 ("drm/vc4: v3d: Stop disabling interrupts") Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Link: https://patch.msgid.link/20260925191318.541938-1-mcanal@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-10-09Merge tag 'drm-intel-fixes-2026-10-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes drm/i915 fixes for v7.3-rc7: - Fix a GT park race that could trigger spurious RPM wakelock warnings - Fix execbuffer relocation cleanup to avoid out-of-bounds free Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/49ac4a9f496e1dadbf71740eb0d1f443598b2632@intel.com
2026-10-08drm/imagination: Size page table preallocation by device addressGyeyoung Baek
Commit 0a8224058a58 ("drm/imagination: Fix page count for page table for map() interface") passed the device address to pvr_mmu_op_context_create(), but the preallocation is still sized from device_addr + sgt_offset with an exclusive end. The offset into the object's pages has no place in a device-virtual range, and the exclusive end allocates one table too many when the range ends on a table boundary. Count the tables from device_addr and the inclusive end of the range. The new calculation does not take page table indices into account. This fixes another issue with the previous implementation, where the difference between start and end indices could underflow when a mapping crossed a page table boundary. This would lead to the driver preallocating a huge number of MMU pages, exhausting system memory and triggering an out of memory panic. Fixes: 0a8224058a58 ("drm/imagination: Fix page count for page table for map() interface") Fixes: ff5f643de0bf ("drm/imagination: Add GEM and VM related code") Signed-off-by: Gyeyoung Baek <gye976@gmail.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Reviewed-by: Alessio Belle <alessio.belle@imgtec.com> Cc: stable@vger.kernel.org [Alessio: add paragraph to point out OOM bug being fixed, cc stable] Link: https://patch.msgid.link/20261001-pvr-fixes-a-v2-2-f58254e5dfb8@gmail.com Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
2026-10-08drm/imagination: Fix reference and vm_bo handling in remap()Gyeyoung Baek
When a map overlaps part of an existing mapping, pvr_vm_gpuva_remap() splits the mapping into prev/next parts covering what the request did not take, instead of creating something new. It gets two things wrong. - A GEM reference is taken for each part but it's never needed and never dropped, so it leaks one reference per split (remap-next-in-2m in tests/imagination/pvr_vm_map.c): CRITICAL: 33558528 bytes of shmem still held after close - The parts still belong to the original object being split, but pvr_vm_gpuva_remap() links them to ctx->gpuvm_bo, the new object's vm_bo: prev_va --obj--> BO_A BO_B <--obj-- vm_bo (ctx->gpuvm_bo) \___________link___________/ (mismatch: BO_A != BO_B) drm_gpuva_link() catches the mismatch: WARNING: drivers/gpu/drm/drm_gpuvm.c:2108 at drm_gpuva_link+0x2ec/0x310 drm_WARN_ON(obj != vm_bo->obj) Call trace: drm_gpuva_link pvr_vm_gpuva_remap __drm_gpuvm_sm_map pvr_vm_map pvr_ioctl_vm_map Link them to op->remap.unmap->va->vm_bo instead. The locking of the GPUVA lists of the other objects touched by a split is not addressed here; it is handled by switching the GPUVM to immediate mode. Fixes: ff5f643de0bf ("drm/imagination: Add GEM and VM related code") Signed-off-by: Gyeyoung Baek <gye976@gmail.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20261001-pvr-fixes-a-v2-1-f58254e5dfb8@gmail.com Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
2026-10-07drm/amdgpu: make Mac FB workaround genericAlex Deucher
Rather than adding a case of every chip where this is seen just check if the FB is at 0 and the ssid is apple. This should cover all chips which fall into this case. Tested-by: Ayhan Çiçek <ayhancicek@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit c54e4d10507722398dc90cf3c532e50b86cf425a) Cc: stable@vger.kernel.org
2026-10-07drm/amdkfd: fix dma_buf reference leak in get_dmabuf_infoHaojie Li
When kzalloc fails for metadata_buffer in amdgpu_amdkfd_get_dmabuf_info(), the function returns -ENOMEM directly without calling dma_buf_put(), leaking the dma_buf reference obtained earlier via dma_buf_get(). Fix both issues by: - Adding an error check after the first amdgpu_bo_get_metadata() call - Replacing the direct return with r = -ENOMEM and goto out_put to ensure dma_buf_put() is called on all error paths Fixes: f54ce9e8cbd3 ("drm/amdkfd: Let driver decide buffer size at AMDKFD_IOC_GET_DMABUF_INFO ioctl") Signed-off-by: Haojie Li <lihaojie@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ffa699553332f8caf8688d312279ddcea9e3c141) Cc: stable@vger.kernel.org
2026-10-07drm/amd/display: Don't replace a sink mode that shares the native totalsAdrian Betschart
decide_crtc_timing_for_drm_display_mode() copies the native mode's CRTC timing into the requested mode when clock, htotal and vtotal match. That is meant for the modes amdgpu inserts itself: amdgpu_dm_create_common_mode() duplicates the native mode and changes only hdisplay and vdisplay, so those are sent with the native timing and scaled. A sink can also offer a real mode with the same clock and totals as its native mode. CTA-861 VIC 102 (4096x2160@60) and VIC 97 (3840x2160@60) both use 594 MHz and 4400x2250. With 3840x2160@60 as the preferred mode, a 4096x2160@60 request goes out with the 3840x2160 timing and the framebuffer scaled into it (dst 3840x2025 at y=67), while the AVI InfoFrame still carries VIC 102. A JVC projector then reports 3840x2160 and shows a corrupted right edge. 4096x2160@24, whose totals differ, is sent and displayed correctly. Inserted modes keep the native sync positions; a real mode with its own active width does not. Compare those too, so only inserted modes are patched. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Adrian Betschart <adrian.betschart@cinemaone.ch> Assisted-by: Claude-Code:claude-opus-5-5 Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 22f9a2da101c37f821cd00954f81dc598754f4d5) Cc: stable@vger.kernel.org
2026-10-07drm/amdkfd: align SDMA doorbell base for shader doorbell writesSaleel Kudchadker
On GC 9.4.3, 9.4.4 and 9.5.0, doorbell writes issued from shaders are routed to an SDMA engine at 32-byte (4 doorbell index) granularity. SDMA engine doorbell ranges are 10 indices apart, so the range of every odd engine starts 2 indices into a 4-index block that begins in the previous engine's range. A shader ringing the doorbell of a queue on an odd engine therefore rings the previous engine instead. The intended queue never sees the doorbell, so its work stalls and the application hangs. Align the per-engine doorbell base up to a 4-index boundary on these ASICs. Each engine only uses 4 of its 10 indices, so the aligned base plus the queue offset stays within the engine's range. Even engines are already aligned, so only the doorbell IDs of odd-engine queues change. Only doorbells rung by the device itself are routed this way. Doorbell writes from the host, including the kernel's own SDMA rings, are not affected. The doorbell ID of an SDMA queue is saved in CRIU checkpoints and checked again on restore. A checkpoint taken before this change that contains an SDMA queue on an odd engine will fail to restore with -EINVAL. This is intentional: the restored process still holds the old doorbell address, so accepting the stale ID would bring back the same stall. Tested on MI300X with a shader-rung SDMA doorbell test: queues on odd engines hung before this change and complete with it. v2: use u32 instead of uint32_t for the new locals (checkpatch) v3: name the routing granularity, use dev->node_id, document the layout invariants, describe impact v4: express the granularity in doorbell indices, drop unrelated cleanups, explain the CRIU restore behavior, add test note Fixes: 6df442a03d1a ("drm/amdgpu: add new doorbell assignment table for aqua_vanjaram") Signed-off-by: Saleel Kudchadker <Saleel.Kudchadker@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ee1379e6d7da47bdf7a8d5b89c2d1b28473701fb) Cc: stable@vger.kernel.org
2026-10-07drm/amdgpu: copy debugfs register data outside the GRBM/SRBM locksMikhail Gavrilov
Reading or writing a register through the amdgpu_regs2 debugfs file with GRBM bank selection, which umr does for every banked access (a single "umr -b x x x -r <reg>" is enough, as is the wave dump with "-O halt_waves"), makes lockdep report a circular locking dependency, after which lockdep stays off until reboot: WARNING: possible circular locking dependency detected umr/63306 is trying to acquire lock: ffff8882cf4b8350 (&mm->mmap_lock){++++}-{4:4}, at: __might_fault+0x9b/0x140 but task is already holding lock: ffff8881aec010d0 (&amdgpu_grbm_lock_key){+.+.}-{4:4}, at: amdgpu_debugfs_regs2_op.isra.0+0x20d/0xd00 [amdgpu] ... Chain exists of: &mm->mmap_lock --> &amdgpu_srbm_lock_key --> &amdgpu_grbm_lock_key ... __might_fault+0xc5/0x140 amdgpu_debugfs_regs2_op.isra.0+0x441/0xd00 [amdgpu] full_proxy_write+0x10e/0x1d0 vfs_write+0x1d0/0xf50 ksys_write+0x116/0x250 amdgpu_debugfs_regs2_op() and amdgpu_debugfs_process_reg_op() call get_user()/put_user() for every dword while holding grbm_idx_mutex or srbm_mutex, and pm.mutex if requested, so a fault there takes mmap_lock inside those locks. The lock hierarchy in amdgpu_lockdep.c puts srbm_mutex and grbm_idx_mutex below notifier_lock, which amdgpu_cs_submit() takes with the BO reservations held, and dma_resv_lockdep() orders the reservations inside mmap_lock. So mmap_lock is outside grbm_idx_mutex and srbm_mutex, and these two debugfs paths nest it the other way round. The copies under the locks are as old as the bank selection in both files; commit 1d0f5838b126 ("drm/amdgpu: Add lockdep annotations for lock ordering validation") only made them visible to lockdep. Copy the user buffer in before any of the locks is taken and the result out after all of them are dropped, as amdgpu_debugfs_wave_read(), amdgpu_debugfs_gpr_read() and amdgpu_debugfs_gprwave_read() already do. The buffer is sized by the count passed to read() or write(), so an access larger than PAGE_SIZE is now rejected with -EINVAL; umr reads and writes one register at a time. A fault on the user buffer of a write now fails with -EFAULT before any register is written, instead of after a partial write. Fixes: 566281595037 ("drm/amd/amdgpu: Add bank selection for MMIO debugfs (v3)") Fixes: 37df9560cd3e ("drm/amd/amdgpu: New debugfs interface for MMIO registers (v5)") Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ccf9e35ed6811f2c25ba6368e7dc6481da17159d) Cc: stable@vger.kernel.org
2026-10-07drm/amdgpu: serialize vblank counter reads against GPU resetVitaly Prosyak
The vblank counter callback reads display registers and scanout position without holding reset_domain->sem. During GPU recovery, display commit work can call the callback while reset owns the semaphore for writing. The hardware access then triggers the lockdep_assert_held() in amdgpu_device_skip_hw_access() and sets TAINT_WARN when lockdep is enabled. Try to acquire the reset semaphore for reading before accessing the hardware, and hold it across the counter and scanout-position reads. If reset is already in progress, return DRM's cached software vblank count instead. This avoids blocking behind reset and avoids accessing display hardware while it is being reset. The cached count is less accurate than the hardware count, but is used only when reset prevents a safe hardware read. This addresses the reset-time warning from this vblank path; it does not suppress or fix unrelated lockdep warnings. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 51a4359f7431a4be5e42803c8bdaf7e0e5be2934) Cc: stable@vger.kernel.org
2026-10-07drm/amd/display: disable self-refresh on tearing flipsLeo Li
[Why & How] Immediate (tearing) flips breaks self refresh state machine assumptions, so disable PSR/Replay for them. Tested-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit acbdd213b37e095f15685f3e3ee6d35defa05616) Cc: stable@vger.kernel.org
2026-10-07drm/amdgpu/userq: return the memdup_user() error for the user MQDJesse Zhang
mes_userq_mqd_create() returns -ENOMEM when copying the user MQD fails, even though memdup_user() returns -EFAULT for a bad pointer or -EINTR when interrupted by a signal. Return PTR_ERR() instead. While at it drop the error messages. Neither case is a driver error and userspace shouldn't be able to spam the log with invalid IOCTL parameters. v2: drop the error messages (Christian) Fixes: 2c695d7c0720 ("drm/amdgpu: enable compute/gfx usermode queue") Fixes: 543b61453774 ("drm/amdgpu: enable SDMA usermode queues") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 49a443fcb829be9fc780f10850652ddea2fe81f0) Cc: stable@vger.kernel.org
2026-10-07drm/amdgpu/userq: only accept doorbell BOs as queue doorbellJesse Zhang
amdgpu_userq_get_doorbell_index() pins any BO passed as doorbell_handle into the doorbell domain. For a regular BO, TTM moves it with ttm_bo_move_null() and its contents are lost. Since an importer on the same device gets the exporter's GEM object, a client can do this to a buffer another client shared with it. Reject BOs that were not created in the doorbell domain. v2: drop the error message, use a local abo variable (Christian) Fixes: f09c1e6077ab ("drm/amdgpu: generate doorbell index for userqueue") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit f7497bbc19db4821c62b9d97b31c9086feb2d917) Cc: stable@vger.kernel.org
2026-10-07drm/amd/display: Fix direct scanout alpha on some DRM_FORMATsLeo Li
[Why] DM was declaring it's own list of has_alpha DRM formats to check against for enabling alpha blending, when the format->has_alpha already does that for us. The self-declared list missed some has_alpha formats, causing direct-scanout planes with such formats to appear opaque. [How] Drop the self-declared list, instead use the format->has_alpha field directly. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 9ecdac91ed43d836683d5daa467f4907405420e2) Cc: stable@vger.kernel.org
2026-10-07drm/amdgpu: make Mac FB workaround genericAlex Deucher
Rather than adding a case of every chip where this is seen just check if the FB is at 0 and the ssid is apple. This should cover all chips which fall into this case. Tested-by: Ayhan Çiçek <ayhancicek@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdkfd: fix dma_buf reference leak in get_dmabuf_infoHaojie Li
When kzalloc fails for metadata_buffer in amdgpu_amdkfd_get_dmabuf_info(), the function returns -ENOMEM directly without calling dma_buf_put(), leaking the dma_buf reference obtained earlier via dma_buf_get(). Fix both issues by: - Adding an error check after the first amdgpu_bo_get_metadata() call - Replacing the direct return with r = -ENOMEM and goto out_put to ensure dma_buf_put() is called on all error paths Fixes: f54ce9e8cbd3 ("drm/amdkfd: Let driver decide buffer size at AMDKFD_IOC_GET_DMABUF_INFO ioctl") Signed-off-by: Haojie Li <lihaojie@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: exclude npa_vmid from the userq vmids tooSunil Khatri
On IP_VERSION(12, 1, 0), we are excluding vmid 15 from the available vmids in kernel queues for mmhub but its not exluded from the userqueues mmhub vmids and it is a problem. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: only clear the hotplug sources the ASIC hasMattia Tadini
amdgpu_dm_hpd_init() clears every hotplug source in the enum before enabling the ones it needs: for (i = DC_IRQ_SOURCE_HPD1; i <= DC_IRQ_SOURCE_HPD6RX; i++) DC fills the unused slots of its interrupt table with dummy handlers that assert when touched, so on an ASIC with fewer than six HPD lines that sweep warns and taints the kernel. DCN 2.0.1 has two: mmHPD0_DC_HPD_INT_CONTROL and mmHPD1_DC_HPD_INT_CONTROL are the only hotplug registers in dcn_2_0_1_offset.h, against five in dcn_2_1_0_offset.h, and irq_service_dcn201.c defines hpd_int_entry(0) and (1) accordingly. On an AMD BC-250, which appears to be the only GPU using DCN 201, every boot produces this for sources 3 to 6: [drm] *ERROR* dal_irq_service_dummy_ack: called for non-implemented irq source, src_id=0, ext_id=0 [drm] dal_irq_service_set: src: 3, st: 0 WARNING: .../display/dc/irq/irq_service.c:129 at dal_irq_service_set.cold+0x2d/0x76 [amdgpu] dal_irq_service_set+0x4c/0x100 [amdgpu] amdgpu_dm_hpd_init.cold+0x15/0x12e [amdgpu] dm_hw_init+0x4c/0x170 [amdgpu] amdgpu_device_init.cold+0x1727/0x1ec0 [amdgpu] and the machine comes up tainted W, which makes every unrelated bug report from it harder to read. Walk the links this ASIC has instead of the whole enum, and skip a link with no hotplug line of its own, which is the same guard the enable loop further down already applies. A source owned by a real link is implemented by definition, so the dummy handlers are no longer reached. Parts with six HPD lines are unaffected. Signed-off-by: Mattia Tadini <info@mtsistemi.it> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Don't replace a sink mode that shares the native totalsAdrian Betschart
decide_crtc_timing_for_drm_display_mode() copies the native mode's CRTC timing into the requested mode when clock, htotal and vtotal match. That is meant for the modes amdgpu inserts itself: amdgpu_dm_create_common_mode() duplicates the native mode and changes only hdisplay and vdisplay, so those are sent with the native timing and scaled. A sink can also offer a real mode with the same clock and totals as its native mode. CTA-861 VIC 102 (4096x2160@60) and VIC 97 (3840x2160@60) both use 594 MHz and 4400x2250. With 3840x2160@60 as the preferred mode, a 4096x2160@60 request goes out with the 3840x2160 timing and the framebuffer scaled into it (dst 3840x2025 at y=67), while the AVI InfoFrame still carries VIC 102. A JVC projector then reports 3840x2160 and shows a corrupted right edge. 4096x2160@24, whose totals differ, is sent and displayed correctly. Inserted modes keep the native sync positions; a real mode with its own active width does not. Compare those too, so only inserted modes are patched. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Adrian Betschart <adrian.betschart@cinemaone.ch> Assisted-by: Claude-Code:claude-opus-5-5 Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: Fix NPA-REVOKE racing an in-flight UALink importDavid Carlier
The exporter records an importer when it answers NPA-REQ, so it can send NPA-REVOKE as soon as the BO is freed, before the importer has finished building the dma-buf for that handle. The revoke handler assumes a fully imported node: it dereferences imp_xa_node->dmabuf, which is still NULL until the import completes, and drops the xarray reference the importing thread still relies on. The importer then links the node and marks it READY regardless, so the node can be freed while still on the per-remote list. Only tear down a node that is READY. A PENDING node is still being imported and nothing has been handed to user-space yet, so only mark it for teardown and send NPA-RELEASE. The importer checks for teardown under the xarray lock before linking the node and marking it READY, and unwinds otherwise. As NPA-REVOKE always follows NPA-RSP, a revoke that finds the node NOT_READY is stale, and one that finds it in teardown hits a node that is already being released, so both are ignored. Fixes: 7cc82cd90d35 ("drm/amdgpu: Implement mechanism to revoke exported memory") Assisted-by: LLM Signed-off-by: David Carlier <devnexen@gmail.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: copy function name into dcn_optc_lock_unlock_state trace eventMelissa Wen
Userspace trace tools that use libtraceevent to read binary buffer only see a kernel address when printing const char *. Use string macros in dcn_optc_lock_unlock_state to copy the function name into the trace event. Fixes: f1943a51f0f9 ("drm/amd/display: Add events log to trace OPTC lock and unlock") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Melissa Wen <mwen@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: copy function name into dcn_fpu trace eventMelissa Wen
Userspace trace tools that use libtraceevent to read binary buffer only see a kernel address when printing const char *. Use string macros in dcn_fpu to copy the function name into the trace event. Fixes: 96ee63730fa3 ("drm/amd/display: Add control mechanism for FPU") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: remove redundant cast on amdgpu_dc_reg_template printkMelissa Wen
Commit 0cf5eb76e2b4 ("drm/amd/display: Add tracing to dc") prints and casts uint32_t fields in amdgpu_dc_reg_template to unsigned long unnecessarily. Just print those fields with %08x and remove the redundant cast. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: use right type for amdgpu_dc_performance event entriesMelissa Wen
Some amdgpu_dc_performance trace event params are passed as unsigned long but stored as uint32_t, cutting them off on 64-bit. Use the right type on entry fields and on printk use unsigned format accordingly. Fixes: 0cf5eb76e2b4 ("drm/amd/display: Add tracing to dc") Signed-off-by: Melissa Wen <mwen@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: declare amdgpu_dm_atomic_state_template as an event classMelissa Wen
Don't create an amdgpu_dm_atomic_state_template event since this is just a template. Declare the template as an event class that will be used by actual event tracers. Fixes: e8a982355f96 ("drm/amd/display: Add tracepoint for amdgpu_dm") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: fix vready offset assignment in dcn_optc_lock_unlock_stateMelissa Wen
vready_offset is captured by optc_state, but the trace point entry is wrongly assigned to vupdate_offset. Fix vready_offset tracepoint field in dcn_optc_lock_unloack_state to record optc_state->vready_offset. Fixes: f1943a51f0f9 ("drm/amd/display: Add events log to trace OPTC lock and unlock") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: remove duplicated prev_p_state_change_support assignmentMelissa Wen
The prev_p_state_change_support trace entry is assigned and printed twice, remove the unnecessary duplicates. Fixes: 13b5ca42ca9c ("drm/amd/display: Add tracepoint for capturing clocks state") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: assign missing trace entry in amdgpu_dm_dc_clocks_stateMelissa Wen
disp_dpp_voltage_level_khz is declared and printed, but never assigned. So when using clock tracepoint the value of this clock is just garbage. Assign clk->disp_dpp_voltage_level_khz since this is stored in dc_clocks as other entries. Fixes: 13b5ca42ca9c ("drm/amd/display: Add tracepoint for capturing clocks state") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Promote DC to 3.2.401Ashwin Santhosh
This version brings along the following updates: - Add HDMI RR and SCDC skips. - Add debug option to override low power SR latencies. - Allow skipping link bandwidth clear. - Handle virtual link encoder. - Improve MCM shaper/3DLUT programming and DTN logging. - Only reprogram DRR when v_total values change. - Refactor DMUB fast lock sequencing. - Send HDMI VRR metadata in VTEM info packet slot. - Set cursor_offload for all pipes for a given stream. - Skip link off frame count for general UI. - Update link training no timeout behaviour on HDMI. Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Send HDMI VRR metadata in VTEM info packet slotIvan Lipski
[Why] Brief blank on HDMI each time VRR engaged and disengaged, with no modeset at either transition. amdgpu_dm_update_freesync_state_on_stream() built the VTEM on top of the buffer holding the AMD FreeSync SPD payload, which becomes stream->vrr_infopacket. DC routes that to HDMI generic slot 3 (SPD) and vtem_infopacket to slot 6 (VTEM), and vtem_infopacket was never populated. So slot 3 carried a VTEM payload the sink parsed as an SPD InfoFrame, no VTEM was sent, and v_total varied with no valid metadata describing it. DP uses the VSC/AS-SDP path and is unaffected. [How] Build the VTEM into a separate vtem_infopacket, gated on the sink not advertising AMD FreeSync. Track it in dm_crtc_state, include it in the freesync_vrr_info_changed comparison and the reset path, and pass it through bundle->stream_update.vtem_infopacket. Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-10-25 00:25:00 +0000