summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm
AgeCommit message (Collapse)Author
2025-10-30drm/i915/display: Add filter lut valuesNemesa Garg
Add the register bits related to filter lut values and helper to load the casf filter lut. These values are golden values and these value has to be loaded one time while enabling the casf. v2: update commit message[Ankit] v3: Add intel_casf prefix to filter_load fn[Jani] v4: Define the filter macros here Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251028120747.3027332-5-ankit.k.nautiyal@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30drm/i915/display: Add CASF strength and winsizeNemesa Garg
Add register definitions for sharpness strength and filter window size used by CASF. Provide functions to read and write these fields. The sharpness strength value is determined by user input, while the winsize is based on the resolution. The casf_enable flag should be set if the platform supports sharpness adjustments and the user API strength is not zero. Once sharpness is enabled, update the strength bit of the register whenever the user changes the strength value, as the enable bit and winsize bit remain constant. Introduce helper to enable, disable and update strength. Add relavant strength and winsize in both enable and disable. v2: Introduce get_config for casf[Ankit] v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit] v4: After updating strength add win_sz register v5: Replace u16 with u32 for total_pixel v6: Add casf logging v7: Add helper for enable and disable casf Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251028120747.3027332-4-ankit.k.nautiyal@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30drm/i915/display: Introduce HAS_CASF for sharpness supportNemesa Garg
Add HAS_CASF macro to check whether platform supports the content adaptive sharpness capability or not. v2: Update commit message[Ankit] v3: Remove \n from middle[Jani] v4: Remove the logging part Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251028120747.3027332-3-ankit.k.nautiyal@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30drm/drm_crtc: Introduce sharpness strength propertyNemesa Garg
Introduce a new crtc property "SHARPNESS_STRENGTH" that allows the user to set the intensity so as to get the sharpness effect. The value of this property can be set from 0-255. It is useful in scenario when the output is blurry and user want to sharpen the pixels. User can increase/decrease the sharpness level depending on the content displayed. v2: Rename crtc property variable [Arun] Add modeset detail in uapi doc[Uma] v3: Fix build issue v4: Modify the subject line[Ankit] Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Tested-by: Adarsh G M <Adarsh.g.m@intel.com> Acked-by: Simona Vetter <simona.vetter@ffwll.ch> Link: https://invent.kde.org/plasma/kwin/-/merge_requests/7689 Link: https://patch.msgid.link/20251028120747.3027332-2-ankit.k.nautiyal@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30drm/i915/display: Take into account AS SDP in intel_dp_sdp_min_guardbandJouni Högander
We started seeing "[drm] *ERROR* Timed out waiting PSR idle state" after taking optimized guardband into use. These are seen because VSC SDPs are sent on same line as AS SDPs when AS SDP is enabled. AS SDP is sent on line configured in EMP_AS_SDP_TL register. We are configuring crtc_state->vrr.vsync_start into that register. Fix this by ensuring AS SDP is sent on line which is within guardband. From the bspec: EMP_AS_SDP_TL < SCL + Guardband v2: check HAS_AS_SDP Bspec: 71197 Fixes: 52ecd48b8d3f ("drm/i915/dp: Add helper to get min sdp guardband") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20251023043140.961104-1-jouni.hogander@intel.com
2025-10-30drm/sti: make use of drm_of_component_probeRaphael Gallais-Pou
Enhance the probing sequence by using the ports property of the display-subsystem node. That done, it becomes possible to handle the display-substem node outside of the soc node within the device-tree and not have each IP blocks as children of the display-subsystem node. Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Acked-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://patch.msgid.link/20250717-sti-rework-v1-2-46d516fb1ebb@gmail.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-10-30drm/sti: check dma_set_coherent_mask return valueRaphael Gallais-Pou
Return value for DMA allocation was not checked. Check it and return error code in case of failing. Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Acked-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://patch.msgid.link/20250717-sti-rework-v1-1-46d516fb1ebb@gmail.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-10-30drm: nova: select NOVA_COREDanilo Krummrich
The nova-drm driver does not provide any value without nova-core being selected as well, hence select NOVA_CORE. Fixes: cdeaeb9dd762 ("drm: nova-drm: add initial driver skeleton") Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20251028110058.340320-2-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-10-30drm: nova: depend on CONFIG_64BITDanilo Krummrich
nova-core already depends on CONFIG_64BIT, hence also depend on CONFIG_64BIT for nova-drm. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20251028110058.340320-1-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-10-29drm/xe/xe3: Apply wa_14024997852Tapani Pälli
Whitelist registers needed for userspace to control autostrip on xe3. v2: fix GRAPHICS_VERSION to match xe3 (Matt) v3: use GRAPHICS_VERSION_RANGE to match all xe3 (Matt) Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251029085057.54210-1-tapani.palli@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-10-29drm: panel: add support for Synaptics TDDI series DSI panelsKaustabh Chakraborty
Synaptics TDDI (Touch/Display Integration) panels utilize a single chip for display and touch controllers. Implement a simple device driver for such panels, along with its built-in LED backlight controller, and add support for TD4101 and TD4300 panels in the driver. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251009-panel-synaptics-tddi-v5-2-59390997644e@disroot.org
2025-10-29drm/panel: Add Samsung S6E3FC2X01 DDIC with AMS641RW panelDavid Heidelberg
Add panel driver used in the OnePlus 6T. No datasheet, based mostly on EDK2 init sequence and the downstream driver. Note: This driver doesn't use previously mentioned "samsung,s6e3fc2x01" by OnePlus 6T device-tree. The reason is because DDIC itself without knowing the panel type used with it will not give the driver enough information about the panel used, as the panel cannot be autodetected. While would be more practical to support the original compatible, I would like to avoid it, to prevent confusing devs upstreaming DDICs. Based on work of: Casey Connolly <casey@connolly.tech> Joel Selvaraj <foss@joelselvaraj.com> Nia Espera <a5b6@riseup.net> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Jessica Zhang <jesszhan0024@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251023-s6e3fc2x01-v5-2-8f8852e67417@ixit.cz
2025-10-29drm/panel: nv3052c: Reduce duplication of init sequencesPriit Laes
Although there are various small changes between the init sequences, the second half is common for all 3 currently supported displays. Note that this is only compile-tested. Signed-off-by: Priit Laes <plaes@plaes.org> Tested-by: John Watts <contact@jookia.org> Reviewed-by: John Watts <contact@jookia.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20250619132211.556027-1-plaes@plaes.org
2025-10-29drm/panel: kingdisplay-kd097d04: Disable EoTpSebastian Fleer
Since commit d97e71e44937 ("drm/bridge: synopsys: dw-mipi-dsi: enable EoTp by default") panel output on an Acer Chromebook Tab 10 (google-dru) is corrupted. The tablet I use is equipped with a kingdisplay-kd097d04 panel, disabling EoTp restores the correct functionality. Fixes: 2a994cbed6b2 ("drm/panel: Add Kingdisplay KD097D04 panel driver") Suggested-by: Jens Reidel <adrian@postmarketos.org> Signed-off-by: Sebastian Fleer <dev@dwurp.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20251029124007.232333-1-dev@dwurp.de
2025-10-29drm/panel: sitronix-st7789v: fix sync flags for t28cp45tn89Sebastian Reichel
I planned to set the polarity of horizontal and vertical sync, but accidentally described vertical sync twice with different polarity instead. Note, that there is no functional change, because the driver only makes use of DRM_MODE_FLAG_P[HV]SYNC to divert from the default active-low polarity. Reported-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Closes: https://lore.kernel.org/all/20250923132616.GH20765@pendragon.ideasonboard.com/ Fixes: a411558cc143 ("drm/panel: sitronix-st7789v: add Inanbo T28CP45TN89 support") Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20251001-t28cp45tn89-fix-v2-1-67fe8e3046ca@collabora.com
2025-10-29drm/xe: Do not wake device during a GT resetMatthew Brost
Waking the device during a GT reset can lead to unintended memory allocation, which is not allowed since GT resets occur in the reclaim path. Prevent this by holding a PM reference while a reset is in flight. Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Cc: stable@vger.kernel.org Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://lore.kernel.org/r/20251022005538.828980-3-matthew.brost@intel.com (cherry picked from commit 480b358e7d8ef69fd8f1b0cad6e07c7d70a36ee4) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-10-29drm/i915/dp_mst: Fix check for FEC support for an uncompressed streamImre Deak
The reason for enabling FEC for an uncompressed stream on an MST link is that the DSC compression is enabled for another stream on the same link. For such an uncompressed stream FEC doesn't need to be supported on the whole path until the (DP-SST) sink DPRX. For instance if a branch device - like a monitor with an MST branch device within it - is plugged to a DFP connector of an MST docking station and the monitor's branch device does not support FEC, the docking station's branch device will still enable the link to the monitor correctly, disabling the FEC on that link as expected. Since it's been verified already that FEC is supported for the compressed stream above, the corresponding check for the uncompressed stream can be dropped: the check for the compressed stream implies already that FEC is supported on the link between the source DPTX and immediate downstream branch device. If FEC is not supported on the whole path until the sink DPRX, FEC will be disabled by a downstream branch device on the path as described above for the MST dock + MST monitor configuration example. This fixes a problem in the above MST dock + MST monitor example, where the dock supports FEC, but the monitor doesn't support it and FEC gets enabled on the link due to DSC getting enabled for another monitor's stream on the same link. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14254 Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251028113536.602352-1-imre.deak@intel.com
2025-10-29drm/xe: Fix uninitialized return value from xe_validation_guard()Thomas Hellström
the DEFINE_CLASS() macro creates an inline function and the init args are passed down to it; since _ret is passed as an int, whatever value is set inside the function is not visible to the caller. Pass _ret as a pointer so its value propagates to the caller. Fixes: c460bc2311df ("drm/xe: Introduce an xe_validation wrapper around drm_exec") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6220 Cc: Maarten Lankhorst <maarten.lankhorst@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: intel-xe@lists.freedesktop.org Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251027131228.12098-1-thomas.hellstrom@linux.intel.com (cherry picked from commit fcb8c304f4673747d535c74b340b5b8a4823727b) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-10-29rust: auxiliary: consider auxiliary devices always have a parentDanilo Krummrich
An auxiliary device is guaranteed to always have a parent device (both in C and Rust), hence don't return an Option<&auxiliary::Device> in auxiliary::Device::parent(). Reviewed-by: Alice Ryhl <aliceryhl@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-10-29drm/xe/xe_debugfs: Expose G7 package state residency counter through debugfsMohammed Thasleem
Add G7 package state residency counter in debugfs alongside existing G2,G6,G8,G10 states for complete power state visibility. Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com> Reviewed-by: Karthik Poosa <karthik.poosa@intel.com> Link: https://patch.msgid.link/20251016001219.37684-1-mohammed.thasleem@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-10-29drm/xe: Fix uninitialized return value from xe_validation_guard()Thomas Hellström
the DEFINE_CLASS() macro creates an inline function and the init args are passed down to it; since _ret is passed as an int, whatever value is set inside the function is not visible to the caller. Pass _ret as a pointer so its value propagates to the caller. Fixes: c460bc2311df ("drm/xe: Introduce an xe_validation wrapper around drm_exec") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6220 Cc: Maarten Lankhorst <maarten.lankhorst@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: intel-xe@lists.freedesktop.org Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251027131228.12098-1-thomas.hellstrom@linux.intel.com
2025-10-29drm/rcar-du: dsi: Convert register bitfields to GENMASK() macroMarek Vasut
Convert register bitfields to GENMASK() macro where applicable. Use FIELD_PREP() throughout the driver. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-12-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Convert register bits to BIT() macroMarek Vasut
Convert register bits to BIT() macro where applicable. This is done automatically using regex 's@(1 << \([0-9]\+\))@BIT(\1)', except for bitfields which are manually updated to use GENMASK(). Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-11-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Clean up handling of DRM mode flagsMarek Vasut
Introduce TXVMVPRMSET0R_BPP_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift, assign this value into vprmset0r. Remove TXVMVPRMSET0R_CSPC_RGB which is never used, replace it with code comment next to TXVMVPRMSET0R_CSPC_YCbCr. Replace (mode->flags & DRM_MODE_FLAG_P.SYNC) test with inverted conditional (mode->flags & DRM_MODE_FLAG_N.SYNC) and bitwise orr vprmset0r with either or both TXVMVPRMSET0R_HSPOL_LOW and TXVMVPRMSET0R_VSPOL_LOW if conditional matches. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-10-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Respect DSI mode flagsMarek Vasut
Cache DSI mode flags in new mode_flags member of struct rcar_mipi_dsi . Configure TXVMSETR register based on the content of DSI mode flags in case the controller operates in video mode. Rename TXVMSETR_H..BPEN_EN to TXVMSETR_H..BPEN and drop TXVMSETR_H..BPEN_DIS which resolves to 0. Update TXVMSETR_VSEN in the same manner. Replace TXVMSETR_SYNSEQ_PULSES with a code comment next to TXVMSETR_SYNSEQ_EVENTS because TXVMSETR_SYNSEQ_PULSES resolves to 0. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-9-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Clean up TXVMPSPHSETR DT macrosMarek Vasut
Introduce TXVMPSPHSETR_DT_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-8-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Clean up CLOCKSET1 CLKINSEL macrosMarek Vasut
Introduce CLOCKSET1_CLKINSEL_MASK macro and remove bitshift from values to make this bitfield usable with FIELD_PREP(). There are no users of this bitfield, hence no updates to the DSI driver. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-7-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Clean up VCLKSET register macrosMarek Vasut
Introduce VCLKSET_BPP_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift. Remove VCLKSET_COLOR_RGB which is never used, replace it with code comment. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-6-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Deduplicate mipi_dsi_pixel_format_to_bpp() usageMarek Vasut
Call mipi_dsi_pixel_format_to_bpp() once in rcar_mipi_dsi_set_display_timing() and store the value into a variable. This slightly simplifies the code. No functional change. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-5-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Document PHTR TESTDOUT as bitfieldMarek Vasut
The register PHTR bitfield TESTDOUT is not a single bit, but a bitfield. Add a MASK macro and a _TEST bitfield value, which is used by the driver to poll for completion. No functional change. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-4-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Document TXVMSETR PIXWDTH as bitfieldMarek Vasut
The register TXVMSETR bitfield PIXWDTH is not a single bit, but a bitfield. Add a MASK macro and document that the only allowed value that can ever be written into the bitfield is the current value, 1. No functional change. Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-3-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/rcar-du: dsi: Fix missing parameter in RXSETR_...EN macrosMarek Vasut
The RXSETR_CRCEN(n) and RXSETR_ECCEN(n) macros both take parameter (n), add the missing macro parameter. Neither of those macros is used by the driver, so for now the bug is harmless. Fixes: 685e8dae19df ("drm/rcar-du: dsi: Implement DSI command support") Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reported-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://patch.msgid.link/20251028232959.109936-2-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-29drm/i915: Add fallback for CDCLK selection when min_cdclk is too highNaladala Ramanaidu
In cases where the requested minimum CDCLK exceeds all available values for the current reference clock, the CDCLK selection logic previously returned 0. This could result coverity division or modulo by zero issue. Introduce a fallback mechanism that returns platform's max_cdclk_freq instead of 0. v2: Update safe fallback value to max cdclk. (Ville) v3: Update commit messgae (Mika) Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20251017150526.781715-1-ramanaidu.naladala@intel.com
2025-10-28drm/xe: Limit number of jobs per exec queueShuicheng Lin
Add a limit to the number of jobs that can be queued in a single exec queue to avoid potential resource exhaustion. A new field `job_cnt` is introduced in `struct xe_exec_queue` to track the number of active DRM jobs, along with a maximum limit `XE_MAX_JOB_COUNT_PER_EXEC_QUEUE` set to 1000. If the job count exceeds this threshold, `xe_exec_ioctl()` now returns `-EAGAIN` to signal that the caller should retry later. A trace event is added to track when the limit is reached: "xe_exec_queue_reach_max_job_count: dev=0000:03:00.0, job count exceeded the maximum limit (1000) per exec queue. engine_class=0x3, logical_mask=0x1, guc_id=2" v3: add assert in xe_exec_queue_destroy that q->job_cnt is zero. (Matt) v2 (Matt): - add log to trace the limit is hit. - Change max count from 0x1000 to 1000. - Use atomic_t for job_cnt. Suggested-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251027202118.3339905-2-shuicheng.lin@intel.com
2025-10-29drm/msm/dpu: Fix adjusted mode clock check for 3d mergeJessica Zhang
Since 3D merge allows for larger modes to be supported across 2 layer mixers, filter modes based on adjusted mode clock / 2 when 3d merge is supported. Reported-by: Abel Vesa <abel.vesa@linaro.org> Fixes: 62b7d6835288 ("drm/msm/dpu: Filter modes based on adjusted mode clock") Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/676353/ Link: https://lore.kernel.org/r/20250923-modeclk-fix-v2-1-01fcd0b2465a@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm/dpu: Disable broken YUV on QSEED2 hardwareVladimir Lypak
YUV formats on this hardware needs scaling for chroma planes. However it is not implemented for QSEED2 which breaks display pipeline if YUV format is used (causing partial and corrupted output with PPDONE timeouts). This patch temporarily disables YUV by switching affected sub-block to RGB only format list. Fixes: daf9a92daeb8 ("drm/msm/dpu: Add support for MSM8996") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/682061/ Link: https://lore.kernel.org/r/20251018-b4-dpu-fixes-v1-6-1852278064d0@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm/dpu: Require linear modifier for writeback framebuffersVladimir Lypak
UBWC-related register configuration for writeback is not implemented in the driver yet but there aren't any checks for non-linear modifiers in atomic_check. Thus when compressed framebuffer is attached to writeback connector it will be filled with linear image data. This patch forbids non-linear modifiers for writeback framebuffers until UBWC support for writeback is properly implemented. Fixes: 71174f362d67 ("drm/msm/dpu: move writeback's atomic_check to dpu_writeback.c") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/681922/ Link: https://lore.kernel.org/r/20251017-b4-dpu-fixes-v1-5-40ce5993eeb6@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm/dpu: Fix pixel extension sub-samplingVladimir Lypak
In _dpu_plane_setup_pixel_ext function instead of dividing just chroma source resolution once (component 1 and 2), second component is divided once more because src_w and src_h variable is reused between iterations. Third component receives wrong source resolution too (from component 2). To fix this introduce temporary variables for each iteration. Fixes: dabfdd89eaa9 ("drm/msm/disp/dpu1: add inline rotation support for sc7280") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/681921/ Link: https://lore.kernel.org/r/20251017-b4-dpu-fixes-v1-4-40ce5993eeb6@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm/dpu: Disable scaling for unsupported scaler typesVladimir Lypak
Scaling is not implemented for some type of scalers (QSEED2 and RGB) but it was unintentionally re-enabled with change below. The remaining condition in dpu_plane_atomic_check_pipe is not enough because it only checks for length of scaler block (which is present). This patch adds a additional check for setup_scaler operation. Fixes: 8f15005783b8 ("drm/msm/dpu: move scaling limitations out of the hw_catalog") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/681918/ Link: https://lore.kernel.org/r/20251017-b4-dpu-fixes-v1-3-40ce5993eeb6@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm/dpu: Propagate error from dpu_assign_plane_resourcesVladimir Lypak
The dpu_plane_virtual_assign_resources function might fail if there is no suitable SSPP(s) for the plane. This leaves sspp field in plane state uninitialized and later leads to NULL dereference during commit: Call trace: _dpu_crtc_blend_setup+0x194/0x620 [msm] (P) dpu_crtc_atomic_begin+0xe4/0x240 [msm] drm_atomic_helper_commit_planes+0x88/0x358 msm_atomic_commit_tail+0x1b4/0x8b8 [msm] commit_tail+0xa8/0x1b0 drm_atomic_helper_commit+0x180/0x1a0 drm_atomic_commit+0x94/0xe0 drm_mode_atomic_ioctl+0xa88/0xd60 drm_ioctl_kernel+0xc4/0x138 drm_ioctl+0x364/0x4f0 __arm64_sys_ioctl+0xac/0x108 invoke_syscall.constprop.0+0x48/0x100 el0_svc_common.constprop.0+0x40/0xe8 do_el0_svc+0x24/0x38 el0_svc+0x30/0xe0 el0t_64_sync_handler+0xa0/0xe8 el0t_64_sync+0x198/0x1a0 Fixes: 3ed12a3664b3 ("drm/msm/dpu: allow sharing SSPP between planes") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/681916/ Link: https://lore.kernel.org/r/20251017-b4-dpu-fixes-v1-2-40ce5993eeb6@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm/dpu: Fix allocation of RGB SSPPs without scalingVladimir Lypak
Due to condition in dpu_rm_reserve_sspp, RGB SSPPs are only tried when scaling is requested, which prevents those SSPPs from being reserved if we don't need scaling at all. Instead we should check if YUV support is requested, since scaling on RGB SSPPs is optional and is not implemented in driver yet. Fixes: 774bcfb73176 ("drm/msm/dpu: add support for virtual planes") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/681914/ Link: https://lore.kernel.org/r/20251017-b4-dpu-fixes-v1-1-40ce5993eeb6@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-29drm/msm: dsi: fix PLL init in bonded modeNeil Armstrong
When in bonded DSI mode, only one PLL in one DSI PHY is used for both DSI PHYs, meaning that parents of the secondary DSI PHY will use the primary DSI PHY PLL as parent. In this case the primary DSI PHY PLL will be set even if the primary DSI PHY is not yet enabled. The DSI PHY code has support for this particular use-case and will handle the fact the PLL was already set when initializing the primary DSI PHY. By introducing a protected variable pll_enable_cnt in the commit cb55f39bf7b1 ("drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared"), this variable is only initially set to 1 when the DSI PHY is initialized making it impossible to set the PLL before, breaking the bonded DSI use case by returning 0 when setting the PLL from the secondary DSI PHY driver and skipping the correct clocks initialization. But since it was already possible to set the PLL without enabling the DSI PHY, just drop the pll_enable_cnt setting from the PHY enable/disable and simply increment/decrement the pll_enable_cnt variable from the dsi_pll_enable/disable_pll_bias to make sure any PLL operation is done with the PLL BIAS enabled. Fixes: cb55f39bf7b1 ("drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared") Closes: https://lore.kernel.org/all/50a49d72-2b1e-471d-b0c4-d5a0b38b2a21@linaro.org/ Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/683688/ Link: https://lore.kernel.org/r/20251027-topic-sm8x50-fix-dsi-bonded-v1-1-a477cd3f907d@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-10-28drm/i915: Unify the logic in {skl,glk}_plane_has_*()Ville Syrjälä
Use the similar logic in skl_plane_has_planar(), glk_plane_has_planar() and skl_plane_has_rc_ccs() to avoid having to think too much when comparing the three. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-9-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Extract glk_plane_has_planar()Ville Syrjälä
Extract glk_plane_has_planar() out from skl_plane_has_planar() to make the logic a bit less convoluted. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-8-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Remove pointless crtc hw.enable checkVille Syrjälä
We don't need to check for crtc hw.enable because that would also imply that the plane is disabled and we would have bailed out already earlier. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-7-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Introduce intel_plane_min_height()Ville Syrjälä
Make the skl+ plane size checks a bit more regular by adding intel_plane_min_height() instead of using a hardcoded 1 everwhere. v2: s/1/min_height/ one more time Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-6-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Start checking plane min size for the chroma planeVille Syrjälä
Currently we check the plane min size only for the Y plane. Extend the check to the CbCr plane as well. This will also allow us to remove the planar format check from icl_plane_min_width() since the +2 on the CbCr plane is equivalent to +4 on the Y plane. I suspect this approach actually models the hardware issue more accurately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-5-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Implement .min_plane_width() for PTL+Ville Syrjälä
PTL+ spposedly still has the same plane min width limit as ADL. Check for it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-4-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Drop the min plane width w/a adl+Ville Syrjälä
ADL+ no longer need the plane min width w/a (Wa_14011264657 or Wa_14011050563). Don't apply it there. DG2 still needs it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-3-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2025-10-28drm/i915: Rewrite icl_min_plane_width()Ville Syrjälä
Replace the ginormous switch statement in icl_plane_min_width() with simple arithmetic. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251009211313.30234-2-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-01-06 00:15:36 +0000