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path: root/drivers/gpu/imx
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2019-03-28Merge tag 'v4.9.166' into 4.9-2.3.x-imxMarcel Ziswiler
This is the 4.9.166 stable release
2018-12-12Merge tag 'v4.9.144' into 4.9-2.3.x-imxMarcel Ziswiler
This is the 4.9.144 stable release
2018-10-02Merge tag 'v4.9.130' into 4.9-2.3.x-imxGary Bisson
This is the 4.9.130 stable release
2018-09-07MLK-19468: drm: imx: dcss: fix blkctl setting for B1 siliconLaurentiu Palcu
B1 silicon has a new ID and we need to handle it properly. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-19274: drm: imx: dcss: add rotation functionalityLaurentiu Palcu
This patch will allow userspace to rotate planes by setting the 'rotation' property. Generally, 0 and 180 rotations are allowed for pretty much all 8-bit xRGB and 2-plane YUV420 formats. 90/270 rotations can be performed only for non-compressed tiled GPU xRGB formats. Tiled YUV420 formats do not allow rotations at all because these formats need DTRC for de-tiling and DTRC has no rotation support. For more info, consult the DPR Features chapter in the reference manual. Test example: modetest -M imx-drm -w 27:rotation:4 -w 32:rotation:32 -w 27:alpha:30 -s 42@31:3840x2160-60@XR24 -P 32@31:3840x2160@NV21 The above will perform: * 180 degree rotation of primary plane (XR24); * vertical flip of first overlay plane; * set primary plane alpha to 30; Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-19242 gpu: imx: dpu: framegen: Increase timeout when waiting for movingLiu Ying
It takes 33 milliseconds to scanout a frame when display refresh rate is 30fps, and 42 milliseconds for 24fps. So, if we wait for framegen frame index moving, 30 milliseconds timeout value is not enough to cover all reasonable display refresh rates. 50 milliseconds should not be a bad choice. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-19158-3 gpu: imx: lcdif: fix output order for 16bpp BGR formatsFancy Fang
The 16bpp BGR order pixel formats 'DRM_FORMAT_ABGR1555' and 'DRM_FORMAT_XBGR1555' also require to be re-ordered to RGB order for display, just like the format 'DRM_FORMAT_BGR565' does. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-19158-2 drm/imx: lcdif: improve output bus format configFancy Fang
According to LCDIF specification, the input pixel data width and the output pixel data width can be different, and this conversion is done by LCDIF automatically. So config the output data width according to the requested bus format from the encoder, instead to be same with the input pixel data width. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-19152-1 gpu: imx: lcdif: realize fb horizontal crop via Pigeon ModeFancy Fang
According to the LCDIF specification, the Legacy Mode does not support cropping function in the horizontal direction, so add Pigeon Mode which can support this kind of function. And when enable this mode, the legacy horizontal timings configuration should use stride value but not the active width, and related pigeon configuration should use the active width but not the stride value. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-19114-2 gpu: imx: imx8-prefetch: Remove has_prefetech_fixup from devtypesLiu Ying
There are prefetch engine fixups embedded in the updated i.MX8QM silicons. So, prefetch engines in all i.MX8 variants should be the same. Let's remove has_prefetech_fixup from devtypes which is no more needed. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-19112 gpu: imx: lcdif: change 'rpm_suspended' to be atomic counterFancy Fang
Change the 'rpm_suspended' field to be an atomic type from boolean type to make it have the counting ability which can help to detect and avoid runtime suspend and resume calls mismatch caused problems. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-18809: drm: imx: dcss: revert the max upscale ratio to 1:8Laurentiu Palcu
The DCSS RM states that the maximum upscale ratio is 1:8. However, DCSS HW team suggested some time back that upscale ratios of 1:16 could be achieved with DCSS scaler, though these ratios were not validated. Unfortunately there are corner cases, when the upscale ratio nears 1:16, that fail. At the recommendation of DCSS designers, we revert the maximum ratio to 1:8 until further notice. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-19017-4 gpu: imx: lcdif: add rpm status check for suspend/resumeFancy Fang
Add runtime PM status check during runtime suspend and resume to avoid unnecessary jobs if it is already in that state which can avoid below kernel warnings during system suspend if it is alreay in runtime suspended state: [ 21.772969] ------------[ cut here ]------------ [ 21.772982] WARNING: CPU: 3 PID: 3328 at drivers/clk/clk.c:594 clk_core_disable+0x80/0x88 [ 21.772986] Modules linked in: [ 21.772988] [ 21.772993] CPU: 3 PID: 3328 Comm: rtcwakeup.out Not tainted 4.9.88-05410-g9fa23e9ada2a #135 [ 21.772995] Hardware name: FSL i.MX8MM EVK board (DT) [ 21.772997] task: ffff800074358c80 task.stack: ffff80007b40c000 [ 21.773000] PC is at clk_core_disable+0x80/0x88 [ 21.773003] LR is at clk_core_disable_lock+0x20/0x34 [ 21.773005] pc : [<ffff0000084e1430>] lr : [<ffff0000084e1a5c>] pstate: 800001c5 [ 21.773007] sp : ffff80007b40fa90 [ 21.773010] x29: ffff80007b40fa90 x28: 0000000000000000 [ 21.773014] x27: 0000000000000002 x26: ffff000009395000 [ 21.773017] x25: ffff00000863473c x24: ffff0000092de3d0 [ 21.773021] x23: ffff80007a53f870 x22: 0000000000000000 [ 21.773024] x21: ffff00000862877c x20: ffff80007a049400 [ 21.773027] x19: 0000000000000140 x18: 0000000000000002 [ 21.773031] x17: 0000ffff93824858 x16: ffff00000822a200 [ 21.773034] x15: 0000463fe3000000 x14: 0000000000000000 [ 21.773037] x13: 0000000000000000 x12: 0000000000000000 [ 21.773040] x11: 0000000000000000 x10: 0000000000000000 [ 21.773044] x9 : 0000000040000000 x8 : 0000000000210d00 [ 21.773047] x7 : 0000000000000000 x6 : 0010ed7f00000000 [ 21.773051] x5 : ffff80007a53f9a8 x4 : 0000000000000000 [ 21.773054] x3 : 0000000010c110c0 x2 : 0000000000000000 [ 21.773057] x1 : 0000000000000000 x0 : ffff80007a049400 [ 21.773058] [ 21.773060] ---[ end trace 4a8e187491f145ed ]--- [ 21.773062] Call trace: [ 21.773065] Exception stack(0xffff80007b40f8b0 to 0xffff80007b40f9e0) [ 21.773068] f8a0: 0000000000000140 0000ffffffffffff [ 21.773071] f8c0: ffff80007b40fa90 ffff0000084e1430 00000000800001c5 000000000000003d [ 21.773074] f8e0: ffff80007b475c00 ffff80007b40c000 ffff80007b40c000 000000018020001e [ 21.773077] f900: ffff000008c53cec ffff80007b40c000 ffff80007b40f950 ffff0000085d3b9c [ 21.773081] f920: ffff80007b40f9b0 ffff0000085f3728 ffff80007b475c00 ffff80007b475c00 [ 21.773084] f940: ffff80007b40f990 ffff0000085f2430 ffff80007b475c00 ffff80007abf8800 [ 21.773087] f960: ffff80007a049400 0000000000000000 0000000000000000 0000000010c110c0 [ 21.773090] f980: 0000000000000000 ffff80007a53f9a8 0010ed7f00000000 0000000000000000 [ 21.773092] f9a0: 0000000000210d00 0000000040000000 0000000000000000 0000000000000000 [ 21.773095] f9c0: 0000000000000000 0000000000000000 0000000000000000 0000463fe3000000 [ 21.773098] [<ffff0000084e1430>] clk_core_disable+0x80/0x88 [ 21.773101] [<ffff0000084e1a5c>] clk_core_disable_lock+0x20/0x34 [ 21.773104] [<ffff0000084e1a8c>] clk_disable+0x1c/0x24 [ 21.773110] [<ffff0000085c73a0>] lcdif_disable_clocks+0x1c/0x60 [ 21.773113] [<ffff0000085c7718>] imx_lcdif_suspend+0x10/0x24 [ 21.773118] [<ffff0000086287a0>] platform_pm_suspend+0x24/0x50 [ 21.773123] [<ffff000008633b58>] dpm_run_callback.isra.12+0x30/0x8c [ 21.773126] [<ffff0000086345d4>] __device_suspend+0x110/0x278 [ 21.773129] [<ffff000008635800>] dpm_suspend+0x114/0x240 [ 21.773132] [<ffff000008635bfc>] dpm_suspend_start+0x6c/0x78 [ 21.773137] [<ffff000008104e28>] suspend_devices_and_enter+0xbc/0x534 [ 21.773139] [<ffff0000081054f8>] pm_suspend+0x258/0x2f4 [ 21.773142] [<ffff000008104030>] state_store+0x80/0xf4 [ 21.773147] [<ffff0000083e7ce8>] kobj_attr_store+0x14/0x24 [ 21.773153] [<ffff00000825d974>] sysfs_kf_write+0x40/0x48 [ 21.773156] [<ffff00000825cd48>] kernfs_fop_write+0xb8/0x1cc [ 21.773160] [<ffff0000081e2d00>] __vfs_write+0x28/0x110 [ 21.773163] [<ffff0000081e3ae4>] vfs_write+0xa8/0x1a8 [ 21.773166] [<ffff0000081e4ea0>] SyS_write+0x44/0xa0 [ 21.773170] [<ffff0000080838d8>] __sys_trace_return+0x0/0x4 [ 21.773184] ------------[ cut here ]------------ [ 21.773188] WARNING: CPU: 3 PID: 3328 at drivers/clk/clk.c:476 clk_core_unprepare+0x88/0x98 [ 21.773190] Modules linked in: [ 21.773192] [ 21.773195] CPU: 3 PID: 3328 Comm: rtcwakeup.out Tainted: G W 4.9.88-05410-g9fa23e9ada2a #135 [ 21.773196] Hardware name: FSL i.MX8MM EVK board (DT) [ 21.773198] task: ffff800074358c80 task.stack: ffff80007b40c000 [ 21.773201] PC is at clk_core_unprepare+0x88/0x98 [ 21.773204] LR is at clk_unprepare+0x28/0x34 [ 21.773206] pc : [<ffff0000084e1320>] lr : [<ffff0000084e3130>] pstate: 60000145 [ 21.773208] sp : ffff80007b40faa0 [ 21.773211] x29: ffff80007b40faa0 x28: 0000000000000000 [ 21.773215] x27: 0000000000000002 x26: ffff000009395000 [ 21.773218] x25: ffff00000863473c x24: ffff0000092de3d0 [ 21.773221] x23: ffff80007a53f870 x22: 0000000000000000 [ 21.773225] x21: ffff00000862877c x20: ffff80007aafbf80 [ 21.773228] x19: ffff80007aafb298 x18: 0000000000000002 [ 21.773232] x17: 0000ffff93824858 x16: ffff00000822a200 [ 21.773235] x15: 0000463fe3000000 x14: 0000000000000000 [ 21.773238] x13: 0000000000000000 x12: 0000000000000000 [ 21.773241] x11: 0000000000000000 x10: 0000000000000000 [ 21.773245] x9 : 0000000040000000 x8 : 0000000000210d00 [ 21.773248] x7 : 0000000000000000 x6 : 0010ed7f00000000 [ 21.773251] x5 : ffff80007a53f9a8 x4 : ffff00000944b000 [ 21.773255] x3 : 0000000000000000 x2 : ffff800074358c80 [ 21.773258] x1 : 0000000000000000 x0 : ffff80007a049400 [ 21.773259] [ 21.773260] ---[ end trace 4a8e187491f145ee ]--- [ 21.773262] Call trace: [ 21.773264] Exception stack(0xffff80007b40f8c0 to 0xffff80007b40f9f0) [ 21.773267] f8c0: ffff80007aafb298 0000ffffffffffff ffff80007b40faa0 ffff0000084e1320 [ 21.773270] f8e0: 0000000060000145 000000000000003d ffff80007b40c000 000000018020001e [ 21.773273] f900: ffff000008c53cec ffff80007b40c000 ffff80007b40f950 ffff0000085d3b9c [ 21.773276] f920: ffff80007b40f9b0 ffff0000085f3728 ffff80007b475c00 ffff80007b475c00 [ 21.773279] f940: ffff80007b40f990 ffff0000085f2430 ffff80007b475c00 ffff80007abf8800 [ 21.773282] f960: ffff80007a049400 0000000000000000 ffff80007a049400 0000000000000000 [ 21.773285] f980: ffff800074358c80 0000000000000000 ffff00000944b000 ffff80007a53f9a8 [ 21.773288] f9a0: 0010ed7f00000000 0000000000000000 0000000000210d00 0000000040000000 [ 21.773291] f9c0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 21.773293] f9e0: 0000000000000000 0000463fe3000000 [ 21.773296] [<ffff0000084e1320>] clk_core_unprepare+0x88/0x98 [ 21.773299] [<ffff0000084e3130>] clk_unprepare+0x28/0x34 [ 21.773303] [<ffff0000085c73a8>] lcdif_disable_clocks+0x24/0x60 [ 21.773306] [<ffff0000085c7718>] imx_lcdif_suspend+0x10/0x24 [ 21.773309] [<ffff0000086287a0>] platform_pm_suspend+0x24/0x50 [ 21.773312] [<ffff000008633b58>] dpm_run_callback.isra.12+0x30/0x8c [ 21.773315] [<ffff0000086345d4>] __device_suspend+0x110/0x278 [ 21.773318] [<ffff000008635800>] dpm_suspend+0x114/0x240 [ 21.773321] [<ffff000008635bfc>] dpm_suspend_start+0x6c/0x78 [ 21.773324] [<ffff000008104e28>] suspend_devices_and_enter+0xbc/0x534 [ 21.773327] [<ffff0000081054f8>] pm_suspend+0x258/0x2f4 [ 21.773329] [<ffff000008104030>] state_store+0x80/0xf4 [ 21.773332] [<ffff0000083e7ce8>] kobj_attr_store+0x14/0x24 [ 21.773336] [<ffff00000825d974>] sysfs_kf_write+0x40/0x48 [ 21.773339] [<ffff00000825cd48>] kernfs_fop_write+0xb8/0x1cc [ 21.773342] [<ffff0000081e2d00>] __vfs_write+0x28/0x110 [ 21.773345] [<ffff0000081e3ae4>] vfs_write+0xa8/0x1a8 [ 21.773347] [<ffff0000081e4ea0>] SyS_write+0x44/0xa0 [ 21.773350] [<ffff0000080838d8>] __sys_trace_return+0x0/0x4 Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-19017-3 gpu: imx: add system pm support for LCDIFFancy Fang
Implement the suspend()/resume() callbacks to support system power management functions for LCDIF. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-19017-2 gpu: imx: add DISPMIX power domain support for LCDIFFancy Fang
After the DISPMIX power domain enabled, all the related registers will drop their values once runtime pm suspend called. So in the pm runtime resume process, the LCDIF de-reset and some init jobs need to be done, and these jobs are no longer necessary to be done during probe stage anymore. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MLK-18992-1 gpu: imx: dpu: framegen: Explicitly set pixel link MST addressLiu Ying
The framegen driver knows the encoder type, so it may set pixel link MST address according to the type. The MST address for the TMDS encoder is special, while the address is zero for other encoders. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18990 gpu: imx: dpu: framegen: Don't set clk_disp rate for TMDS encoderLiu Ying
When TMDS encoder is used, the encoder would provide framegen display clock directly via clk_bypass. So, we don't have to set clk_disp rate. This should work with or without pixel combiner(pixel combiner would combine two framegens' output to drive high pixel rate displays via TMDS encoder only currently). Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18826: drm: imx: dcss: fix hang when dumping registersLaurentiu Palcu
If DCSS is suspended, the clocks are disabled. Dumping the registers, with the following command: cat /sys/kernel/debug/imx-dcss/dump_registers will hang the system, because of DTG. This patch makes sure clocks are enabled before dumping the registers and will immediately release them afterwards. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-18873: drm: imx: dcss: request PM QoS only when VBLANK is onLaurentiu Palcu
DCSS needs PM QoS in order to keep interrupt latency low. Otherwise, page flipping will not work smooth enough because CTXLD will not be triggered in time. Currently, PM QoS is requested all the time but that does not allow the CPUs to go idle. Hence, this leads to increased power consumption. This patch will change how PM QoS is requested by doing it only when VBLANK is enabled/disabled. The VBLANK interrupt is enabled just before a commit takes place and disabled after one second after last commit. This will allow DCSS to function properly and, also, allow CPUs to go idle whenever there's no buffer submitted. Exception to this is when DTRC is used (when DCSS is passed tiled buffers). In this case, PM QoS will always be active, even if no buffer is submitted, because DTRC banks need to be switched in CTXLD ISR, so that DCSS does not underrun. DTRC does not have the REPEAT feature, as the rest of DCSS does. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-18844: drm: imx: dcss: lower mode change timeLaurentiu Palcu
Currently, there's a hardcoded wait time (500ms) after enabling DTG clocks. This is supposed to avoid VBLANK timeout warning messages. However, this time is quite big. This patch changes this by lowering this time as much as possible, with the use of completion events. After enabling CRTC we just block until the first VBLANK interrupt comes. This way, we know for sure that we'll never get a VBLANK timeout. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MGS-4061 gpu: imx: dpu-blit: fix kernel panic in pm testXianzhong
resume will increase unlock counter, max allowed value is 15. suspend need decrease unlock counter to avoid overflow panic. Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MGS-4051 gpu: imx: dpu-blit: fix suspend resume issueXianzhong
suspend & resume will destory and recreate blitter, reset dprc start flags in blitter initialization. Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MLK-18680-4: drm: imx: dcss: activate DPR completion interruptsLaurentiu Palcu
This patch activates DPR completion interrupts, just for tracing and detecting green screen issues. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-18680-3: drm: imx: dcss: activate DTRC interrupts for debuggingLaurentiu Palcu
DTRC interrupts will not be used for switching the banks, as the CTXLD will be used for that, however these are useful for tracing and debugging green screen issues when DTRC is used. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-18680-2: drm: imx: dcss: add some tracesLaurentiu Palcu
This patch will add traces for the following events: * CTXLD arm, completion and kick; * VBLANKs; * atomic flushes; * plane updates (printing the DPR buffer base address); These will allow us to measure and analyze where bottlenecks are: application or driver. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-18680-1: drm: imx: dcss: low latency tracing mechanismLaurentiu Palcu
This patch adds a DCSS tracing mechanism that introduces as low latency as possible, so that it does not affect timings. Instead of text, 64 bit tags will be logged, together with the system time in nanoseconds. Based on these, post-processing can be done on any PC to compute deltas, delays, missed buffers, etc. Example usage: echo 1 > /sys/module/imx_dcss_core/parameters/tracing gplay-1.0 movie.mpg echo 0 > /sys/module/imx_dcss_core/parameters/tracing To dump the trace: cat /sys/kernel/debug/imx-dcss/dump_trace_log > trace.txt With the help of a scripting language (awk), the trace can then be post-processed and analyzed on the PC. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MGS-3560-1 [#imx-913] Enable DRM compression for mscale boardYong Gan
Addd the API dcss_dec400d_fast_clear_config. Date: June 29, 2018 Signed-off-by: Yong Gan <yong.gan@nxp.com> (cherry picked from commit 508110b51b9d9186ebb85d2d7bcaae415e2476f6)
2018-08-24MGS-3560 [#imx-913] Enable DRM compression for mscale boardYong Gan
Refine the code for compressed format support. Date: June 29, 2018 Signed-off-by: Yong Gan <yong.gan@nxp.com> (cherry picked from commit 564b74a36e40cb340c697bce44e5523eed56c5c6)
2018-08-24MLK-17925: drm: imx: dcss: fix tearingLaurentiu Palcu
The video tearing appeared only when the application used 2 buffers. That's because, sometimes, the context loader could be armed after the DB event came in the frame trace. That made a buffer submitted in frame N end up on screen in frame N+2 because the context loader waits for the next DB event. Since vblank events are sent at the end of the frame, by the time the buffer lands on screen, the application will reuse it while it's being displayed, hence the tearing effect. This patch moves the CTXLD trigger moment all the way to the end of the frame trace, just before DB event arrives. This will leave the application plenty of time to submit new buffers. In the event that the trigger moment is missed (application submits a buffer right at the end of a frame trace), then we're not signalling the next VBLANK event to application. This way, application will know that the buffer is still needed and will not submit a new one. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-08-24MLK-18576-3 drm/imx: ldb: Add dual channel mode support for i.MX8dx/dxp/qxpLiu Ying
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support dual channel mode. This patch adds the dual channel mode support for i.MX8dx/dxp/qxp. Note that the drivers contain specific sequence needed by this mode - LDB VSYNC polarity and channel selection settings should be configured into the register a bit earlier in ->atomic_mode_set instead of in ->enable, and DC subsystem pixel link enablement is moved from the DPU driver to the LDB driver to make sure it happens later than LDB clocks enablement in ->enable. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18560 drm/imx: lcdif: refine bus format sanity check for planeFancy Fang
Add an function to get the LCDIF controller supported bus formats according to the pixel format bpp. And change the bus format sanity check in the plane's atomic check to see if the bus format required by the peripheral attached to LCDIF can be supported by LCDIF. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MGS-3940-3 gpu: imx: dpu-blit: fix the confusable logicXianzhong
Simplify the code to sync command sequncer in conditions: 1. tile work with dprc/prg (baddr) 2. switch tile to linear (!start) revert 686c717fefdfc118f09085272af03358520acc7c MLK-18398 gpu: imx: imx8_dprc: dpu-blit: Wait the dprc idle before disable it Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MGS-3940-2 gpu: imx: dpu-blit: fix event triggerXianzhong
the previous programming does not flush command sequence, that cause the obvious flicker when run glmark2 in full-screen, also the wrong logic cause wayland hang in strict conditions. need program event trigger to sync command sequencer properly. also revert workaround: 4767f9aaad6d8167c21b329ace00afd3a01cd336 MLK-18283-3 gpu: imx: dpu-blit: sync for cmd sequence finished Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MGS-3940-1 gpu: imx: dpu-blit: fix first frame handlerXianzhong
chrome browser hang is reproduced with mouse connected, the first frame handler trigger the problem in below scenario: tile (dprc-enable) --> linear (dprc->disable) --> tile (handle first frame wrongly). need_handle_start is set following dprc_enable, need reset it with dprc_disable. Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MLK-18535-3 gpu: imx: add LCDIF core driverFancy Fang
The LCDIF core driver is responsible to provide controller registers configuration and create the platform devices for the child port nodes. And the platform devices later will attach to the corresponding DRM/KMS drivers via name match. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2018-08-24MGS-3947 gpu: imx: dpu-blit: fix wayland vg3d stuck on 8qxpXianzhong
gpu tiling is not enabled in vg3d, need bypass dprc/prg process, dprc stuck since no pipeline sync when switch linear to tile. add force sync for command sequence pipeline when switch to tile, remove the frequent dprc config for the contigous linear blit. Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MLK-18477-2 gpu: imx: dpu: framegen: Explicitly use bypass clk for TMDS encoderLiu Ying
The framegen driver should get PLL clock, bypass clock and display selection/mux clock via device tree if available. It may use bypass clock when a TMDS encoder is connected with the framegen, otherwise, PLL clock is used. This way, the assigned-clocks and assigned-clock-parents device tree properties can be removed from the dpu device tree node. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18398 gpu: imx: imx8_dprc: dpu-blit: Wait the dprc idle before disable itYuchou Gan
For linear and tiled mixed blit, wait the dprc idle before disable it in linear blit. Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
2018-08-24MLK-18347 gpu: imx: dpu: Correct baddr and stride for PRG x/y offsetLiu Ying
We use PRG x/y offset to do in-micro-tile cropping for new DPR/PRG IPs. When tile resolving is enabled by using the new IPs, the design team indicates that DPU fetch unit base address and DPU/PRG stride need to be calculated in the below steps: 1) prg_Baddr = dpr_Baddr 2) tmp_dpu_Baddr = prg_Baddr + prg_x_offset * bytes_per_pixel 3) tmp_burst_size = 1 << (ffs(tmp_dpu_Baddr) - 1) tmp_burst_size = round_up(tmp_burst_size, 8) burst_size = min(tmp_burst_size, 128) 4) tmp_dpu_stride = dpu_width * bytes_per_pixel 5) dpu_stride = round_up(tmp_dpu_stride + round_up(tmp_dpu_Baddr % 8, 8), burst_size) 6) dpu_Baddr = tmp_dpu_Baddr + prg_y_offset * dpu_stride 7) prg_stride = dpu_stride The legacy DPR/PRG IPs and linear formats driver logic should not be essentially touched. This patch implements the above calculation method in the drivers so that all valid in-micro-tile x/y cropping arguments can be supported. Without this, at least, some cropping cases with odd x value would fail. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18283-3 gpu: imx: dpu-blit: sync for cmd sequence finishedYuchou Gan
As blit engine use cmd sequence and disabled hardware interrupt, sync to wait the cmd sequence idle before execute new cmd sequence Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
2018-08-24MLK-18283-2 gpu: imx: imx8_dprc: Align the dprc width to smaller sizeYuchou Gan
As to super-tiled format for blit engine, the dprc width should aligned to smaller size instead of 64. Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
2018-08-24MLK-18283-1 gpu: imx: imx8_dprc: Set prg stride bigger for blit engineYuchou Gan
Blit engine need arbitrary crop, but ULC can only lie on block boundary, prg stride should be bigger than (width + align_margin) * bpp / 8 Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
2018-08-24MLK-18229-4 gpu: imx: dpu: fetchwarp: Cosmetic changes on fw_ops entriesLiu Ying
This patch contains cosmetic changes on fw_ops entries to make the entries be more readable. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18229-3 gpu: imx: dpu: fetchdlayer: Cosmetic changes on fl_ops entriesLiu Ying
This patch contains cosmetic changes on fl_ops entries to make the entries be more readable. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18229-2 gpu: imx: dpu: fetcheco: Cosmetic changes on fe_ops entriesLiu Ying
This patch contains cosmetic changes on fe_ops entries to make the entries be more readable. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18229-1 gpu: imx: dpu: fetchdecode: Cosmetic changes on fd_ops entriesLiu Ying
This patch contains cosmetic changes on fd_ops entries to make the entries be more readable. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18207 gpu: imx: framegen: Remove redundant pll and display clk rate getLiu Ying
We get pll and display clock rates twice in framegen_cfg_videomode(). This patch removes the redundant code so that the rates are got once. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18211 gpu: imx: layerblend: Zero sec alpha when sec input is from scalerLiu Ying
It turns out that local alpha value of the secondary input is set to 0xFF by the hardware if the secondary input is from scaler(hscaler or vscaler). This makes the layer on this secondary input accidentally cover the layer with higher z-order(if it exists), even though the layer with lower z-order doesn't supply local alpha. This patch zeros the secondary local alpha value to prevent the issue from happening. Users are unlikely to expect local alpha to be correctly scaled, so it looks fine to simply zero the alpha. If we find the unlikely case, the KMS driver may later explicitly do atomic check to invalidate the case. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18195 gpu: imx: dpu: framegen: Correct PLL rate to get proper pclk rateOliver Brown
This patch corrects pixel clock PLL rate calculation. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-08-24MLK-18164: drm: imx: dcss: fix max upscale ratioLaurentiu Palcu
Currently, the maximum upscale ratio is 1:7. However, DCSS can support upscale ratios up to 1:16, even though the RM states the maximum upscale ratio is 1:8. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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