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2026-10-07drm/amd/display: copy function name into dcn_optc_lock_unlock_state trace eventMelissa Wen
Userspace trace tools that use libtraceevent to read binary buffer only see a kernel address when printing const char *. Use string macros in dcn_optc_lock_unlock_state to copy the function name into the trace event. Fixes: f1943a51f0f9 ("drm/amd/display: Add events log to trace OPTC lock and unlock") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Melissa Wen <mwen@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: copy function name into dcn_fpu trace eventMelissa Wen
Userspace trace tools that use libtraceevent to read binary buffer only see a kernel address when printing const char *. Use string macros in dcn_fpu to copy the function name into the trace event. Fixes: 96ee63730fa3 ("drm/amd/display: Add control mechanism for FPU") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: remove redundant cast on amdgpu_dc_reg_template printkMelissa Wen
Commit 0cf5eb76e2b4 ("drm/amd/display: Add tracing to dc") prints and casts uint32_t fields in amdgpu_dc_reg_template to unsigned long unnecessarily. Just print those fields with %08x and remove the redundant cast. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: use right type for amdgpu_dc_performance event entriesMelissa Wen
Some amdgpu_dc_performance trace event params are passed as unsigned long but stored as uint32_t, cutting them off on 64-bit. Use the right type on entry fields and on printk use unsigned format accordingly. Fixes: 0cf5eb76e2b4 ("drm/amd/display: Add tracing to dc") Signed-off-by: Melissa Wen <mwen@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: declare amdgpu_dm_atomic_state_template as an event classMelissa Wen
Don't create an amdgpu_dm_atomic_state_template event since this is just a template. Declare the template as an event class that will be used by actual event tracers. Fixes: e8a982355f96 ("drm/amd/display: Add tracepoint for amdgpu_dm") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: fix vready offset assignment in dcn_optc_lock_unlock_stateMelissa Wen
vready_offset is captured by optc_state, but the trace point entry is wrongly assigned to vupdate_offset. Fix vready_offset tracepoint field in dcn_optc_lock_unloack_state to record optc_state->vready_offset. Fixes: f1943a51f0f9 ("drm/amd/display: Add events log to trace OPTC lock and unlock") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: remove duplicated prev_p_state_change_support assignmentMelissa Wen
The prev_p_state_change_support trace entry is assigned and printed twice, remove the unnecessary duplicates. Fixes: 13b5ca42ca9c ("drm/amd/display: Add tracepoint for capturing clocks state") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: assign missing trace entry in amdgpu_dm_dc_clocks_stateMelissa Wen
disp_dpp_voltage_level_khz is declared and printed, but never assigned. So when using clock tracepoint the value of this clock is just garbage. Assign clk->disp_dpp_voltage_level_khz since this is stored in dc_clocks as other entries. Fixes: 13b5ca42ca9c ("drm/amd/display: Add tracepoint for capturing clocks state") Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Promote DC to 3.2.401Ashwin Santhosh
This version brings along the following updates: - Add HDMI RR and SCDC skips. - Add debug option to override low power SR latencies. - Allow skipping link bandwidth clear. - Handle virtual link encoder. - Improve MCM shaper/3DLUT programming and DTN logging. - Only reprogram DRR when v_total values change. - Refactor DMUB fast lock sequencing. - Send HDMI VRR metadata in VTEM info packet slot. - Set cursor_offload for all pipes for a given stream. - Skip link off frame count for general UI. - Update link training no timeout behaviour on HDMI. Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Send HDMI VRR metadata in VTEM info packet slotIvan Lipski
[Why] Brief blank on HDMI each time VRR engaged and disengaged, with no modeset at either transition. amdgpu_dm_update_freesync_state_on_stream() built the VTEM on top of the buffer holding the AMD FreeSync SPD payload, which becomes stream->vrr_infopacket. DC routes that to HDMI generic slot 3 (SPD) and vtem_infopacket to slot 6 (VTEM), and vtem_infopacket was never populated. So slot 3 carried a VTEM payload the sink parsed as an SPD InfoFrame, no VTEM was sent, and v_total varied with no valid metadata describing it. DP uses the VSC/AS-SDP path and is unaffected. [How] Build the VTEM into a separate vtem_infopacket, gated on the sink not advertising AMD FreeSync. Track it in dm_crtc_state, include it in the freesync_vrr_info_changed comparison and the reset path, and pass it through bundle->stream_update.vtem_infopacket. Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Add debug option to override low power SR latenciesAlvin Lee
[Description] - Add debug options to override low power SR latencies - Match regular SR latency debug override Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Add dcn42b project idDillon Varone
[WHY&HOW] Add project ID to distinguish dcn42b from dcn42. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Handle virtual link encoderSridevi Arvindekar
[Why/How] Fix check for virtual link encoder Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Revert "avoid to write signal specific for tmds"Joshua Aberback
This reverts commit 93179870ae52d1663080655fb8f0170a82cf9951. The change regressed HDMI output on the TMDS-to-FRL switch. Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Update link training no timeout behaviour on HDMIRelja Vojvodic
[Why & How] - HMDI link training compliance testing fails when no timeout bit is set - Update condition to skip some link training logic when no timeout is set Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Assign alt wa bit in fams2 cmdAlvin Lee
[Description] Assign the workaround bit to ensure it propagates to FW Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Prepare DSC configuration before BLS executionRafal Ostrowski
[Why] DSC sequence operations calculated configuration during execution and passed OPTC outputs through pointers into other sequence steps. This coupled consumers to step storage and mixed calculation with programming. [How] Merge the DSC configuration operations into DSC_SET_CONFIG. Prepare register values in each DSC instance during build and pass OPTC values by value to timing-generator and stream-encoder operations. Share stream composition while preserving link-update and ODM padding. Use the correct DCN401 preparation callback and remove the legacy ops. Validate local composition inputs and capacity, stop immediate programming on preparation failure, and publish prepared caches only on success. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: allow skipping link bandwidth clearMartin Tsai
[why] To set link bandwidth with zero could hit error protection from Sink panel to fail link training and cause screen corruption. [how] To skip link bw cleaning in two conditions: 1. eDP v1.5 or latter, because the last write will take effect. 2. Sink requires not to clear it. Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Martin Tsai <Martin.Tsai@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Skip link off frame count for general UIAllen Li
[Why&How] To improve power saving of Replay, skip the link off frame count check for general UI in DC mode. Also disable timing sync in the same condition. Reviewed-by: ChunTao (Chun-Tao) Tso <chuntao.tso@amd.com> Signed-off-by: Allen Li <Allen.Li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Refactor DMUB fast lock sequencingRafal Ostrowski
[WHY] Resolve fast-lock policy before execution and avoid queuing no-op steps. Remove duplicated per-ASIC command construction. [HOW] Use one fast-lock opcode, parameter structure and executor. Capture the service handle and precomputed Inbox0 command. Keep separate SubVP and generic capability hooks and preserve the lock manager's original support and split feature gates. Retain the unused SubVP enumerator and existing opcode values. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Set cursor_offload for all pipes for a given streamAlvin Lee
[Description] - When using the cursor offload path, the cursor_offload flag must be set for each DPP and HUBP driving the stream - Previous implementation only sets the flag in the DPP and HUBP for the OTG master pipe - Add helper function to populate an array of DPP's and HUBP's that need to have the cursor_offload flag set - This is to avoid passing in pipe_ctx to hwss execution params Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Add HDMI RR and SCDC skipsIlya Bakoulin
[Why/How] - Add debug key to avoid enabling RR by default. - Skip SCDC access if sink or SCDC cap not present Reviewed-by: Relja (Reggie) Vojvodic <relja.vojvodic@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: only reprogram DRR when v_total values changeAric Cyr
[Why] dc_stream_adjust_vmin_vmax() programmed the OTG on every call. FreeSync BTR calls it once per vblank, so identical v_total values were rewritten every frame, each one paying dc_exit_ips_for_hw_access() and, when FAMS is enabled, a blocking DMUB round trip from setup_manual_trigger(). [How] Return early when timing_adjust_pending is clear and every v_total field already matches the request, so hardware is only touched when the values change. stream->adjust is still updated on every path that continues, so a later commit programs the requested values. timing_adjust_pending is the existing "stream->adjust has not reached hardware" marker, so keep it accurate wherever hardware is left untouched: set_drr_and_clear_adjust_pending() now sets it when called with null params, which resets DRR in the OTG during pipe back-end teardown, and the max_v_total overflow path only clears it when set_long_vtotal() runs. Reviewed-by: Josip Pavic <josip.pavic@amd.com> Signed-off-by: Aric Cyr <Aric.Cyr@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: log MCM shaper and 3D LUT mode in the DTN logHarry Wentland
On DCN4 the per-plane MCM shaper and 3D LUT state wasn't visible in the DTN log: dcn401 wired read_mpcc_state to mpc1_read_mpcc_state, which only reads the base MPCC blend registers, and the MPCC section didn't print the LUT fields even where they were populated. Add mpc401_read_mpcc_state to also read MPCC_MCM_3DLUT_MODE (mode current and size) and MPCC_MCM_SHAPER_CONTROL (mode current), and print SHAPER, 3DLUT and 3DLUT_SIZE columns in the MPCC section. Mode is 0 bypass, 1 RAM_A, 2 RAM_B; 3DLUT_SIZE is 0 for 17x17x17 and 1 for 9x9x9. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: enable shaper when programming 3DLUTHarry Wentland
The plane-XR30-XR30-3dlut_17_12_rgb kms_colorop test fails on DCN 4.x. We need to make sure we set shaper_enable to enable the shaper block, otherwise the 3DLUT block will stay inactive. Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdkfd: align SDMA doorbell base for shader doorbell writesSaleel Kudchadker
On GC 9.4.3, 9.4.4 and 9.5.0, doorbell writes issued from shaders are routed to an SDMA engine at 32-byte (4 doorbell index) granularity. SDMA engine doorbell ranges are 10 indices apart, so the range of every odd engine starts 2 indices into a 4-index block that begins in the previous engine's range. A shader ringing the doorbell of a queue on an odd engine therefore rings the previous engine instead. The intended queue never sees the doorbell, so its work stalls and the application hangs. Align the per-engine doorbell base up to a 4-index boundary on these ASICs. Each engine only uses 4 of its 10 indices, so the aligned base plus the queue offset stays within the engine's range. Even engines are already aligned, so only the doorbell IDs of odd-engine queues change. Only doorbells rung by the device itself are routed this way. Doorbell writes from the host, including the kernel's own SDMA rings, are not affected. The doorbell ID of an SDMA queue is saved in CRIU checkpoints and checked again on restore. A checkpoint taken before this change that contains an SDMA queue on an odd engine will fail to restore with -EINVAL. This is intentional: the restored process still holds the old doorbell address, so accepting the stale ID would bring back the same stall. Tested on MI300X with a shader-rung SDMA doorbell test: queues on odd engines hung before this change and complete with it. v2: use u32 instead of uint32_t for the new locals (checkpatch) v3: name the routing granularity, use dev->node_id, document the layout invariants, describe impact v4: express the granularity in doorbell indices, drop unrelated cleanups, explain the CRIU restore behavior, add test note Fixes: 6df442a03d1a ("drm/amdgpu: add new doorbell assignment table for aqua_vanjaram") Signed-off-by: Saleel Kudchadker <Saleel.Kudchadker@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdkfd: mark A+A VF VRAM PTEs as system memoryZhigang Luo
On the A+A VF, VRAM is accessed through the system memory path, so SVM range PTEs that point at VRAM need AMDGPU_PTE_SYSTEM set, matching what the graphics paths already do. v2: - Use (sriov_vf || passthrough) and amdgpu_virt_vram_is_spm() for SVM VRAM PTE_SYSTEM. v3: - Rely on amdgpu_virt_vram_is_spm() without redundant VF/passthrough checks. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: get rid of amdgpu_drm_ioctlPierre-Eric Pelloux-Prayer
Remove the entire amdgpu_drm_ioctl handler system in favor of drm_ioctl, as amdgpu_drm_ioctl held a runtime_pm reference for every ioctl that passed through it, even if hardware access was not required. The runtime_pm references should now be handled by each individual IOCTL that requires the GPU to be awake. Hopefully all the IOCTLs that require hardware access were covered. v2 (Shahyan): Added commit description Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu/gfx12: read xccs-per-xcp from RLC_IMU_AID_CONFIG for VFIYuBiao Wang
gfx_v12_1_get_xccs_per_xcp() supplies the compute partition layout that gfx_v12_1_cp_resume() needs on a VF. Once VFI is enabled the VF reaches registers through RLCG, which cannot access the GFX_IMU registers, so the GFX_IMU_PARTITION_SWITCH read stops working. Take the same field from RLC_IMU_AID_CONFIG instead, and read it with a direct MMIO access rather than RREG32_SOC15, which would route back into the RLCG path. Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: copy debugfs register data outside the GRBM/SRBM locksMikhail Gavrilov
Reading or writing a register through the amdgpu_regs2 debugfs file with GRBM bank selection, which umr does for every banked access (a single "umr -b x x x -r <reg>" is enough, as is the wave dump with "-O halt_waves"), makes lockdep report a circular locking dependency, after which lockdep stays off until reboot: WARNING: possible circular locking dependency detected umr/63306 is trying to acquire lock: ffff8882cf4b8350 (&mm->mmap_lock){++++}-{4:4}, at: __might_fault+0x9b/0x140 but task is already holding lock: ffff8881aec010d0 (&amdgpu_grbm_lock_key){+.+.}-{4:4}, at: amdgpu_debugfs_regs2_op.isra.0+0x20d/0xd00 [amdgpu] ... Chain exists of: &mm->mmap_lock --> &amdgpu_srbm_lock_key --> &amdgpu_grbm_lock_key ... __might_fault+0xc5/0x140 amdgpu_debugfs_regs2_op.isra.0+0x441/0xd00 [amdgpu] full_proxy_write+0x10e/0x1d0 vfs_write+0x1d0/0xf50 ksys_write+0x116/0x250 amdgpu_debugfs_regs2_op() and amdgpu_debugfs_process_reg_op() call get_user()/put_user() for every dword while holding grbm_idx_mutex or srbm_mutex, and pm.mutex if requested, so a fault there takes mmap_lock inside those locks. The lock hierarchy in amdgpu_lockdep.c puts srbm_mutex and grbm_idx_mutex below notifier_lock, which amdgpu_cs_submit() takes with the BO reservations held, and dma_resv_lockdep() orders the reservations inside mmap_lock. So mmap_lock is outside grbm_idx_mutex and srbm_mutex, and these two debugfs paths nest it the other way round. The copies under the locks are as old as the bank selection in both files; commit 1d0f5838b126 ("drm/amdgpu: Add lockdep annotations for lock ordering validation") only made them visible to lockdep. Copy the user buffer in before any of the locks is taken and the result out after all of them are dropped, as amdgpu_debugfs_wave_read(), amdgpu_debugfs_gpr_read() and amdgpu_debugfs_gprwave_read() already do. The buffer is sized by the count passed to read() or write(), so an access larger than PAGE_SIZE is now rejected with -EINVAL; umr reads and writes one register at a time. A fault on the user buffer of a write now fails with -EFAULT before any register is written, instead of after a partial write. Fixes: 566281595037 ("drm/amd/amdgpu: Add bank selection for MMIO debugfs (v3)") Fixes: 37df9560cd3e ("drm/amd/amdgpu: New debugfs interface for MMIO registers (v5)") Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: serialize vblank counter reads against GPU resetVitaly Prosyak
The vblank counter callback reads display registers and scanout position without holding reset_domain->sem. During GPU recovery, display commit work can call the callback while reset owns the semaphore for writing. The hardware access then triggers the lockdep_assert_held() in amdgpu_device_skip_hw_access() and sets TAINT_WARN when lockdep is enabled. Try to acquire the reset semaphore for reading before accessing the hardware, and hold it across the counter and scanout-position reads. If reset is already in progress, return DRM's cached software vblank count instead. This avoids blocking behind reset and avoids accessing display hardware while it is being reset. The cached count is less accurate than the hardware count, but is used only when reset prevents a safe hardware read. This addresses the reset-time warning from this vblank path; it does not suppress or fix unrelated lockdep warnings. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: mark A+A VF VRAM mappings as system memoryZhigang Luo
On the A+A VF the GPU reaches its HBM over the system memory path at a system physical address, so page table entries covering VRAM have to carry AMDGPU_PTE_SYSTEM and the addresses they hold have to be physical rather than MC addresses. Set the SYSTEM bit in the PDB0 entries and in amdgpu_ttm_tt_pde_flags(), and convert the VRAM address in amdgpu_gmc_get_pde_for_bo() with amdgpu_gmc_vram_mc2pa(). NPA mappings still require VSCT=0011 (PTE.S=0). Clear SYSTEM in gmc_v12_1_get_npa_flags() and amdgpu_ualink_peer_remote_init() so NPA PTEs do not inherit the VRAM SYSTEM bit. v2: - Use (sriov_vf || passthrough) and amdgpu_virt_vram_is_spm() for PDB0/TTM SYSTEM bits and mc2pa. v3: - Rely on amdgpu_virt_vram_is_spm() without redundant VF/passthrough checks. v4: - Explicitly clear AMDGPU_PTE_SYSTEM for NPA (VSCT=0011). Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: take the A+A VF GMC aperture from SRATZhigang Luo
The A+A VF FB BAR is not usable, so resolve its aperture from SRAT in GMC early_init. Skip later aperture assignment for SPM-backed devices, and restrict the existing mmhub-based override to native A+A and APU. The GPU reaches its HBM at a system physical address, so vram_base_offset becomes aper_base as well, which makes PDB0 map GPU address 0 onto that address. The XGMI node segment size comes from the same place: once early_init has resolved the aperture, use its size rather than the value derived from the register, which does not describe the VF partition. v2: - Use (sriov_vf || passthrough) and amdgpu_virt_vram_is_spm() instead of connected_to_cpu for the SRAT aperture and node segment size. v3: - Resolve the SRAT aperture in GMC early_init and skip later aperture assignment in mc_init for SPM-backed devices. - Rely on amdgpu_virt_vram_is_spm() without redundant VF/passthrough checks. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: fetch the A+A VF VBIOS from the SRAT HBM rangeZhigang Luo
On A+A the VF has no usable FB BAR, so the VBIOS copy cannot be read through BAR 0. It lives in HBM, which the SRAT describes as specific-purpose memory reachable at a system physical address. Add a dedicated amdgpu_read_bios_from_spm() path that resolves the HBM range from SRAT and maps it as write-back system memory. Keep the existing SR-IOV dynamic critical region path when it is enabled, matching the VRAM reader. v2: - Use a separate amdgpu_read_bios_from_spm() helper and leave amdgpu_read_bios_from_vram() unchanged. - Keep the SR-IOV dynamic critical region path for SPM-backed VBIOS. - Fetch VBIOS after the COMMON block and make it optional for SPM-backed SR-IOV VF and passthrough configurations. v3: - Keep the SRAT range local to the VBIOS path; GMC owns aper_base and aper_size. - Map SPM with memremap(), memcpy(), and memunmap(). - Rely on amdgpu_virt_vram_is_spm() without redundant VF/passthrough checks. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: add helper for VRAM in system physical memoryZhigang Luo
On A+A, HBM is reached at a host physical address, so VRAM mappings need the system-memory path. That is true for both an SR-IOV VF and a passthrough VM; native PF A+A keeps the mmhub/sysvm path. Add AMDGPU_VIRT_VRAM_IS_SPM and amdgpu_virt_vram_is_spm() so later patches can identify SPM-backed VRAM without repeating the cap test. v2: - Rename the helper to amdgpu_virt_vram_is_spm(); it only tests AMDGPU_VIRT_VRAM_IS_SPM. - Set the cap in ip_early_init when an SR-IOV VF or passthrough dGPU has no FB BAR0, after AMD_IS_APU is known. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: fix the unit of the SR-IOV IP discovery size checkYuBiao Wang
ip_discovery_size_in_kb is in KB but was compared against DISCOVERY_TMR_SIZE, a byte count, so the check never fired. Compare both sides in KB against a new 16KB SR-IOV bound, since 10KB does not cover new ASICs which need 0x2840, and drop the duplicate check below. Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: disable self-refresh on tearing flipsLeo Li
[Why & How] Immediate (tearing) flips breaks self refresh state machine assumptions, so disable PSR/Replay for them. Tested-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: add SRAT lookup for GPU-local memoryZhigang Luo
On A+A the GPU HBM is exposed as specific-purpose memory described by SRAT, and the GPU reaches it at a system physical address over the internal link, so the driver needs a way to discover that range. Add amdgpu_acpi_find_gpu_memory_in_srat(), which resolves the GPU proximity domain from the SRAT GENERIC_AFFINITY entry matching the PCI device handle, then returns the enabled, non-hotpluggable memory range of that domain. No caller yet, the users follow. v2: - A+A VF/passthrough is identified later by missing FB BAR0 (AMDGPU_VIRT_VRAM_IS_SPM), not by xgmi.connected_to_cpu. v3: - Rename best_base/best_len to mem_base/mem_len; first match, not a comparison. - Drop the unused legacy packed-BDF PCI handle format. - Log "no acpi generic initiator found" without extra PCI BDF. - Use dev_err for error-return logs. v4: - Reverse Christmas-tree local declarations, one per line. - Reject NULL base_addr/length with -EINVAL. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu/userq: return the memdup_user() error for the user MQDJesse Zhang
mes_userq_mqd_create() returns -ENOMEM when copying the user MQD fails, even though memdup_user() returns -EFAULT for a bad pointer or -EINTR when interrupted by a signal. Return PTR_ERR() instead. While at it drop the error messages. Neither case is a driver error and userspace shouldn't be able to spam the log with invalid IOCTL parameters. v2: drop the error messages (Christian) Fixes: 2c695d7c0720 ("drm/amdgpu: enable compute/gfx usermode queue") Fixes: 543b61453774 ("drm/amdgpu: enable SDMA usermode queues") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu/userq: only accept doorbell BOs as queue doorbellJesse Zhang
amdgpu_userq_get_doorbell_index() pins any BO passed as doorbell_handle into the doorbell domain. For a regular BO, TTM moves it with ttm_bo_move_null() and its contents are lost. Since an importer on the same device gets the exporter's GEM object, a client can do this to a buffer another client shared with it. Reject BOs that were not created in the doorbell domain. v2: drop the error message, use a local abo variable (Christian) Fixes: f09c1e6077ab ("drm/amdgpu: generate doorbell index for userqueue") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: prevent suspend in fault handlerPierre-Eric Pelloux-Prayer
Temporarily increment the PM reference count during page handling to ensure the GPU does not enter a sleep state. v2 (Shahyan): Added commit description Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: handle runtime pm in amdgpu_gem_userptr_ioctlPierre-Eric Pelloux-Prayer
Wake up the GPU while setting up user pages and validating the buffer. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Co-developed-by: Shahyan Soltani <shahyan.soltani@amd.com> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: push down runtime pm handling in amdgpu_gem_create_ioctlPierre-Eric Pelloux-Prayer
For now use the same logic as the existing one, but it's not 100% correct since: 1) most operations don't need the GPUs 2) some operations that need it are actually deferred Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Co-developed-by: Shahyan Soltani <shahyan.soltani@amd.com> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: add amdgpu_vmid_uq_mask_init() helperSunil Khatri
Move the duplicated VMID-mask-above-first_kfd_vmid computation out of amdgpu_mes.c and amdgpu_amdkfd.c into a shared helper, called once from amdgpu_vmid_mgr_init() to set vm_manager.vmid_uq_mask_gfxhub/mmhub. MES and KFD now just read those fields instead of each computing them. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: rename amdgpu_vmid_mgr to amdgpu_kq_vmid_mgrSunil Khatri
amdgpu_vmid_mgr is really the per-VMHUB structure used for VMIDs handed out to kernel queues only, not to user queues. Rename it to amdgpu_kq_vmid_mgr to make that unambiguous. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Fix direct scanout alpha on some DRM_FORMATsLeo Li
[Why] DM was declaring it's own list of has_alpha DRM formats to check against for enabling alpha blending, when the format->has_alpha already does that for us. The self-declared list missed some has_alpha formats, causing direct-scanout planes with such formats to appear opaque. [How] Drop the self-declared list, instead use the format->has_alpha field directly. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: rework runtime pm management for csPierre-Eric Pelloux-Prayer
Submitting a cs ioctl will now wake up the GPU. The guard will automatically drop the rpm ref when the cs ioctl goes out of scope. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Co-developed-by: Shahyan Soltani <shahyan.soltani@amd.com> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: fix the indentation of fault_info memberSunil Khatri
In struct amdgpu_vm_manager fix the indentation of member "fault_info". Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: move vmid_mask_gfxhub/vmid_mask_mmhub to vm_managerSunil Khatri
vmid_mask_gfxhub/vmid_mask_mmhub makes more sense logically in vm_manager than the mes ip struct. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amdgpu: Use MTYPE_UC for ext-coherent local memory on AID A0 non-SPXMukul Joshi
On GFX 12.1 AID A0, extended-scope fine-grained local HBM must be mapped MTYPE_UC when the device is in DPX, QPX or CPX compute partition mode. In SPX mode the local MTYPE (MTYPE_NC by default) is kept. Remote VRAM and system memory already use MTYPE_UC. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: David Yat Sin <david.yatsin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-10-29 21:43:52 +0000