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2025-10-31Merge tag 'amd-drm-next-6.19-2025-10-29' of ↵Simona Vetter
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-10-29: amdgpu: - VPE idle handler fix - Re-enable DM idle optimizations - DCN3.0 fix - SMU fix - Powerplay fixes for fiji/iceland - License copy-pasta fixes - HDP eDP panel fix - Vblank fix - RAS fixes - SR-IOV updates - SMU 13 VCN reset fix - DMUB fixes - DC frame limit fix - Additional DC underflow logging - DCN 3.1.5 fixes - DC Analog encoders support - Enable DC on bonaire by default - UserQ fixes - Remove redundant pm_runtime_mark_last_busy() calls amdkfd: - Process cleanup fix - Misc fixes radeon: - devm migration fixes - Remove redundant pm_runtime_mark_last_busy() calls UAPI - Add ABM KMS property Proposed kwin changes: https://invent.kde.org/plasma/kwin/-/merge_requests/6028 Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251029205713.9480-1-alexander.deucher@amd.com
2025-10-31drm/xe/pf: Allow to stop the VF using sysfsMichal Wajdeczko
It is expected that VFs activity will be monitored and in some cases admin might want to silence specific VF without killing the VM where it was attached. Add write-only attribute to stop GuC scheduling at VFs level. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── vf1/ │ └── stop [WO] bool ├── vf2/ │ └── stop [WO] bool Writing "1" or "y" (or whatever is recognized by the strtobool() function) to this file will trigger the change of the VF state to STOP (GuC will stop servicing the VF). To go back to a READY state (to allow GuC to service this VF again) the VF FLR must be triggered (which can be done by writing 1 to device/reset file). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-17-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add sysfs device symlinks to enabled VFsMichal Wajdeczko
For convenience, for every enabled VF add 'device' symlink from our SR-IOV admin VF folder to enabled sysfs PCI VF device entry. Remove all those links when disabling PCI VFs. For completeness, add static 'device' symlink for the PF itself. /sys/bus/pci/drivers/xe/BDF/sriov_admin/ ├── pf │   └── device -> ../../../BDF # PF BDF ├── vf1 │   └── device -> ../../../BDF' # VF1 BDF ├── vf2 │   └── device -> ../../../BDF" # VF2 BDF Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-16-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Promote xe_pci_sriov_get_vf_pdevMichal Wajdeczko
In the upcoming patch we would like to use this private helper during preparation of the sysfs links. Promote it. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-15-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow change PF scheduling priority using sysfsMichal Wajdeczko
We have just added bulk change of the scheduling priority for all VFs and PF, but that only allow to select LOW and NORMAL priority. Add read-write attribute under PF to allow changing its priority without impacting other VFs priority settings. For completeness also add read-only attributes under VFs, to show currently selected priority levels used by the VFs. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ │ └── profile │ └── sched_priority [RW] low, normal, high ├── vf1/ │ └── profile │ └── sched_priority [RO] low, normal Writing "high" to the PF read-write attribute will change PF priority on all tiles/GTs to HIGH (schedule function in the next time-slice after current one completes and it has work). Writing "low" or "normal" to change priority to LOW/NORMAL is supported. When read, those files will display the current and available scheduling priorities. The currently active priority level will be enclosed in square brackets, default output will be like: $ grep . -h sriov_admin/{pf,vf1,vf2}/profile/sched_priority [low] normal high [low] normal [low] normal Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-14-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow bulk change all VFs priority using sysfsMichal Wajdeczko
It is expected to be a common practice to configure the same level of scheduling priority across all VFs and PF (at least as starting point). Due to current GuC FW limitations it is also the only way to change VFs priority. Add write-only sysfs attribute that will apply required priority level to all VFs and PF at once. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── .bulk_profile │   └── sched_priority [WO] low, normal Writing "low" to this write-only attribute will change PF and VFs scheduling priority on all tiles/GTs to LOW (function will be scheduled only if it has work submitted). Similarly, writing "normal" will change functions priority to NORMAL (functions will be scheduled irrespective of whether there is a work or not). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-13-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to provision scheduling priorityMichal Wajdeczko
We already have function to configure PF (or VF) scheduling priority on a single GT, but we also need function that will cover all tiles and GTs. However, due to the current GuC FW limitation, we can't always rely on per-GT function as it actually only works for the PF case. The only way to change VFs scheduling priority is to use 'sched_if_idle' policy KLV that will change priorities for all VFs (and the PF). We will use these new functions in the upcoming patches. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-12-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow bulk change all VFs EQ/PT using sysfsMichal Wajdeczko
It is expected to be a common practice to configure the same values of execution quantum and preemption timeout parameters across all VFs. Add write-only sysfs attributes that will apply required EQ/PT values globally, without forcing admin to update PF and each VF separately. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── .bulk_profile │   ├── exec_quantum_ms [WO] unsigned integer │   └── preempt_timeout_us [WO] unsigned integer Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-11-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to bulk provision EQ/PTMichal Wajdeczko
We already have functions to configure EQ/PT for single VF across all tiles/GTs. Now add helper functions that will do that for all VFs (and the PF) at once. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-10-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to bulk configure EQ/PT on GTMichal Wajdeczko
We already have functions to bulk configure 'hard' resources like GGTT, LMEM or GuC context/doorbells IDs. Now add functions for the 'soft' scheduling parameters, as we will need them soon in the upcoming patches. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-9-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Fix signature of internal config helpersMichal Wajdeczko
Both pf_get_exec_quantum() and pf_get_preempt_timeout() should return u32 as this is a type of the underlying data. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-8-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Relax report helper to accept PF in bulk configsMichal Wajdeczko
Our current bulk configuration requests are only about VFs, but we want to add new functions that will also include PF configs. Update our bulk report helper to accept also PFID as first VFID. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-7-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow change PF and VFs EQ/PT using sysfsMichal Wajdeczko
On current platforms, in SR-IOV virtualization, the GPU is shared between VFs on the time-slice basis. The 'execution quantum' (EQ) and 'preemption timeout' (PT) are two main scheduling parameters that could be set individually per each VF. Add EQ/PT read-write attributes for the PF and all VFs. By exposing those two parameters over sysfs, the admin can change their default values (infinity) and let the GuC scheduler enforce that settings. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ │ └── profile │ ├── exec_quantum_ms [RW] unsigned integer │ └── preempt_timeout_us [RW] unsigned integer ├── vf1/ │ └── profile │ ├── exec_quantum_ms [RW] unsigned integer │ └── preempt_timeout_us [RW] unsigned integer Writing 0 to these files will set infinity EQ/PT for the VF on all tiles/GTs. This is a default value. Writing non-zero integers to these files will change EQ/PT to new value (in their respective units: msec or usec). Reading from these files will return EQ/PT as previously set on all tiles/GTs. In case of inconsistent values detected, due to errors or low-level configuration done using debugfs, -EUCLEAN error will be returned. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-6-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add _locked variants of the VF PT config functionsMichal Wajdeczko
In upcoming patches we will want to configure VF's preemption timeout (PT) on all GTs under single lock to avoid potential races due to parallel GT configuration attempts. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-5-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add _locked variants of the VF EQ config functionsMichal Wajdeczko
In upcoming patches we will want to configure VF's execution quantum (EQ) on all GTs under single lock to avoid potential races in parallel GT configuration attempts. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-4-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Take RPM during calls to SR-IOV attr.store()Michal Wajdeczko
We expect that all SR-IOV attr.store() handlers will require active runtime PM reference. To simplify implementation of those handlers, take an implicit RPM reference on their behalf. Also wait until PF completes its restart. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-3-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Prepare sysfs for SR-IOV admin attributesMichal Wajdeczko
We already have some SR-IOV specific knobs exposed as debugfs files to allow low level tuning of the SR-IOV configurations, but those files are mainly for the use by the developers and debugfs might not be available on the production builds. Start building dedicated sysfs sub-tree under xe device, where in upcoming patches we will add selected attributes that will help provision and manage PF and all VFs: /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ ├── vf1/ ├── vf2/ : └── vfN/ Add all required data types and helper macros that will be used by upcoming patches to define actual attributes. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-2-michal.wajdeczko@intel.com
2025-10-31Merge tag 'drm-xe-fixes-2025-10-30' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Driver Changes: - Fix xe_validation_guard() not guarding (Thomas Hellström) - Do not wake device during a GT reset (Matthew Brost) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/o2b3lucyitafbbcd5bewpfqnslavtnnpc6ck4qatnou2wwukix@rz6seyfw75uy
2025-10-31Merge tag 'drm-misc-fixes-2025-10-30' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Short summary of fixes pull: ast: - Preserve correct bits on register I/O dma-fence: - Use correct timeline name etnaviv: - Use correct GPU adress space for flush imx: - parallel-display: Fix bridge handling nouveau: - Fix locking in scheduler panel: - kingdisplay-kd097d04: Disable EOT packet - sitronix-st7789v: Use correct SYNC flags sched: - Fix locking to avoid race condition - Fix SIGKILL handling sysfb: - Avoid NULL-pointer access Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251030195644.GA188441@localhost.localdomain
2025-10-31Merge tag 'drm-intel-fixes-2025-10-30' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes - Fix DMC/DC6 asserts on ADL-S (Ville) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/aQNtTV75vPaDhnXh@intel.com
2025-10-31Merge tag 'drm-msm-fixes-2025-10-29' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.18-rc4 CI - Disable broken sanity job GEM - Fix vm_bind prealloc error path - Fix dma-buf import free - Fix last-fence update - Reject MAP_NULL if PRR is unsupported - Ensure vm is created in VM_BIND ioctl GPU - GMU fw parsing fix DPU: - Fixed mode_valid callback - Fixed planes on DPU 1.x devices. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV03kUm1ms7FBg0m9U4ZcyickSWbnayAWqYqs0XH4UjWf+A@mail.gmail.com
2025-10-31Merge tag 'amd-drm-fixes-6.18-2025-10-29' of ↵Simona Vetter
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.18-2025-10-29: amdgpu: - VPE idle handler fix - Re-enable DM idle optimizations - DCN3.0 fix - SMU fix - Powerplay fixes for fiji/iceland - License fixes - HDP eDP panel fix - Vblank fix radeon: - devm migration fixes Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251029201342.8813-1-alexander.deucher@amd.com
2025-10-31Merge tag 'drm-intel-gt-next-2025-10-29' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Driver Changes: Fixes/improvements/new stuff: - Set O_LARGEFILE in __create_shmem() (Taotao Chen) - Fix incorrect error handling in shmem_pwrite() (Taotao Chen) - Skip GuC communication warning on reset in progress [guc] (Zhanjun Dong) - Fix conversion between clock ticks and nanoseconds [guc] (Umesh Nerlige Ramappa) Miscellaneous: - Avoid accessing uninitialized context in emit_rpcs_query() [selftests] (Krzysztof Karas) - Fix typo in comment (I915_EXEC_NO_RELOC) [gem] (Marlon Henrique Sanches) Backmerges: - Merge drm/drm-next into drm-intel-gt-next (Joonas Lahtinen) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Tvrtko Ursulin <tursulin@igalia.com> Link: https://patch.msgid.link/aQH994lQI_iVPzTI@linux
2025-10-31Merge tag 'mediatek-drm-fixes-20251028' of ↵Simona Vetter
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes Mediatek DRM Fixes - 20251028 1. Fix device use-after-free on unbind Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patch.msgid.link/20251028151548.3944-1-chunkuang.hu@kernel.org
2025-10-31Merge tag 'drm-misc-next-2025-10-28' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.19-rc1: UAPI Changes: Cross-subsystem Changes: - Update DT bindings for renesas and powervr-rogue. - Update MAINTAINERS email and add spsc_queue. Core Changes: - Allow ttm page protection flags on risc-v. - Move freeing of drm client memory to driver. Driver Changes: - Assorted small fixes and updates to qaic, ivpu, st7571-i2c, gud, amdxdna. - Allow configuration of vkms' display through configfs. - Add Arm Ethos-U65/U85 accel driver. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/32b43261-3c99-49d9-92ee-615ada1d01e8@lankhorst.se
2025-10-31Merge tag 'drm-xe-next-2025-10-28' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next Driver Changes: More xe3p support (Harish, Brian, Balasubramani, Matt Roper) Make panic support work on VRAM for display (Maarten) Fix stolen size check (Shuicheng) xe_pci_test update (Gustavo) VF migration updates (Tomasz) A couple of fixes around allocation and PM references (Matt Brost) Migration update for the MEM_COPY instruction (Matt Auld) Initial CRI support (Balasubramani, Matt Roper) Use SVM range helpers in PT layer (Matt Brost) Drop MAX_GT_TYPE_CHARS constant (Matt Roper) Fix spelling and typos (Sanjay) Fix VF FLR synchronization between all GTs (Michal) Add a Workaround (Nitin) Access VF's register using dedicated MMIO view (Michal) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> Link: https://patch.msgid.link/aQCl9uJxN6CWJ8Vg@fedora
2025-10-31Merge tag 'amd-drm-next-6.19-2025-10-24' of ↵Simona Vetter
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-10-24: amdgpu: - HMM cleanup - Add new RAS framework - DML2.1 updates - YCbCr420 fixes - DC FP fixes - DMUB fixes - LTTPR fixes - DTBCLK fixes - DMU cursor offload handling - Userq validation improvements - Misc code cleanups - Unify shutdown callback handling - Suspend improvements - Power limit code cleanup - Fence cleanup - IP Discovery cleanup - SR-IOV fixes - AUX backlight fixes - DCN 3.5 fixes - HDMI compliance fixes - DCN 4.0.1 cursor updates - DCN interrupt fix - DC KMS full update improvements - Add additional HDCP traces - DCN 3.2 fixes - DP MST fixes - Add support for new SR-IOV mailbox interface Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20251024175249.58099-1-alexander.deucher@amd.com
2025-10-31drm/xe/xe3: Extend wa_14023061436Tangudu Tilak Tirumalesh
Extend wa_14023061436 to Graphics Versions 30.03, 30.04 and 30.05. Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251030154626.3124565-1-tilak.tirumalesh.tangudu@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-10-31drm/xe: highlight reserved PAT entries in dump outputXin Wang
Enhance the PAT table dump by marking reserved entries with an asterisk (*) for improved readability and debugging. V2: Added a note in the "PAT table" header explaining the meaning of the asterisk(*) to improve clarity for readers. (Matt Roper) V3: Introduced a valid field in struct xe_pat_table_entry to explicitly track whether an entry is valid or reserved, avoiding reliance on coh_mode == 0. (Matt Roper) Signed-off-by: Xin Wang <x.wang@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251030221734.1058350-1-x.wang@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-10-31drm/tidss: Set vblank (event) time at crtc_atomic_enableTomi Valkeinen
It was reported that Weston stops at an assert, which checks that the page flip event timestamp is the same or newer than the previous timestamp: weston_output_finish_frame: Assertion `timespec_sub_to_nsec(stamp, &output->frame_time) >= 0' failed. With manual tests, I can see that when I enable the CRTC, I get a page flip event with a timestamp of 0. Tracking this down led to drm_reset_vblank_timestamp() which does "t_vblank = 0" if "high-precision query" is not available. TI DSS does not have any hardware timestamping, and thus the default ktime_get() is used in the DRM framework to get the vblank timestamp, and ktime_get() is not "high precision" here. It is not quite clear why the framework behaves this way, but I assume the idea is that drm_crtc_vblank_on(), which calls drm_reset_vblank_timestamp(), can be called at any time, and thus ktime_get() wouldn't give a good timestamp. And, the idea is that the driver would wait until next vblank after the CRTC enable, and then we could get a good timestamp. This is hinted in the comment: "reinitialize delayed at next vblank interrupt and assign 0 for now". I think that makes sense. However, when we enable the CRTC in TI DSS, i.e. we write the enable bit to the hardware, that's the exact moment when the "vblank cycle" starts. It is the zero point in the cycle, and thus ktime_get() would give a good timestamp. I am not sure if this is applicable to other hardware, and if so, how should it be solved in the framework. So, let's fix this in the tidss driver at least for now. This patch updates the vblank->time manually to ktime_get() just before sending the vblank event, and we enable the crtc just before calling ktime_get(). To get even more exact timing, the dispc_vp_enable() is moved inside the event_lock spinlock. With this, we get a proper timestamp for the page flip event from enabling the CRTC, and Weston is happy. Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-2-c2aedf31e2c9@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Closes: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1553964/processor-sdk-am62x-weston-fails-to-wake-from-idle-time-sleep-restarts-after-sigterm Closes: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1416342/am625-am625-doesn-t-wake-up-from-standy-when-idle-time-is-configured-in-weston-ini
2025-10-31drm/tidss: Restructure dispc_vp_prepare() and dispc_vp_enable()Tomi Valkeinen
tidss_crtc.c calls dispc_vp_prepare() and dispc_vp_enable() in that order, next to each other. dispc_vp_prepare() does preparations for enabling the crtc, by writing some registers, and dispc_vp_enable() does more preparations. As the last thing, dispc_vp_enable() enables the CRTC by writing the enable bit. There might have been a reason at some point in the history for this split, but I can't find any point to it. They also do a bit of overlapping work: both call dispc_vp_find_bus_fmt(). They could as well be a single function. But instead of combining them, this patch moves everything from dispc_vp_enable() to dispc_vp_prepare(), except the actual CRTC enable bit write. The reason for this is that unlike all the preparatory register writes, CRTC enable has an immediate effect, starting the timing generator and the CRTC as a whole. Thus it may be important to time the enable just right (as we do in the next patch). No functional changes. Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-1-c2aedf31e2c9@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-31drm/sched: Add warning for removing hack in drm_sched_fini()Philipp Stanner
The assembled developers agreed at the X.Org Developers Conference 2025 that the hack added for amdgpu in drm_sched_fini() shall be removed. It shouldn't be needed by amdgpu anymore. As it's unclear whether all drivers really follow the life time rule of entities having to be torn down before their scheduler, it is reasonable to warn for a while before removing the hack. Add a warning in drm_sched_fini() that fires if an entity is still active. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20251023123429.139848-2-phasta@kernel.org
2025-10-31drm/imagination: Fix reference to devm_platform_get_and_ioremap_resource()Geert Uytterhoeven
The call to devm_platform_ioremap_resource() was replaced by a call to devm_platform_get_and_ioremap_resource(), but the comment referring to the function's possible returned error codes was not updated. Fixes: 927f3e0253c11276 ("drm/imagination: Implement MIPS firmware processor and MMU support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://patch.msgid.link/2266514318480d17f52c7e5e67578dae6827914e.1761745586.git.geert+renesas@glider.be Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-10-31drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBCVinod Govindapillai
There is a hw restriction that we could enable the FBC for FP16 formats only if the pixel normalization block is enabled. Hence enable the pixel normalizer block with normalzation factor as 1.0 for the supported FP16 formats to get the FBC enabled. Two existing helper function definitions are moved up to avoid the forward declarations as part of this patch as well. v2: sw/hw state differentiation on handling pixel normalizer (Jani) Bspec: 69863, 68881 Cc: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251027134001.325064-5-vinod.govindapillai@intel.com
2025-10-31drm/i915/xe3p_lpd: extract pixel format valid routine for FP16 formatsVinod Govindapillai
As the pixel normalizer block is needed only for the FP16 formats, separating out the FP16 formats handling will benefit in selectively enabling the pixel normalizer block in the following patch. Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251027134001.325064-4-vinod.govindapillai@intel.com
2025-10-31drm/i915/xe3p_lpd: Add FBC support for FP16 formatsVinod Govindapillai
Add supported FP16 formats for FBC. FBC can be enabled with FP16 formats only when plane pixel normalizer block is enabled. The follow up patches will handle the pixel normalizer block configuration. v2: changes related to comments to use better tracking of pixel normalizer Bspec: 6881, 69863, 68904 Cc: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251027134001.325064-3-vinod.govindapillai@intel.com
2025-10-31drm/i915/xe3p_lpd: Extend FBC support to UINT16 formatsSai Teja Pottumuttu
Starting Xe3p_LPD, FBC is supported on UINT16 formats as well. Also UINT16 being a 64bpp format, will use cpp of 8 for cfb stride and thus size calculations. v2: simplify getting the cpp per format (Ville) simplify the pixel format is valid for xe3p_lp (Vinod) Cc: Shekhar Chauhan <shekhar.chauhan@intel.com> BSpec: 68881, 68904, 69560 Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251027134001.325064-2-vinod.govindapillai@intel.com
2025-10-31drm/xe/compat: reduce i915_utils.[ch]Jani Nikula
Reduce the compat i915_utils.h to only cover the requirements of MISSING_CASE() in soc/ and the few i915_inject_probe_failure() instances, instead of including the entire i915_utils.h from i915. This prevents new users for the utilities from cropping up. With this, we can remove the xe/display/ext/i915_utils.c altogether. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/c02f82e45f31caf95bd1339080b9099c3b7190be.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915/display: switch to intel_display_utils.hJani Nikula
The remaining utils display needs from i915_utils.h are primarily MISSING_CASE() and fetch_and_zero(), with a couple of i915_inject_probe_failure() uses. To avoid excessive churn, add duplicates of MISSING_CASE() and fetch_and_zero() to intel_display_utils.h, and switch display to use the display utils. As long as there are display files that include i915_drv.h, which includes i915_utils.h, we'll need #ifndef guards for MISSING_CASE() and fetch_and_zero() in both utils headers. We can remove them once display no longer depends on i915_drv.h. A couple of files in display still need i915_utils.h for i915_inject_probe_failure(). Annotate this. They will be handled separately. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/79f9e31ca64c8c045834d48e20ceb0c515d1e9e1.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915/display: add intel_display_vtd_active()Jani Nikula
Add intel_display_vtd_active() to utils. It's intentional duplication with i915_utils.h i915_vtd_active(), but reduces duplication with xe. Win some, lose some. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/e022166af7c67f43904e2d0fc87bc5c13e0f1204.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915/display: add intel_display_run_as_guest()Jani Nikula
Add intel_display_utils.c for display utilities that need more than a header. Start off with intel_display_run_as_guest(). The implementation is intentional duplication of the i915_utils.h i915_run_as_guest(), with the idea that it's small enough to not matter. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/469f9c41e0c3e3099314a3cf1a7671bf36ec8ffd.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915/display: create intel_display_utils.hJani Nikula
Start a file for display specific generic utilities. Move KHz() and MHz() helpers there first. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/dbdd1915466850293b9737b751170dd225197873.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915: split out separate files for jiffies timeout and wait helpersJani Nikula
Add i915_jiffies.h and intel_display_jiffies.h for jiffies timeout and wait helpers, and use them separately from i915 and display. This helps reduce the display dependency on i915_utils.h. Long term, both msecs_to_jiffies_timeout() and wait_remaining_ms_from_jiffies() really belong in core kernel headers, but for now unblock display refactoring. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/d8bc62b3a81afa05c849dde9b0f633572eaf5611.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915/dsi: debug log send packet sequence contentsJani Nikula
This might help debug issues better than just debug logging the function name. v2: Debug log type as hex (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029084603.2254982-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/i915/dsi: log send packet sequence errorsJani Nikula
We might be getting send packet sequence errors and never know. Log them as errors. Also upgrade the not supported read commands to errors. v2: Also error log -EOPNOTSUPP (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029084603.2254982-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31drm/panel: ilitek-ili9882t: Add support for Ilitek IL79900A-based panelsLangyan Ye
The Ilitek IL79900A display controller is similar to the ILI9882T and can be supported within the existing `panel-ilitek-ili9882t.c` driver. This patch extends the ILI9882T driver to handle IL79900A-based panels, such as the Tianma TL121BVMS07-00. The IL79900A uses a similar command sequence and initialization flow, with minor differences in power supply configuration and timing. Signed-off-by: Langyan Ye <yelangyan@huaqin.corp-partner.google.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251031100447.253164-3-yelangyan@huaqin.corp-partner.google.com
2025-10-31drm/sched: Fix comment in drm_sched_run_job_work()Philipp Stanner
drm_sched_run_job_work() contains a comment which explains that an entity being NULL means that there is no more work to do. It can, however, also mean that there is work, but the scheduler doesn't have enough credits to process the jobs right now. Provide this detail in the comment. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20251028134602.94125-3-phasta@kernel.org
2025-10-31drm/i915/gt: Use standard API for seqcount read in TLB invalidationAndi Shyti
seqprop_sequence() is not intended for use outside seqlock.h. Although it is accessible as a macro, it is meant to be used only internally within the header. Replace it with its proper wrapper, raw_read_seqcount(). Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Co-developed-by: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@linux.intel.com> Cc: Christoph Lameter (Ampere) <cl@gentwo.org> Reviewed-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Link: https://lore.kernel.org/r/20251023132802.654061-1-andi.shyti@linux.intel.com
2025-10-31drm/i915: Wait for page_sizes_gtt in gtt selftest on CHV/BXT+VTDJanusz Krzysztofik
VMA pinning to GGTT is now commited asynchronously in CHV / BXT+VDT environments to avoid lock inversion among reservation_ww and cpu_hotplug locks, the latter acquired from stop_machine(). Then, vma->resource->page_sizes_gtt the test uses as shift count may still be not populated (equal 0) after i915_vma_pin() returns. Wait for VMA bind completion in those cases to avoid shift-out-of-bounds kernel warnings and the test case failing with -EBADSLT. v2: Explain why VMA pinning is commited asynchronously on CHV/BXT+VTD (Krzysztof), - use more precise wording in commit description. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Acked-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20251023082925.351307-8-janusz.krzysztofik@linux.intel.com
2025-10-31drm/i915: Wait longer for threads in migrate selftest on CHV/BXT+VTDJanusz Krzysztofik
When running on a Cherryview, or on a Broxton with VTD enabled, pinning of a VMA to GGTT is now committed asynchronously to avoid lock inversion among reservation_ww and cpu_hotplug locks, the latter acquired from stop_machine(). That may defer further processing of resources that depend on that VMA. As a consequence, a 10ms delay in a multithreaded migrate test case may occur too short and still incomplete threads may be interrupted, and the test case may fail with -ERESTARTSYS or -EINTR error code returned by any of those threads. Extend the delay to empirically determined 100ms on affected platforms. v3: Add an in-line comment that explains why 100ms (Andi). v2: Fix spelling (Sebastian, Krzysztof), - explain why VMA pinning is commited asynchronously on CHV/BXT+VTD (Krzysztof). Cc: Andi Shyti <andi.shyti@kernel.org> Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Acked-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20251023082925.351307-7-janusz.krzysztofik@linux.intel.com
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