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This must have been messed up while merging, the intention was
clearly to unlock there.
Change-Id: Icf525a51d4899dc718710ec56a4d3fd2150501cd
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/96139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Pass the correct gart device pointer.
Change-Id: Ia54c3df7ce013855bf8843161f5ee0816482bda6
Reviewed-on: http://git-master/r/90064
Reviewed-by: Vandana Salve <vsalve@nvidia.com>
Tested-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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The mainline IOMMU API v3.3-rc1 has been changed so that bytes are
used in mapping size instead of page order and page-by-page iteration
is taken care of by iommu core.
The rest are mostly for maintainability:
$ git co iommu/next drivers/iommu/tegra-gart.c
Change-Id: Id88ae8d23d11f4e003d11ec1e4223a72215ad142
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/78138
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This
patch implements struct iommu_ops for GART for the upper IOMMU API.
This H/W module supports only single virtual address space(domain),
and manages a single level 1-to-1 mapping H/W translation page table.
Change-Id: I2f550bf0e14d9f994abdde79b835ddfe815faa5a
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/75945
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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