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path: root/drivers/mmc
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2012-01-09Revert "ENGR00125411 eMMC: Boot Partition switch func used in MFG tool"Jason Liu
This reverts commit 9f26eaa231cf2a19064c5589a3515bdd60af596a.
2012-01-09Revert "ENGR00126228 eMMC: Configure boot_partition_enable"Jason Liu
This reverts commit b35268ca923a8785ab311170b0a84210b3c7863e.
2012-01-09Revert "ENGR00133884 eMMC: improve boot_info message output"Jason Liu
This reverts commit 70c73cd0dde38fd44b4c019cb7288cbea90008f3.
2012-01-09Revert "ENGR00152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller"Jason Liu
This reverts commit 7da674ed743b6feb9471fc290e10fc21194f09be.
2012-01-09Revert "ENGR00154217 [MX6Q/D]fix mmc suspend/resume issue."Jason Liu
This reverts commit e3f2cd88631b667173047e66d311ba0f815f8a35.
2012-01-09Revert "ENGR00139261 [MX6Q]support 8 bit MMC and eMMC DDR mode"Jason Liu
This reverts commit bcc0edfb10bfd8ab2974b0cf108490be72281146. Conflicts: drivers/mmc/host/sdhci-esdhc-imx.c drivers/mmc/host/sdhci.h Signed-off-by: Jason Liu <jason.hui@linaro.org>
2012-01-09Revert "ENGR00155612-3 [mx6q]add delay after cmd6 for eMMC compatibility"Jason Liu
This reverts commit dee9bc3d9c98bc45ad42960a6650dffc66140d19.
2012-01-09ENGR00162792-1 [IMX6Q] mmc host pm caps should be board specificRyan QIAN
- move mmc host pm caps into board specific section Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-01-09ENGR00162681 iMX6 SDIO WIFI AR6003 failed to work on resumingRyan QIAN
- Add keep power option to mmc pm_caps, since power of SD can not be cut on mx6, which should be indicated in host pm cap. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-01-09ENGR00162335-2 [mx6q_arm2]SD card 3.0 can't be recognizedTony Lin
change mmc rescan delay to 500ms from 200ms. this will make insert and removal reflection more stable. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00160940-2 [MX6Q]sdhci: add delay line configurationTony Lin
driver will configure the delay line setting due to board data after DDR mode is enabled. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00160241 [mx6q]sdhci: kernel panic caused by clock enable in interruptTony Lin
cancel the timer even in interrupt context to fix following error log: clk_enable cannot be called in an interrupt context kernel BUG at arch/arm/plat-mxc/clock.c:104! Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = 80004000 [00000000] *pgd=00000000 Internal error: Oops: 805 [#1] PREEMPT SMP last sysfs file: /sys/devices/platform/fsl-ehci.1/usb2/2-0:1.0/uevent Modules linked in: CPU: 1 Tainted: G W (2.6.38-00559-g4938069-dirty #30) PC is at __bug+0x18/0x24 LR is at __bug+0x14/0x24 pc : [<80039eec>] lr : [<80039ee8>] psr: 20000193 sp : e6067eb8 ip : ec91a000 fp : 00000000 r10: 8002eacc r9 : 805738e0 r8 : 00000023 r7 : 60000113 r6 : e67c92a8 r5 : 00000001 r4 : 8054d8f8 r3 : 00000000 r2 : 00000104 r1 : 60000193 r0 : 00000033 Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7d Table: 7461804a DAC: 00000015 Process swapper (pid: 0, stack limit = 0xe60662f0) Stack: (0xe6067eb8 to 0xe6068000) 7ea0: 8054d8f8 8004914c 7ec0: e67c9280 802fa9e4 e67c9280 00000100 e67c92a8 802f7754 e67c9280 e61ade14 7ee0: e67c92a8 802f8f60 e67c9324 e67c9328 00000000 e6066000 80547c40 802ebe80 7f00: e67c9324 8005d828 8005d71c 00000018 00000001 e6066000 80538040 80538040 7f20: 805738e0 00000103 8002e9f4 8005dbf0 2faf2e40 0000030e 2faf2e40 00000006 7f40: 00000009 00000001 00000000 80547c40 8002f380 00000000 80573900 00000001 7f60: e6066000 00000000 00000000 8005dd30 80547c40 80030390 ffffffff f2a00100 7f80: 0000001d 00000002 00000001 8003600c 00000020 80547a84 e6067fd8 00000000 7fa0: e6066000 8056e1e4 803fdd54 8054ae9c 70000000 412fc09a 00000000 00000000 7fc0: 00000000 e6067fd8 800372ac 800372b0 60000013 ffffffff e6066000 800378d8 7fe0: 7606806a 00000015 10c03c7d 8056e36c 70000000 103f628c 78fffff6 debdbeb9 (__bug+0x18/0x24) from [<8004914c>] (clk_enable+0x100/0x118) (clk_enable+0x100/0x118) from [<802fa9e4>] (plt_clk_ctrl+0x28/0x34) (plt_clk_ctrl+0x28/0x34) from [<802f7754>] (sdhci_enable_clk+0x5c/0x80) (sdhci_enable_clk+0x5c/0x80) from [<802f8f60>] (sdhci_request+0xac/0x188) (sdhci_request+0xac/0x188) from [<802ebe80>] (mmc_request_done+0x74/0x78) (mmc_request_done+0x74/0x78) from [<8005d828>] (tasklet_action+0x10c/0x15c) (tasklet_action+0x10c/0x15c) from [<8005dbf0>] (__do_softirq+0xa8/0x140) (__do_softirq+0xa8/0x140) from [<8005dd30>] (irq_exit+0xa8/0xb0) (irq_exit+0xa8/0xb0) from [<80030390>] (do_local_timer+0x54/0x7c) (do_local_timer+0x54/0x7c) from [<8003600c>] (__irq_svc+0x4c/0xe8) Exception stack(0xe6067f90 to 0xe6067fd8) 7f80: 00000020 80547a84 e6067fd8 00000000 7fa0: e6066000 8056e1e4 803fdd54 8054ae9c 70000000 412fc09a 00000000 00000000 7fc0: 00000000 e6067fd8 800372ac 800372b0 60000013 ffffffff ...... Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00155612-4 [mx6q]change the delay after clock frequence change to 1msTony Lin
100ms is too long delay, thus it impact other tasks scheduling. for example, nfs reports timeout if two sd card is inserted because the 100ms delay occupies cpu too long. 1ms value is evaluated by IC engineer. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00155612-3 [mx6q]add delay after cmd6 for eMMC compatibilityTony Lin
sandisk eMMC4.4 cards need a 1ms delay after cmd6 (switch cmd) which is confirm by sandisk errata. add 1ms delay after cmd6 to provide more robustness and compatiblity of our driver supporting eMMC4.4 cards. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00155612-2 [mx6q]dynamically sd pad setting changeTony Lin
call platform callback funtion, if exists, when clock frequency is changed. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00155611 [mx6q]correct eMMC DDR mode clock settingTony Lin
in uSDHC controller, SDCLKFS field in SYS_CTRL register is defined differently from eSDHC In Single Data Rate mode(DDR_EN bit of MIXERCTRL is '0') Only the following settings are allowed: 80h) Base clock divided by 256 40h) Base clock divided by 128 20h) Base clock divided by 64 10h) Base clock divided by 32 08h) Base clock divided by 16 04h) Base clock divided by 8 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 While in Dual Data Rate mode(DDR_EN bit of MIXERCTRL is '1') Only the following settings are allowed: 80h) Base clock divided by 512 40h) Base clock divided by 256 20h) Base clock divided by 128 10h) Base clock divided by 64 08h) Base clock divided by 32 04h) Base clock divided by 16 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 so the clock setting function should be changed to fit the definition Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00153895 [MX6Q]SD: SD3 clock is not off, when no SD card is in useTony Lin
the patch brings in clock management, not only card removal will gate off corresponding SD clock, but also a timeout after last request will gate off the SD clock. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00155288 [mx6q]sd dat1 glitch causes system panicTony Lin
some sd cards insertion will cause a glitch on sd dat1 which is also a card interrupt signal. Thus the wrongly generated card interrupt will make system panic because there's no registered sdio interrupt handler. the patch fixes this issue. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00139261 [MX6Q]support 8 bit MMC and eMMC DDR modeTony Lin
enable 8 bit MMC mode according to mmc stack. enable eMMC DDR mode according to mmc stack, but change sdhci a little, since sdhci does not support DDR mode so far. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00154217 [MX6Q/D]fix mmc suspend/resume issue.Tony Lin
following log is the scenario. mmc0: host doesn't support card's voltages mmc0: error -110 during resume (card was removed?) can't clear ocr in power off, instead we need to set it to the highest bit of ocr_avail. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00153221 [MX6Q uSDHC]workaround for TC intr coming ealier than DMA intrTony Lin
if TC interrupt bit is set but DMA interrupt bit is clear, read status register again in case DMA interrupt will come in next time cycle Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00153160 fix card interrupt issue on uSDHC and eSDHCTony Lin
uSDHC: card interrupt storm if we do not clear card interrupt status by sw. eSDHC: card interrupt will be lost if we do not set D3CD bit. apply the workarounds in sdhci-esdhc-imx.c to avoid adding new QUIRKs. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00152547-04 [MX6Q]add SDHC3.0 support on uSDHC controllerTony Lin
modify host controller driver to meet SD3.0 spec. including voltage switch, and tuning control. add a function pointer for bus driver to do tuning preparation, in case some host controller like uSDHC does not tune automatically. it needs change delay line before tuning. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00152547-03 [MX6Q]add SDHC3.0 support on uSDHC controllerTony Lin
add voltage switch function due to SDHC3.0 spec requirement add tuning function due to SDHC3.0 spec requirement extend some functions to support SDR50 & SDR104 speed mode Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-01-09ENGR00139229-4 SDHC: Add SDHC support for i.MX6Zeng Zhaoming
Add sdhc support to make it easy mount rootfs from SD card. Merge from imx6_bringup branch. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Merged-by: Zeng Zhaoming <b32542@freescale.com>
2012-01-09ENGR00142266-2 eSDHC:Add the GPIO CD/WP on MX5x boardsRichard Zhu
sdhc: add the CD/WP on the MX5x boards Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-01-09ENGR00133884 eMMC: improve boot_info message outputFrank Li
Output bit means of important esd_csd register Read esd_csd info each time when cat boot_info becasue user may change config affect esd_csd value. boot_info:0x07; ALT_BOOT_MODE:1 - Supports alternate boot method DDR_BOOT_MODE:1 - Supports alternate dual data rate during boot HS_BOOTMODE:1 - Supports high speed timing during boot boot_size:0512KB boot_partition:0x48; BOOT_ACK:1 - Boot acknowledge sent during boot operation BOOT_PARTITION-ENABLE: 1 - Boot partition 1 enabled PARTITION_ACCESS:0 - No access to boot partition boot_bus:0x01 BOOT_MODE:0 - Use single data rate + backward compatible timings in boot operation RESET_BOOT_BUS_WIDTH:0 - Reset bus width to x1, single data rate and backward compatible timings after boot operation BOOT_BUS_WIDTH:1 - x4 (sdr/ddr) bus width in boot operation mode Signed-off-by: Frank Li <Frank.Li@freescale.com>
2012-01-09ENGR00126228 eMMC: Configure boot_partition_enableRichard Zhu
Enable the configurations of the boot enable on the eMMC cards. Add the interface that used to configure the boot_bus_width In order to make sure that the re-read the ext-csd of card can be completed successfully, add the method to wait for the finish of the busy state. NOTE: The following are the valid inputs when configure the boot bus width of the eMMC cards. +--------------------------------------------------------------------+ | Bit7 Bit6 Bit5 | Bit4 Bit3 | Bit2 | Bit1 Bit0 | |----------------|----------------------------------|----------------| | X | BOOT_MODE | RESET_BOOT_BUS_WIDTH | BOOT_BUS_WIDTH | +--------------------------------------------------------------------+ Bit [4:3] : BOOT_MODE (non-volatile) 0x0 : Use single data rate + backward compatible timings in boot operation (default) 0x1 : Use single data rate + high speed timings in boot operation mode 0x2 : Use dual data rate in boot operation 0x3 : Reserved Bit [2]: RESET_BOOT_BUS_WIDTH (non-volatile) 0x0 : Reset bus width to x1, single data rate and backward compatible timings after boot operation (default) 0x1 : Retain boot bus width and boot mode after boot operation Bit[1:0] : BOOT_BUS_WIDTH (non-volatile) 0x0 : x1 (sdr) or x4 (ddr) bus width in boot operation mode (default) 0x1 : x4 (sdr/ddr) bus width in boot operation mode 0x2 : x8 (sdr/ddr) bus width in boot operation mode 0x3 : Reserved The following are the valid inputs when configure the boot partitions of the eMMC cards. +------------------------------------------------------------+ | Bit7 | Bit6 | Bit5 Bit4 Bit3 | Bit2 Bit1 Bit0 | |------|----------|-----------------------|------------------| | X | BOOT_ACK | BOOT_PARTITION_ENABLE | PARTITION_ACCESS | +------------------------------------------------------------+ Bit7: Reserved Bit6: always set to vaule '1' when boot_part is enabled Bit[5:3]: 0x0 : Device not boot enabled (default) 0x1 : Boot partition 1 enabled for boot 0x2 : Boot partition 2 enabled for boot 0x7 : User area enabled for boot Bit[2:0]: 0x0 : No access to boot partition (default) 0x1 : R/W boot partition 1 0x2 : R/W boot partition 2 So only the '0, 1, 2; 8, 9, 10; 16, 17, 18; 56, 57, 58' are valid parameters when configure the boot_partiton. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-01-09ENGR00125411 eMMC: Boot Partition switch func used in MFG toolRichard Zhu
User can get eMMC partitions info from user space layer in linux OS enviroment. User can do switch operations between the eMMC boot partitions and the user partition. User can access the eMMC boot partitions from user space layer in linux OS enviroment. NOTE:This func had been verified on TOSHIBA eMMC44 card only. Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Rob Herring <r.herring@freescale.com>
2011-12-21mmc: mxcmmc: fix falling back to PIOSascha Hauer
commit e58f516ff4730c4047c3f104b061f7a03e9a263c upstream. When we can't configure the dma channel we want to fall back to PIO. We do this by setting host->do_dma to zero. This does not work as do_dma is used to see whether dma can be used for the current transfer. Instead, we have to set host->dma to NULL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-11-11mmc: core: ext_csd.raw_* used in comparison but never setAndrei Warkentin
commit 5238acbe36dd5100fb6b035a995ae5fc89dd0708 upstream. f39b2dd9d ("mmc: core: Bus width testing needs to handle suspend/resume") added code to only compare read-only ext_csd fields in bus width testing code, yet it's comparing some fields that are never set. The affected fields are ext_csd.raw_erased_mem_count and ext_csd.raw_partition_support. Signed-off-by: Andrei Warkentin <andrey.warkentin@gmail.com> Acked-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-11-11mmc: core: Fix hangs related to insert/remove of cardsUlf Hansson
commit 7f7e4129c23f0419257184dff6fec89d2d5a8964 upstream. During a rescan operation mmc_attach(sd|mmc|sdio) functions are called. The error handling in these function can trigger a detach of the bus, which also meant a power off. This is not notified by the rescan operation which then continues to the next attach function. If a power off has been done, the framework must never send any new commands to the host driver, without first doing a new power up. This will most likely trigger any host driver to hang. Moving power off out of detach and instead handle power off separately when it is actually needed, solves the issue. Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-10-16mmc: mxs-mmc: fix clock rate settingKoen Beel
commit d982dcdc4e64eb1881df44b0035a8268bf1ab067 upstream. Fix clock rate setting in the mxs-mmc driver. Previously, if div2 was 0 then the value for TIMING_CLOCK_RATE would have been 255 instead of 0. The limits for div1 (TIMING_CLOCK_DIVIDE) and div2 (TIMING_CLOCK_RATE+1) were also not correctly defined. Can easily be reproduced on mx23evk: default clock for high speed sdio cards is 50 MHz. With a SSP_CLK of 28.8 MHz default), this resulted in an actual clock rate of about 56 kHz. Tested on mx23evk. Signed-off-by: Koen Beel <koen.beel@barco.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-10-03mmc: sdhci-s3c: Fix mmc card I/O problemGirish K S
commit 49bb1e619568ec84785ceb366f07db2a6f0b64cc upstream. This patch fixes the problem in sdhci-s3c host driver for Samsung Soc's. During the card identification stage the mmc core driver enumerates for the best bus width in combination with the highest available data rate. It starts enumerating from the highest bus width (8) to lowest width (1). In case of few MMC cards the 4-bit bus enumeration fails and tries the 1-bit bus enumeration. When switched to 1-bit bus mode the host driver has to clear the previous bus width setting and apply the new setting. The current patch will clear the previous bus mode and apply the new mode setting. Signed-off-by: Girish K S <girish.shivananjappa@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-10-03mmc: core: use non-reentrant workqueue for clock gatingMika Westerberg
commit 50a50f9248497484c678631a9c1a719f1aaeab79 upstream. The default multithread workqueue can cause the same work to be executed concurrently on a different CPUs. This isn't really suitable for clock gating as it might already gated the clock and gating it twice results both host->clk_old and host->ios.clock to be set to 0. To prevent this from happening we use system_nrt_wq instead. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-10-03mmc: core: prevent aggressive clock gating racing with ios updatesMika Westerberg
commit 778e277cb82411c9002ca28ccbd216c4d9eb9158 upstream. We have seen at least two different races when clock gating kicks in in a middle of ios structure update. First one happens when ios->clock is changed outside of aggressive clock gating framework, for example via mmc_set_clock(). The race might happen when we run following code: mmc_set_ios(): ... if (ios->clock > 0) mmc_set_ungated(host); Now if gating kicks in right after the condition check we end up setting host->clk_gated to false even though we have just gated the clock. Next time a request is started we try to ungate and restore the clock in mmc_host_clk_hold(). However since we have host->clk_gated set to false the original clock is not restored. This eventually will cause the host controller to hang since its clock is disabled while we are trying to issue a request. For example on Intel Medfield platform we see: [ 13.818610] mmc2: Timeout waiting for hardware interrupt. [ 13.818698] sdhci: =========== REGISTER DUMP (mmc2)=========== [ 13.818753] sdhci: Sys addr: 0x00000000 | Version: 0x00008901 [ 13.818804] sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 [ 13.818853] sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 13.818903] sdhci: Present: 0x1fff0000 | Host ctl: 0x00000001 [ 13.818951] sdhci: Power: 0x0000000d | Blk gap: 0x00000000 [ 13.819000] sdhci: Wake-up: 0x00000000 | Clock: 0x00000000 [ 13.819049] sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 [ 13.819098] sdhci: Int enab: 0x00ff00c3 | Sig enab: 0x00ff00c3 [ 13.819147] sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 [ 13.819196] sdhci: Caps: 0x6bee32b2 | Caps_1: 0x00000000 [ 13.819245] sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 [ 13.819292] sdhci: Host ctl2: 0x00000000 [ 13.819331] sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000 [ 13.819377] sdhci: =========================================== [ 13.919605] mmc2: Reset 0x2 never completed. and it never recovers. Second race might happen while running mmc_power_off(): static void mmc_power_off(struct mmc_host *host) { host->ios.clock = 0; host->ios.vdd = 0; [ clock gating kicks in here ] /* * Reset ocr mask to be the highest possible voltage supported for * this mmc host. This value will be used at next power up. */ host->ocr = 1 << (fls(host->ocr_avail) - 1); if (!mmc_host_is_spi(host)) { host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN; host->ios.chip_select = MMC_CS_DONTCARE; } host->ios.power_mode = MMC_POWER_OFF; host->ios.bus_width = MMC_BUS_WIDTH_1; host->ios.timing = MMC_TIMING_LEGACY; mmc_set_ios(host); } If the clock gating worker kicks in while we are only partially updated the ios structure the host controller gets incomplete ios and might not work as supposed. Again on Intel Medfield platform we get: [ 4.185349] kernel BUG at drivers/mmc/host/sdhci.c:1155! [ 4.185422] invalid opcode: 0000 [#1] PREEMPT SMP [ 4.185509] Modules linked in: [ 4.185565] [ 4.185608] Pid: 4, comm: kworker/0:0 Not tainted 3.0.0+ #240 Intel Corporation Medfield/iCDKA [ 4.185742] EIP: 0060:[<c136364e>] EFLAGS: 00010083 CPU: 0 [ 4.185827] EIP is at sdhci_set_power+0x3e/0xd0 [ 4.185891] EAX: f5ff98e0 EBX: f5ff98e0 ECX: 00000000 EDX: 00000001 [ 4.185970] ESI: f5ff977c EDI: f5ff9904 EBP: f644fe98 ESP: f644fe94 [ 4.186049] DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068 [ 4.186125] Process kworker/0:0 (pid: 4, ti=f644e000 task=f644c0e0 task.ti=f644e000) [ 4.186219] Stack: [ 4.186257] f5ff98e0 f644feb0 c1365173 00000282 f5ff9460 f5ff96e0 f5ff96e0 f644feec [ 4.186418] c1355bd8 f644c0e0 c1499c3d f5ff96e0 f644fed4 00000006 f5ff96e0 00000286 [ 4.186579] f644fedc c107922b f644feec 00000286 f5ff9460 f5ff9700 f644ff10 c135839e [ 4.186739] Call Trace: [ 4.186802] [<c1365173>] sdhci_set_ios+0x1c3/0x340 [ 4.186883] [<c1355bd8>] mmc_gate_clock+0x68/0x120 [ 4.186963] [<c1499c3d>] ? _raw_spin_unlock_irqrestore+0x4d/0x60 [ 4.187052] [<c107922b>] ? trace_hardirqs_on+0xb/0x10 [ 4.187134] [<c135839e>] mmc_host_clk_gate_delayed+0xbe/0x130 [ 4.187219] [<c105ec09>] ? process_one_work+0xf9/0x5b0 [ 4.187300] [<c135841d>] mmc_host_clk_gate_work+0xd/0x10 [ 4.187379] [<c105ec82>] process_one_work+0x172/0x5b0 [ 4.187457] [<c105ec09>] ? process_one_work+0xf9/0x5b0 [ 4.187538] [<c1358410>] ? mmc_host_clk_gate_delayed+0x130/0x130 [ 4.187625] [<c105f3c8>] worker_thread+0x118/0x330 [ 4.187700] [<c1496cee>] ? preempt_schedule+0x2e/0x50 [ 4.187779] [<c105f2b0>] ? rescuer_thread+0x1f0/0x1f0 [ 4.187857] [<c1062cf4>] kthread+0x74/0x80 [ 4.187931] [<c1062c80>] ? __init_kthread_worker+0x60/0x60 [ 4.188015] [<c149acfa>] kernel_thread_helper+0x6/0xd [ 4.188079] Code: 81 fa 00 00 04 00 0f 84 a7 00 00 00 7f 21 81 fa 80 00 00 00 0f 84 92 00 00 00 81 fa 00 00 0 [ 4.188780] EIP: [<c136364e>] sdhci_set_power+0x3e/0xd0 SS:ESP 0068:f644fe94 [ 4.188898] ---[ end trace a7b23eecc71777e4 ]--- This BUG() comes from the fact that ios.power_mode was still in previous value (MMC_POWER_ON) and ios.vdd was set to zero. We prevent these by inhibiting the clock gating while we update the ios structure. Both problems can be reproduced by simply running the device in a reboot loop. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-10-03mmc: rename mmc_host_clk_{ungate|gate} to mmc_host_clk_{hold|release}Mika Westerberg
commit 08c14071fda4e69abb9d5b1566651cd092b158d3 upstream. As per suggestion by Linus Walleij: > If you think the names of the functions are confusing then > you may rename them, say like this: > > mmc_host_clk_ungate() -> mmc_host_clk_hold() > mmc_host_clk_gate() -> mmc_host_clk_release() > > Which would make the usecases more clear (This is CC'd to stable@ because the next two patches, which fix observable races, depend on it.) Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-29mmc: sdhci: fix retuning timer wrongly deleted in sdhci_tasklet_finishAaron Lu
commit 78869618a886d33d8cdfcb78cf9b245b5250e465 upstream. Currently, the retuning timer for retuning mode 1 will be deleted in function sdhci_tasklet_finish after a mmc request done, which will make retuning timing never trigger again. This patch fixed this problem. Signed-off-by: Aaron Lu <Aaron.Lu@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-04mmc: sdhci-esdhc-imx: SDHCI_CARD_PRESENT does not get clearedShawn Guo
commit 803862a6f7de4939e0a557214e5e4b37e36f87ff upstream. The function esdhc_readl_le intends to clear bit SDHCI_CARD_PRESENT, when the card detect gpio tells there is no card. But it does not clear the bit actually. The patch gives a fix on that. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-07-13Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: mmc: core: Bus width testing needs to handle suspend/resume
2011-07-13mmc: core: Bus width testing needs to handle suspend/resumePhilip Rakity
On reading the ext_csd for the first time (in 1 bit mode), save the ext_csd information needed for bus width compare. On every pass we make re-reading the ext_csd, compare the data against the saved ext_csd data. This fixes a regression introduced in 3.0-rc1 by 08ee80cc397ac1a3 ("mmc: core: eMMC bus width may not work on all platforms"), which incorrectly assumed we would be re-reading the ext_csd at resume- time. Signed-off-by: Philip Rakity <prakity@marvell.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-07-06ARM: 6980/1: mmci: use StartBitErr to detect bad connectionsLinus Walleij
Stresstesting insert/remove of SD-cards can trigger a StartBitErr. This made the driver to hang in forever waiting for a non ocurring data timeout. This bit and interrupt is documented in the original PL180 TRM, just never implemented until now. Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-25mmc: queue: bring discard_granularity/alignment into line with SCSIAdrian Hunter
SCSI defines discard alignment as the offset to the first optimal discard. In the case of SD/MMC, that is always zero which is the default. SCSI defines discard granularity as a hint of a optimal discard size. That is much better expressed by the MMC "preferred erase size" (pref_erase) field. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: queue: append partition subname to queue thread nameAdrian Hunter
For example, an eMMC with 2 boot partitions will have 3 threads. The names change from: 40 ? 00:00:00 mmcqd/0 41 ? 00:00:00 mmcqd/0 42 ? 00:00:00 mmcqd/0 to: 40 ? 00:00:00 mmcqd/0 41 ? 00:00:00 mmcqd/0boot0 42 ? 00:00:00 mmcqd/0boot1 Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: core: make erase timeout calculation allow for gated clockAdrian Hunter
The erase timeout calculation may depend on clock rate which is zero if the clock is gated, so use mmc_host_clk_rate() which allows for that case. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: block: switch card to User Data Area when removing the block driverAdrian Hunter
The MMC block driver and other drivers (e.g. mmc-test) will expect the card to be switched to the User Data Area eMMC partition when they start. Hence the MMC block driver should ensure it is that way when it is removed. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: sdio: reset card during power_restoreDaniel Drake
mmc_sdio_power_restore() skips some steps that are performed in other power-related codepaths which are necessary to fully reset the card. Without this, runtime PM fails for SD8686 SDIO wifi on OLPC XO-1.5. Signed-off-by: Daniel Drake <dsd@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: sdhi: DMA slave ID 0 is invalidGuennadi Liakhovetski
Don't try to allocate DMA resources if the platform didn't specify positive DMA slave IDs. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: tmio: fix regression in TMIO_MMC_WRPROTECT_DISABLE handlingGuennadi Liakhovetski
Commit b6147490e6aac82 ("mmc: tmio: split core functionality, DMA and MFD glue") broke handling of the TMIO_MMC_WRPROTECT_DISABLE flag by the tmio-mmc driver. This patch restores the original behaviour. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: <stable@kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-06-25mmc: omap_hsmmc: use original sg_len for dma_unmap_sgPer Forlin
Don't use the returned sg_len from dma_map_sg() as inparameter to dma_unmap_sg(). Use the original sg_len for both dma_map_sg and dma_unmap_sg according to the documentation in DMA-API.txt. Signed-off-by: Per Forlin <per.forlin@linaro.org> Reviewed-by: Venkatraman S <svenkatr@ti.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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