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Change SOC conditionals to make them more forward-looking.
Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Configure the pull up and pull down drive strengths for sdmmc.
Bug 822057
Change-Id: Ic483f5311cdfdb6c35043ab33b5ff22462304de3
Reviewed-on: http://git-master/r/32607
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Switching off and switching on the power rails during
suspend and resume. Passing the power rail name, maxV
and minV through platform data.
Bug 793796
Change-Id: I6c80c1a23c9681043d11ffdd210dc6d2146bdd2e
Reviewed-on: http://git-master/r/29660
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Make SD card write protection GPIO optional.
Some boards such as Whistler do not support this GPIO.
Default behaviour for this case is write-enabled.
Bug 686892.
Change-Id: I5e16e2260e681145e52d604abcfa38135e2be873
Original-Change-Id: If5253bfbadeafbffdf4f69ff0315fcf572886e0e
Reviewed-in: http://git-master/r/#change,21101
Reviewed-on: http://git-master/r/27542
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Change-Id: I5e16e2260e681145e52d604abcfa38135e2be873
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this work around is no more required as proper fix is
done in bcm driver.
Bug 795460
Original-Change-Id: I3ad30c1211ae5492307d32e9788a8db977a54d94
Reviewed-on: http://git-master/r/26687
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ia17ac97478bf3b750c9122991543c0237a31c0ac
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Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a
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Enabling SDHCI_POWER_ON bit during SDIO resume. Without
this bit, SDIO card clock is not enabled and SDIO resume
fails.
Bug 802383
Original-Change-Id: I6d897c542ba2be625720804e0d04d81f0ce0cedb
Reviewed-on: http://git-master/r/23211
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I0b01fe847fa2f8e470775dd443e26a6a1895a0e5
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Enabling controller clock before MMC_POWER_UP to ensure
proper register read/writes. Currently, during initialization
SDHCI_POWER_ON is being set without controller clock enabled.
Original-Change-Id: Ifc7b9f14eaf1ad5641d6edabaae4eca050c0ac6f
Reviewed-on: http://git-master/r/23186
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I31b2d2a3075646e6b6605ad7c55dda3d621ebc7d
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Properly enabling/disabling all sdmmc clocks to ensure the
clock refcount is correctly maintained.
Clocks are disabled in suspend and set in resume.
Bug 793796
Original-Change-Id: I941b979e16c347df46761cd21a986fa7768ed705
Reviewed-on: http://git-master/r/23185
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I14c57c175291d6bce2dd08df0d54d984f073d568
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Fix build break on ventana due to improper use
of kernel config paramters.
Original-Change-Id: If6f54e1f305e960f8bf935058f48b0e77adce6c6
Reviewed-on: http://git-master/r/22639
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Ia78069e7c3413e031dcb2df61216bfb577a693b5
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Unsetting bus speed mode variable after reset to
ensure that the uhs mode is set properly.
Original-Change-Id: I098a0df1289acefe01c391da622132a3562382fe
Reviewed-on: http://git-master/r/22423
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Change-Id: I0ffd0ab93b7fb72e2a7ae8d060b264d4f735df03
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Set SDHCI_QUIRK_8_BIT_DATA if the platform supports 8-bit
data. If not, use 4-bit data width.
Bug 794550
Bug 796574
Bug 796220
Original-Change-Id: Icd8536e0e0b2db77d1443fbbf0ba6b90b51b62ca
Reviewed-on: http://git-master/r/20746
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I85a1f68f2faf0751ada631132b19116e3b574bc5
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this work around is enabling SDHCI_QUIRK_NO_SDIO_IRQ
to unblock power activity for CONFIG_ARCH_TEGRA_3X_SOC.
By this wifi is using polling mode.
BUG 795460
Original-Change-Id: I351021fb96537f1ac1ed525c1cec27c8fd4dea32
Reviewed-on: http://git-master/r/21107
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
Change-Id: Ibff8e8786ee560a823eb3b06079a964453b2e846
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Set SDHCI_QUIRK_BROKEN_CARD_DETECTION to support
sd card hot plug in/plug out detection.
Original-Change-Id: Ia0a748dc38b61a73460bee19b4a4544630aa163b
Reviewed-on: http://git-master/r/20586
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I366ad96995f2c5939e42c98a7f626811b279ad4e
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Enable polling for the card presence if there is no mechanism
for card detection.
Original-Change-Id: I7c38a1df61eb94f3555dc87adddff268079cd788
Reviewed-on: http://git-master/r/20585
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I376f3dc38d6f8844ab8847b05b84ceb71f83f7b9
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Added interface to configure tap delays. This
is required for the frequency tuning algorithm.
Bug 661035
Original-Change-Id: I7e835ac53456e4c0cd7bb62b10d605d6da869764
Reviewed-on: http://git-master/r/20047
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ide438d530aa6db22d8dbb5540c925d3a9ac9cfd7
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Implemented the frequency tuning by configuring tap
delays. This is required for SD 3.0 cards to work at
208 MHz on tegra.
Bug 661035
Original-Change-Id: Ie86b084473da090b329a0220d58a6753d7fb335b
Reviewed-on: http://git-master/r/20044
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ifb812ee2d807f35bff78f440f6da7f7f5673c2ce
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- corrected i2c driver registration sequence to 1st so that it will be suspended last
- disabled pmu based rtc since tps6591x-rtc driver not available
- disabled SDHCI_QUIRK_BROKEN_CARD_DETECTION which acquire wake lock forever
Original-Change-Id: Ia2feba6b429a0864aa780e7c2ae96e164010b832
Reviewed-on: http://git-master/r/19793
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Change-Id: I37eb6c932358f900c4dede8b55a1f120a16aefb7
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Pad calibration is not present in AP20. Doing this
only for T30 by checking for the config variable
CONFIG_ARCH_TEGRA_3x_SOC
Original-Change-Id: I922ae7d54928fc29c6c1aed83b2adcd36ce54ac2
Reviewed-on: http://git-master/r/19250
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Id9d4e0b8f43e464f5fa037c00679307cc4c46121
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Enabling hot plugin/plugout support for sd card using
a gpio.
Enabling write protect detection support for sd card
using a gpio.
Enabling SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk for
sdmmc on T30.
Bug 784133
Bug 786261
Original-Change-Id: Ie9a49472f4b2337a7e2b0eb52c2cb346b021f768
Reviewed-on: http://git-master/r/18438
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I5b41730281aa360b2ec29fd94c7644d008e8be28
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Doing voltage switching for SD3.0 cards to
support the new data transfer modes.
Added set_signalling_voltage function in ops
to handle voltage switching on controllers that
cannot switch the voltage directly.
Added support for SD3.0 specification.
Bug 661035
Original-Change-Id: I641b606fb6fadd65f0ff68c1a41c0aa25d2c9553
Reviewed-on: http://git-master/r/18701
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I4c285d26da9354369354e53bf42db4c3f4883351
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Enabling quirk SDHCI_QUIRK_BROKEN_VOLTAGE_SWITCHING.
Added tegra_sdhci_set_signalling_voltage function
to do switch signalling voltage.
Disabling quirk SDHCI_QUIRK_NO_VERSION_REG for Tegra3.
Doing Auto Calibration when switching to 1.8V.
Corrected Typo error of the register name while writing
the tap delay value.
Setting the requested clock.
Configuring the base clock frequency for all
sdmmc instances.
Bug 661035
Original-Change-Id: If439135114785ec96be4f7bae8f224802679657b
Reviewed-on: http://git-master/r/18705
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I30781e38eb3ba52ccce351942e403f3bc2673fec
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On T30, block gap interrupt should not be set while enabling
card interrupt. If it is enabled, some of the card interrupts
are missing.
Bug 788298
Original-Change-Id: Icee59e90f89d443d8be4fa5b1e2dd3d903c85368
Reviewed-on: http://git-master/r/18330
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Ib7e1160bb0157f7c18d952b526239e4f50cc5180
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Using pll_p clk source for all sdmmc instances.
Disabling clocks left over by the bootloader.
Original-Change-Id: I245347b016618c39a4ceb2323f659b09261eaf7d
Reviewed-on: http://git-master/r/17847
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I0790f6f67c944a9ca42be9d6b9398d8093b4beef
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Enabling DDR mode support for eMMC v4.4 cards by
adding the support in the capabilities.
Original-Change-Id: I1a546185ca778bd2316422811c61c902c2322511
Reviewed-on: http://git-master/r/17957
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I29c829172abb312dc81e8e55a63c713189e2debf
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Enabling required power rails for sdmmc1 device.
Original-Change-Id: I72b451961adf5a235bfc3abbeb4d4429f26aab76
Reviewed-on: http://git-master/r/17572
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I3e3ec7da0e8a2eecd27853c1a0bf140cc9376b0c
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Enabling LVL2 CLK OVR bit for sdmmc1.
Disabling cd and wp gpios for sdmmc1.
Enabling vddio_sdmmc1 using regulator and
setting the voltage to 3.3V.
Using clk_m for sdmmc1.
Original-Change-Id: Id38e2357c5cafe103b7607ef5adb4e7e9bc228d4
Reviewed-on: http://git-master/r/17212
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I89e4ab5b4cc501cf02eb800bc3acb49b0dba2519
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Enabling the SDMMC3_CLK_OVR_ON bit to make the
sdmmc3 internal clock stable.
Original-Change-Id: I76c8e966bf333c3638ddf029117734414578efcd
Reviewed-on: http://git-master/r/17184
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Idb6e083cdaa99e72566925e72ee1f0c8985d2308
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Do not switch off sdmmc4 clock. Also, removed ddr
mode temporarily from linux mmc driver.
Programming tap_delays and internal clock.
Original-Change-Id: I830bf5e94ccd47e154c5ef9909e8bff1ff7754c0
Reviewed-on: http://git-master/r/17070
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Ic1cff8dd85229fe903206f1dc9a967d600ba88c1
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Adding support for sd3.0 cards. Added
support for SDR50, SDR104 and DDR50 modes.
Bug 661035
Original-Change-Id: Iecd6634b8e25d5fcbc05f79f34aea40a8460b527
Reviewed-on: http://git-master/r/15003
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Ic2119387d55b2e4263f50a606e0f957ab518f0cb
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Configuring the vendor clk control and vendor
misc control bits for adding SD 3.0 support and
for sw reset.
Bug 741503
Bug 767242
Original-Change-Id: I8a0d6958bbd29af710d045f9f8f639b6e7df8c55
Reviewed-on: http://git-master/r/14594
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I6b048425124eed7edf61370917d0da4b08b3b123
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Adding ddr mode support for eMMC v4.4 cards.
If the card and host controller support ddr mode,
configuring it. Setting clock divisor as 1 in case
ddr mode is configured.
Original-Change-Id: I94c7f2c4d23e856a67ccf312672e5f1eaee04a91
Reviewed-on: http://git-master/r/13798
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I79cd2f6a5ca1e8e00e4bceed5fdf61b4543aa1e4
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Bug 764354
Original-Change-Id: I807433ff825bed1fe91ce0cf50a2b3691c64ef0a
Reviewed-on: http://git-master/r/12227
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I3da91a438f98f2f51618446ce024f3fefd726a19
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This reverts commit a616ec3ef588ab50b4f296b5b022b1bb5934aa31.
Change-Id: Idadd2c62d4dc99518d87b424bd164a97d342cab3
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Conflicts:
arch/arm/mm/proc-v7.S
drivers/video/tegra/dc/dc.c
Change-Id: I40be0d615f14f1c01305388a706d257f624ba968
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CMD38 argument is passed through EXT_CSD[113].
Change-Id: I47e9d5e2cf44d9274a65a3b1955026185cb8f2b8
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
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Needed for Sandisk workaround (manipulate EXT_CSD).
Change-Id: I7bfe50a1503ac73ae072db718b60c27526521e41
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
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Block quirks implemented using core/quirks.c support.
Change-Id: I81d9ad57a7ae95c60ee8026f090c8df7c75fd069
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
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The current mechanism is SDIO-only. This allows us to create
function-specific quirks, without creating messy Kconfig dependencies,
or polluting core/ with function-specific code.
Change-Id: If31a151c20a8a1fddb0774674821e9fdc4aa61a0
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
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Some cards have quirks valid for every platforms using current
platform quirk hooks leads to a lot of code and debug duplication.
So we inspire a bit from what exists in PCI subsystem and do our own
per vendorid/deviceid quirk. We still drop the complexity of the pci
quirk system (with special section tables, and so on).
That can be added later if needed.
Change-Id: Ib67a3e97486023267f5ea3e7c6ef8fc99b13a704
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Write protection was disabled in K36. Enabling this feature by
storing the write protection GPIO pin number (wp_gpio) from
platform_data for the device and reading this GPIO (whenever the
card is inserted) to determine whether the card is write protected
or not.
Bug 686892.
Change-Id: I6f1855b7b974caaa5ea58aaee3881d85d5da6c18
Reviewed-in: http://git-master/r/#change,21101
Reviewed-on: http://git-master/r/23971
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Implement functions needed in struct mmc_host_ops to support
enable/disable SDCLK dynamically.
Add SDHCI_QUIRK_RUNTIME_DISABLE to switch on/off this feature.
Bug 800655
Change-Id: I4c71ca4beb56df020381236ca8ec949647a0d333
Reviewed-on: http://git-master/r/23125
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug 783535
original-work by Pavan Kunapuli <pkunapuli@nvidia.com>
Change-Id: I91df865cd8235b5ffc7e49c675bcf417333c5776
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/23308
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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If remove/insert sdcard continuously, kernel panic happened
due to lock up at sdhci_card_detect_callback(). The problem
was that sdhci_card_detect_callback() being called from
interrupt context. This code uses interfaces that cannot be
called while the kernel is atomic (no scheduling). With
using tasklet rather than directly call, detection call will
be scheduled. So tasklet will make sure of serialization for
card detection interrupt calls.
Bug 783446
Reviewed-on: http://git-master/r/16884
(cherry picked from commit a991cb2311799116f17504e137d0672650643ea6)
Change-Id: I4249e9e7becd9b5c0a4594b5cca6e5b5dc2184a4
Reviewed-on: http://git-master/r/21741
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
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Change-Id: Id030cc94db62c9dcaa79a2ddd7c034ac9f9adc61
Reviewed-on: http://git-master/r/21803
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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This reverts commit 5f2e1258ff35f700f5ca9df3047dc5fe19b99017.
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devices""
This reverts commit 6b53bad8ac54b3d748c4b0dbe6b0a4ed6e2e60f4.
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Conflicts:
drivers/usb/host/ehci-tegra.c
include/linux/usb.h
include/linux/usb/hcd.h
Change-Id: I2499459b717e36a2a994af9d7a5ae1ecb5e7ca9c
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