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Bug 200042283
Change-Id: I3c1783e362f9a0e95abb4955640e4cdd70d1f59e
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/668855
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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12MHz frequency for emc is not sufficient in case of high data
transfer using PCIE, hence need to increase emc frequency for
gen1 and gen2 pcie devices to 102MHz and 508MHz respectively.
Bug 1566598
Change-Id: I82c5592dc232ba32eaf6ed959ff78a9966dc6ff1
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/663267
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Based on the capability of card, we should dynamically
set the mselect, pciex clock and link speed selection.
Clocks will be set to support the highest capable card
This patch:
1. enable the clocks to minimal value during boot
2. Based on card capability, it boosts the clocks
3. And train the link
Bug 1483608
Change-Id: Iaf90f9b06846f8e23e4f60d1670a1db9ec562257
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/437560
(cherry picked from commit ada2f21676de75332ad906fa2386a74f9d58f94a)
Reviewed-on: http://git-master/r/448072
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Update prod settings for Gen2 High Swing TX
Amplitude
Bug 1476459
Reviewed-on: http://git-master/r/422694
(cherry picked from commit 82af7145023762ee27ebc0cede3c9163ea1e6ef1)
Change-Id: Id967133f6e22ccad7ba7f46c56c57a4984e53686
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/424189
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 200004122
Conflicts:
drivers/cpufreq/cpufreq.c
drivers/regulator/core.c
sound/soc/codecs/max98090.c
Change-Id: I9418a05ad5c56b2e902249218bac2fa594d99f56
Signed-off-by: Ishan Mittal <imittal@nvidia.com>
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Page protection flag updated after PTE_PROT_NONE
is moved up.
Bug 1513681
Change-Id: If0b27d7b0b211ba6488a28fde5fa2d79b477c4be
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/414128
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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The time from +1.05V_RUN to PEX_L1_RST_L signal
(PEX_L1_RST_N on T124) should be 100ms minimum
Bug 1500840
Change-Id: I170ed3225f80b5ef0ccaf4b38565d3adf94a674a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/402841
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Disable for Tegra12 L0s feature as its broken.
Bug 1483608
Change-Id: I84cc97d7a3e3f6527366a2edb3238d103ca5d167
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/391647
(cherry picked from commit 80f4ce0958393616d98f759f7fa190f761c6a711)
Reviewed-on: http://git-master/r/402824
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Enable both the lanes for the x2, x1 configuration
based on port status
Bug 1468239
Change-Id: I8e4b59940bc148d883c129cecc614a0173874219
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/374341
(cherry picked from commit 65d65f9eb2c9320b27da0fb4e425785bb6f966f7)
Reviewed-on: http://git-master/r/402823
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Change-Id: I30baee4084399b8078232f31296c4d891a903d47
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/395123
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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1. Add a bool to determine what all resources to
be cleaned up at a particular exit point
2. Add calls to this api from required exit points
for better cleanup
Bug 1489959
Change-Id: I2cae4a41ec9978f0bd52d28fd2288ca090d2d57c
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/391381
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit 1d5c438690a6000f11bf4610e4029dcdd6e5b8ba.
This change is causing failures on l4t nvlptest.
Change-Id: Iec560e71c60f1243823807d73d82bc89cb35f9a8
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/391491
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Call power off api from required exit points in
probe for better cleanup
Bug 1489959
Change-Id: I908bce099f00e441fe1ed13a08f34fb38575adf1
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/390508
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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1. Fixed interrupt code mask to use 5 bits
2. Added more interrupt messages
Change-Id: I61e9ea1c49919b142e6e409da952e41c47a77d4b
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/387728
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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commit 3cdeb713dc66057b50682048c151eae07b186c42 upstream.
Andreas reported that after 1f42db786b14 ("PCI: Enable INTx if BIOS left
them disabled"), pciehp surprise removal stopped working.
This happens because pci_reenable_device() on the hotplug bridge (used in
the pciehp_configure_device() path) clears the Interrupt Disable bit, which
apparently breaks the bridge's MSI hotplug event reporting.
Previously we cleared the Interrupt Disable bit in do_pci_enable_device(),
which is used by both pci_enable_device() and pci_reenable_device(). But
we use pci_reenable_device() after the driver may have enabled MSI or
MSI-X, and we *set* Interrupt Disable as part of enabling MSI/MSI-X.
This patch clears Interrupt Disable only when MSI/MSI-X has not been
enabled.
Fixes: 1f42db786b14 PCI: Enable INTx if BIOS left them disabled
Link: https://bugzilla.kernel.org/show_bug.cgi?id=71691
Reported-and-tested-by: Andreas Noever <andreas.noever@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Enable ASPM in host driver only when pci_aspm=off
is not set.
Bug 1459770
Change-Id: I1fc6bab71df0297e1c6775837f023aed3396eb8b
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/381953
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Vijayarahavan Rajendran <vrajendran@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 1476459
Change-Id: I1371654355f27e1bc1b26b81dd4307f389092bf5
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/380375
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Resolve below warnings:
1. statement with no effect
2. ISO C90 forbids mixed declarations and code
3. cast to pointer from integer of different size
Bug 1466403
Change-Id: I3f3a14bf80e25c411adb222500f8f40cc848282d
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/379859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 1456092
Change-Id: I3021247ec68a3c2dddd9e98cde13d70a45191d53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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commit 1f42db786b14a31bf807fc41ee5583a00c08fcb1 upstream.
Some firmware leaves the Interrupt Disable bit set even if the device uses
INTx interrupts. Clear Interrupt Disable so we get those interrupts.
Based on the report mentioned below, if the user selects the "EHCI only"
option in the Intel Baytrail BIOS, the EHCI device is handed off to the OS
with the PCI_COMMAND_INTX_DISABLE bit set.
Link: http://lkml.kernel.org/r/20140114181721.GC12126@xanatos
Link: https://bugzilla.kernel.org/show_bug.cgi?id=70601
Reported-by: Chris Cheng <chris.cheng@atrustcorp.com>
Reported-and-tested-by: Jamie Chen <jamie.chen@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Bug 1415344
Change-Id: I83b4776dda302a38969dcf8337c883309db622c7
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/377634
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 1369825
Change-Id: I0e37ee8d1090741c6b08694d20cb4d427da26988
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/366554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Use devm_* gpio APIs to ensure better cleanup
Also suppress debug prints in MSI isr by 10 times
Bug 1429394
Change-Id: I32663a6443e32bcdf56c1e314250fdb639b17e7c
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/367706
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Bug 1450513
Change-Id: I99b11dfc04d7398a5e6efa3fcf22919ee96a2964
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/362387
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
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Initialize IRQ_LINE to non-zero before enumeration
to avoid warning for invalid IRQ.
Bug 1453145
Change-Id: Ifbed98cb15f4f57a77bdc59dff225ae7fbaa3684
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/365334
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Bug 1345350
Change-Id: I3f4c1bd232df2ad121144dcec84232a468e603be
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/360732
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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1. Avoid removing controller shutdown in detach
and init sequence in attach.
2. Instead, remove all data structures in detach
and recreate them in attach.
3. Also hide AER capability in detach to avoid AER
spews in log and unhide it attach.
Bug 1446334
Change-Id: Ic76f227e24d249d2374b700980697850a1e5303f
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/351039
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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request for wake gpio before using it for
wake irq purpose
Bug 1429394
Change-Id: Ifecc930e1ef82da930670ffbda46a9660543294b
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/358812
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Change-Id: Ic2f95cd148fde9e0c392403d4d7bd55182b4fc75
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/271887
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
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Change-Id: I563e6a59bf37d137114cd84161081f89f669de53
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/259835
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
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Change-Id: I12f75dae7accc503e3cc4eb11ccc75117fd90943
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/259828
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
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gpio_hot_plug might be invalid (-1) in some cases when we pass it to
gpio_free(). hence add a check on gpio_hot_plug before freeing it.
Coverity id : 25448
Bug 1416640
Change-Id: If23a16e260466da86c11009ff5a660d59d548f5c
Signed-off-by: Salona Sinha <salonas@nvidia.com>
Reviewed-on: http://git-master/r/357694
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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1. Add api to provide required info to test suite
2. Remove expose of tegra_pcie struct
3. Remove unnecessary macros to use standard ones
Bug 1347997
Change-Id: Ifd5f4ac38bc3235e07b37c74dd0c9420c6d7dfae
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/356534
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
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Initialize core MSI data once and re-enable MSI
registers on resume, if MSI were enabled.
Bug 1363735
Change-Id: I3d3d7e21be121e38d5159302ec47aaff9dcf7525
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/354470
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MSI for port driver results in panic, so disabled
Bug 1421847
Change-Id: I5e9e10ad80cbf86d763be11b3f473ae7cea9f772
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/351374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 1319925
Bug 1400987
Change-Id: I0d47581bd0c0835e52a90efe142076bdd476a2c1
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/352206
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 1421847
Change-Id: Idd5d767c4e2f8539fb7ccc92839b951b8123095b
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/350991
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Get PCIE mselect clock and set it to 408MHz for
maximum bandwidth if PCIE is used.
Bug 1430734
Change-Id: If9c7395b4094704eff039df0066a666a8170a4f5
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/349445
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 1333935
Change-Id: I39137ed64e75745c330f064a2e373b4e7f27c98c
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/350582
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Removing unnecessary dock detect variable which
was appropriate for T30 using PM293 dock. T124
does not use any such dock
Bug 1406265
Change-Id: I29078472b269f73a8b4a60ea98c5c3a7d8c907ed
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/349765
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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T124 does not need this WAR as required registers
are already initialized properly for it.
Bug 1412769
Change-Id: I949cc79b6c37d5ed227eead3c7f72de094eaaad2
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/350108
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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1. Move pads programming before AFI/RP programming
2. Move deassert PEX reset at end of AFI program
3. Removed unnecessary xclk & plle clock enable
4. Disable PADS by putting them in IDDQ while LP0
Bug 1415344
Change-Id: I9c6857366c4f0872aba3fb530ff60bfa81dd3832
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/345875
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Removed unused members from host structures
Bug 1415344
Change-Id: I5c8fd3f2dedef69aba2bcfbe4b04b538c95f6a9c
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/348016
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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commit 4fc9bbf98fd66f879e628d8537ba7c240be2b58e upstream.
Add a flag to tell the PCI subsystem that kernel is shutting down in
preparation to kexec a kernel. Add code in PCI subsystem to use this flag
to clear Bus Master bit on PCI devices only in case of kexec reboot.
This fixes a power-off problem on Acer Aspire V5-573G and likely other
machines and avoids any other issues caused by clearing Bus Master bit on
PCI devices in normal shutdown path. The problem was introduced by
b566a22c2332 ("PCI: disable Bus Master on PCI device shutdown").
This patch is based on discussion at
http://marc.info/?l=linux-pci&m=138425645204355&w=2
Link: https://bugzilla.kernel.org/show_bug.cgi?id=63861
Reported-by: Chang Liu <cl91tp@gmail.com>
Signed-off-by: Khalid Aziz <khalid.aziz@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Konstantin Khlebnikov <koct9i@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This is the 3.10.24 stable release
Change-Id: Ibd2734f93d44385ab86867272a1359158635133b
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Enable AER Support for Rootports by programming
its private registers
Bug 1259524
Change-Id: Ia9d2e5dbcdac1d3e8af114d152be5059518e6eb1
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/339209
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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The pcie_ports parameter, which defaults to 'auto', allows a user
to specify if PCIe port services are disabled ('compat'), always
enabled ('native'), or only used when allowed by the BIOS
('auto').
Where CONFIG_ACPI isn't enabled, as is often the case for non
x86/ia64 platforms, the 'auto' behavior results in that of
'compat'. Thus in order to use port services on these platforms
'pcie_ports=native' must be added to the kernel command line.
This patch results in the 'native' behavior being followed where
'auto' is selected and ACPI is not enabled.
Bug 1259524
Change-Id: I3838d8d50c765d3866a63369a96608db0c36f038
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 6b87e700cd65120b70aaa097a8f4e7f22f1945ee)
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/338219
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Enable PE_WAKE signal as wake source to invoke LP0
resume when any pcie device is connected
Bug 1320407
Change-Id: Ia9ddcfdb1a57d747bf391f5b1a354ac68857d96f
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/338227
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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commit e7cc5cf74544d97d7b69e2701595037474db1f96 upstream.
The pcie_portdrv .probe() method calls pci_enable_device() once, in
pcie_port_device_register(), but the .remove() method calls
pci_disable_device() twice, in pcie_port_device_remove() and in
pcie_portdrv_remove().
That causes a "disabling already-disabled device" warning when removing a
PCIe port device. This happens all the time when removing Thunderbolt
devices, but is also easy to reproduce with, e.g.,
"echo 0000:00:1c.3 > /sys/bus/pci/drivers/pcieport/unbind"
This patch removes the disable from pcie_portdrv_remove().
[bhelgaas: changelog, tag for stable]
Reported-by: David Bulkow <David.Bulkow@stratus.com>
Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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commit 6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e upstream.
Previously we allowed callers to access Slot Capabilities, Status, and
Control for Root Ports even if the Root Port did not implement a slot.
This seems dubious because the spec only requires these registers if a
slot is implemented.
It's true that even Root Ports without slots must have *space* for these
slot registers, because the Root Capabilities, Status, and Control
registers are after the slot registers in the capability. However,
for a v1 PCIe Capability, the *semantics* of the slot registers are
undefined unless a slot is implemented.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
Acked-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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