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requirement
As the below diagram shows, to achieve a particular serial clock rate,
we should choose an appropriate CO divider value(1/2/4/8) so that PLL
VCO frequency(fvco) is in specified range(640MHz ~ 1500MHz).
--------- 640MHz ~ 1500MHz ------------ --------------
| PLL VCO | ----------------> | CO divider | -> | serial clock |
--------- ------------ --------------
1/2/4/8 div 7 * phy_clk_rate
This patch configures CO divider to be appropriate value to meet the fvco
range requirement. This may address display flicker issue seen on some
SoC samples.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 720ed81158607cefecec7a3f7c53680aff251139)
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Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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It seems that we haven't got SCU ISO bit available to check if PHY is
locked or not after enable, so let's simply delay for a while as a
temporary solution.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds Mixel LVDS combo PHY support(MIPI DSI and LVDS combo).
This LVDS PHY supports one LVDS channel in single mode and two channels in
dual mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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