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path: root/drivers/pinctrl/spear
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2012-11-05pinctrl: SPEAr1340: Add clcd sleep mode pin configurationVipul Kumar Samar
CLCD pads must be configured differently for sleep mode. This patch adds support for clcd_sleep_pingroup. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr1340: Make DDR reset & clock pads as gpioDeepak Sikri
Some gpio pins are used to control DDR reset and clock enable while the system is moved into Low power. This patch adds in the corresponding GPIO entries in the pads_as_gpio_pins to ensure the pads are available as gpio's. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr1310: add register entries for enabling pad directionShiraz Hashim
Pad direction must also be updated for SPEAr1310, while setting pads values. This patch adds support for that. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr1310: Separate out pci pins from pcie_sata pin groupVipul Kumar Samar
SPEAr1310 has separate PCI and PCIe implementations which are not muxed with each other. Presently they have been implemented as muxed together with SATA and are represented wrongly in the software. In reality only PCIe and SATA implementations are muxed with each other. This patch separates out pci pins creating a new pingroup and function for pci. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr1310: Fix value of PERIP_CFG reigster and MCIF_SEL_SHIFTVipul Kumar Samar
This patch fixes two macros: PERIP_CFG registers offset and MCIF selection shift. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr1310: fix clcd high resolution pin group nameShiraz Hashim
All group names in SPEAr pinctrl have "_grp" at the end of their name. Do the same for clcd_high_res_grp. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr320: Correct pad mux entries for rmii/smiiDeepak Sikri
pin entries of rmii and smii are interchanged by mistake. Fix it. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr3xx: correct register space to configure pwmShiraz Hashim
To have pwm on pad no. 34 we also need to select between pwm and SD_LED functions. Add this to pwm pin mux register configuration. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05pinctrl: SPEAr: Don't update all non muxreg bits on pinctrl_disableViresh Kumar
Not all bits of a register are used for pinctrl in SPEAr. So only update bits relevant to pinctrl using muxreg->mask. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-07-03pinctrl/pinctrl-spear: remove IS_ERR checking of pmx->pctlDevendra Naga
pinctrl_register returns a pointer of struct type struct pinctrl_dev, if successfully registered to pinctrl subsystem, otherwise returns NULL, and there wont' be any pointers which are not dereferencible. They are not type of pointer addresses but are kind of error codes rather actual addresses, but are a kind of return codes of functions returning integer types. return -ENODEV if device registration fails. Signed-off-by: Devendra Naga <devendra.aaru@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-06-20Viresh has movedViresh Kumar
viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-05-14pinctrl: SPEAr1310: Fix pin numbers for clcd_high_resViresh Kumar
Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-14pinctrl: Add SPEAr13xx pinctrl driversViresh Kumar
This adds pinctrl driver for SPEAr13xx family. SPEAr13xx family supports two machines: SPEAr1310 and SPEAr1340. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-14pinctrl: SPEAr: Create macro for declaring GPIO PINSViresh Kumar
Same GPIO pins declarations would be required for other SoCs and that will be a lot of lines of code. Its better to create common macros for it. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-22pinctrl: Add SPEAr3xx pinctrl driversViresh Kumar
This adds pinctrl driver for SPEAr3xx family. SPEAr3xx family supports three families: SPEAr300, SPEAr310 and SPEAr320. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
2012-04-22pinctrl: Add SPEAr pinctrl driversViresh Kumar
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file for SPEAr pinctrl drivers. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>