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path: root/drivers/pinctrl
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2026-05-11pinctrl: renesas: rzg2l: Update OEN pin validation to use exact matchBiju Das
The RZ/G2L SoC uses pin 0 from a port for OEN while RZ/G3L uses pin 1. The existing greater-than comparison against oen_max_pin in rzg2l_pin_to_oen_bit() would incorrectly accept any pin below that value rather than enforcing the single valid OEN pin for each SoC. Replace the range check with an exact equality test so that only the designated OEN pin is accepted. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Add support for selecting power source for ↵Biju Das
{WDT,AWO,ISO} The RZ/G3L SoC has support for setting power source that are not controlled by the following voltage control registers: - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC Add support for selecting voltages using OTHER_POC register for setting I/O domain voltage for WDT, ISO and AWO by extending rzg2l_caps_to_pwr_reg() with a mask output parameter so that callers callers can identify which bit(s) within OTHER_POC correspond to the requested domain. Update rzg2l_get_power_source() to extract the relevant bit field via field_get() when reading OTHER_POC, and update rzg2l_set_power_source() to perform a read-modify-write under the spinlock when writing to OTHER_POC, since multiple domains share the same register. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Make QSPI register handling conditionalBiju Das
The QSPI register at offset 0x3008 is not present on all SoCs supported by the RZ/G2L pinctrl driver. Unconditionally reading and writing this register during suspend/resume on hardware that lacks it can cause undefined behaviour. Add a qspi field to rzg2l_register_offsets to allow per-SoC declaration of the QSPI register offset, and guard the suspend/resume accesses with a check on that field. Populate the offset only for the RZ/{G2L,G2LC,G2UL, Five} hardware configuration, which is where the register is known to exist. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-07pinctrl: qcom: nord: remove duplicated pin functionBartosz Golaszewski
The qdss_cti function is initialized twice in the nord_functions array. Remove the duplicate entry. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202605061633.BJLI5voT-lkp@intel.com/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Make important drivers default (1)Krzysztof Kozlowski
The main SoC TLMM (Top-Level Multiplexer) pin controller drivers are essential for booting up SoCs and are not really optional for a given platform. Kernel should not ask users choice of drivers when that choice is obvious and known to the developers that answer should be 'yes' or 'module'. Switch all Qualcomm TLMM pin controller drivers to a default 'yes' for ARCH_QCOM. This has impact: 1. arm64 defconfig: enable PINCTRL_SM7150, PINCTRL_IPQ9650 and PINCTRL_HAWI, which were not selected before but should be, because these platforms need them for proper boot. 2. arm qcom_defconfig: no changes. 3. arm multi_v7 defconfig: enable drivers necessary to boot ARM 32-bit platforms, which are already enabled on qcom_defconfig. 4. COMPILE_TEST builds: enable by default all drivers for arm or arm64 builds, whenever ARCH_QCOM is selected. This has impact on build time and feels logical, because if one selects ARCH_QCOM then probably by default wants to build test it entirely. Kernels with COMPILE_TEST are not supposed to be used for booting. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> [linusw@kernel.org: Split off the defconfig changes to a separate patch] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: rockchip: Move MODULE_DEVICE_TABLE next to the table itselfKrzysztof Kozlowski
By convention MODULE_DEVICE_TABLE() immediately follows the ID table it exports, because this is easier to read and verify. It also makes more sense since #ifdef for ACPI or OF could hide both of them. Most of the pin controller drivers already have this correctly placed, so adjust the other drivers. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: bcm: Move MODULE_DEVICE_TABLE next to the table itselfKrzysztof Kozlowski
By convention MODULE_DEVICE_TABLE() immediately follows the ID table it exports, because this is easier to read and verify. It also makes more sense since #ifdef for ACPI or OF could hide both of them. Most of the pin controller drivers already have this correctly placed, so adjust the other drivers. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Move MODULE_DEVICE_TABLE next to the table itselfKrzysztof Kozlowski
By convention MODULE_DEVICE_TABLE() immediately follows the ID table it exports, because this is easier to read and verify. It also makes more sense since #ifdef for ACPI or OF could hide both of them. Some Qualcomm pin controller drivers already have this correctly placed, so adjust the other drivers. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: sophgo: allocate power_cfg with privRosen Penev
Use a flexible array member to combine allocations and simplify code slightly. Signed-off-by: Rosen Penev <rosenp@gmail.com> [linusw@kernel.org: add a counter and __counted_by() annotation] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: single: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: mediatek: moore: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: ingenic: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. While Ingenic is a 32-bit platform, it is still better to use the correct type, to serve as an example. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: equilibrium: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: airoha: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Add SM6350 LPASS LPI TLMMLuca Weiss
Add support for the pin controller block on SM6350 Low Power Island. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> [linusw@kernel.org: fixed up Kconfig entry] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew controlLuca Weiss
On some platforms like SM6350 (Bitra), some pins have their slew controlled with the SPARE_1 register. Add support for that. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-06pinctrl: qcom: Remove unused macro definitionsMaulik Shah
Remove SDC_QDSD_PINGROUP, QUP_I3C and UFS_RESET macros as on some platforms they are unused. No functional impact. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: add generic board-level pinctrl driver using mux frameworkFrank Li
Many boards use on-board mux chips (often controlled by GPIOs from an I2C expander) to switch shared signals between peripherals. Add a generic pinctrl driver built on top of the mux framework to centralize mux handling and avoid probe ordering issues. Keep board-level routing out of individual drivers and supports boot-time only mux selection. Ensure correct probe ordering, especially when the GPIO expander is probed later. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: add optional .release_mux() callbackFrank Li
Add an optional .release_mux() callback to struct pinmux_ops. Some drivers acquire additional resources in .set_mux(), such as software locks. These resources may need to be released when the mux function is no longer active. Introducing a dedicated .release_mux() callback allows drivers to clean up such resources. The callback is optional and does not affect existing drivers. Commit 2243a87d90b42 ("pinctrl: avoid duplicated calling enable_pinmux_setting for a pin") removed the .disable() callback to resolve two issues: 1. desc->mux_usecount increasing monotonically 2. Hardware glitches caused by repeated .disable()/.enable() calls Adding .release_mux() does not reintroduce those problems. The callback is intended only for releasing driver-side resources (e.g. locks) and must not modify hardware registers. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: extract pinctrl_generic_to_map() from ↵Frank Li
pinctrl_generic_pins_function_dt_node_to_map() Refactor pinctrl_generic_pins_function_dt_subnode_to_map() by separating DT parsing logic from map creation. Introduce a new helper pinctrl_generic_to_map() to handle mapping to kernel data structures, while keeping DT property parsing in the subnode function. Improve code structure and enables easier reuse for platforms using different DT properties (e.g. pinmux) without modifying the dt_node_to_map-style callback API. Avoid unnecessary coupling to pinctrl_generic_pins_function_dt_node_to_map(), which provides functionality not needed when the phandle target is unambiguous. Maximize code reuse and provide a cleaner extension point for future pinctrl drivers. Suggested-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05Merge tag 'renesas-pinctrl-fixes-for-v7.1-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into fixes pinctrl: renesas: Fixes for v7.1 - Fix pin bias suspend/resume handling on the RZ/G2L family, - Fix Schmitt-trigger suspend/resume handling on RZ/V2H(P), RZ/V2N, and RZ/G3E. Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: qcom: add the TLMM driver for the Nord platformsBartosz Golaszewski
Add support for the TLMM controller on the Qualcomm Nord platform. Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: qcom: Fix wakeirq map by removing disconnected irqs for sm8150Maulik Shah
PDC interrupts 122-125 were meant for ibi_i3c wakeup but sm8150 do not support i3c. GPIOs 39,51,88 and 144 are also connected to different PDC pin and already reflected in the wake irq map. Remove the unsupported wakeup interrupts from the map. Fixes: 90337380c809 ("pinctrl: qcom: sm8150: Specify PDC map") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-05pinctrl: sunxi: fix regulator leak in sunxi_pmx_request() error pathFelix Gu
In the error path of sunxi_pmx_request(), the code calls regulator_put(s_reg->regulator) to release the regulator. However, s_reg->regulator is only assigned after a successful regulator_enable(). This causes a memory leak: the regulator obtained via regulator_get() is never properly released when regulator_enable() fails. Fixes: dc1445584177 ("pinctrl: sunxi: Fix and simplify pin bank regulator handling") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-30pinctrl: mediatek: eint: Drop base from mtk_eint_chip_write_mask()Chen-Yu Tsai
When support for multiple EINT base addresses was added in commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses"), mtk_eint_chip_write_mask() was changed to write interrupt masks for all base addresses in one call. However the "base" parameter was left around and now causes sparse warnings: mtk-eint.c:428:44: warning: incorrect type in argument 2 (different address spaces) mtk-eint.c:428:44: expected void [noderef] __iomem *base mtk-eint.c:428:44: got void [noderef] __iomem **base mtk-eint.c:436:44: warning: incorrect type in argument 2 (different address spaces) mtk-eint.c:436:44: expected void [noderef] __iomem *base mtk-eint.c:436:44: got void [noderef] __iomem **base Since the "base" parameter is no longer needed, just drop it. Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses") Cc: Hao Chang <ot_chhao.chang@mediatek.com> Cc: Qingliang Li <qingliang.li@mediatek.com> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: starfive: jh7110: use struct_sizeRosen Penev
Instead of an extra kcalloc, Use a flexible array member to combine allocations. Saves a pointer in the struct. Signed-off-by: Rosen Penev <rosenp@gmail.com> Acked-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: Fix GPIO to PDC wake irq map for qcs615Maulik Shah
PDC interrupts 122-125 were meant for ibi_i3c wakeup but qcs615 do not support i3c. GPIOs 39,51,88 and 89 are also connected to different PDC pin to support non-ibi wakeup. Update the wakeirq map to reflect same. Fixes: b698f36a9d40 ("pinctrl: qcom: add the tlmm driver for QCS615 platform") Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: meson: amlogic-a4: fix deadlock issueXianwei Zhao
Accessing the pinconf-pins sysfs node may deadlock. pinconf_pins_show() holds pctldev->mutex, and the platform driver calls pinctrl_find_gpio_range_from_pin(), which tries to acquire the same mutex again, leading to a deadlock. Use pinctrl_find_gpio_range_from_pin_nolock() to fix this issue. Fixes: 6e9be3abb78c ("pinctrl: Add driver support for Amlogic SoCs") Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: Unify user-visible "Qualcomm" nameKrzysztof Kozlowski
Various names for Qualcomm as a company are used in user-visible config options: QCOM, Qualcomm and Qualcomm Technologies. Switch to unified "Qualcomm" so it will be easier for users to identify the options when for example running menuconfig. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> [linusw@kernel.org: Also fix the new IPQ9650] Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: pinconf-generic: fix properties bitmap leak in parse_fw_cfg()Felix Gu
In parse_fw_cfg(), if fwnode_property_match_property_string() fails with -ENOENT, the code returns directly and leaks the bitmap. Use __free(bitmap) for automatic cleanup to fix the leak. Fixes: 9c105255108b ("pinctrl: pinconf-generic: perform basic checks on pincfg properties") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: eliza: Split QUP1_SE4 lanesAlexander Koskovich
QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the function name cannot be the same or the alternate function cannot be selected. Split them up into individual lane functions so boards can specify. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: eliza: Split QUP lane mirror alternatesAlexander Koskovich
Several QUP lanes have MIRA/MIRB mirror routings which are collapsed under a single function name (e.g. qup1_se6). This is an issue because it means there are multiple functions defined for a given pin that share the same name: [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6... So when you select pin 42 and request function qup1_se6, it will select the first instance of it in this group, which just happens to be QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively unreachable. Split each of these lanes that has an alternative GPIO into their own function so they can actually be selected, following the pattern seen in pinctrl-sm8550.c. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: eliza: Fix QDSS trace clock/control pingroup namesAlexander Koskovich
Fix a few typos for these in their respective pingroups, the groups already exist they just weren't referenced. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: pinconf-generic: Use kmemdup_array() over kmemdup()Yash Suthar
using kmemdup_array instead of kmemdup ,as it is more readable and matches the intent of the api. tested with w=1, no new warnings introduced. Signed-off-by: Yash Suthar <yashsuthar983@gmail.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: qcom: Introduce IPQ9650 TLMM driverKathiravan Thirumoorthy
Qualcomm's IPQ9650 comes with a TLMM block, like all other platforms, so add a driver for it. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: vt8500: Enable compile testingKrzysztof Kozlowski
Enable compile testing for Realtek pin controller drivers for increased build and static checkers coverage. PINCTRL_WMT uses gpiochip_get_data(), thus needs GPIOLIB. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: aspeed: Enable compile testing outside of ARCH_ASPEEDKrzysztof Kozlowski
Since inception in commit 4d3d0e4272d8 ("pinctrl: Add core support for Aspeed SoCs"), the Aspeed pin controller drivers cannot be compile tested, unless ARCH_ASPEED is selected. . That partially defeats the purpose of compile testing, since ARCH_ASPEED is pulled when building platform kernels. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: realtek: Enable compile testingKrzysztof Kozlowski
Enable compile testing for Realtek pin controller drivers for increased build and static checkers coverage. PINCTRL_RTD uses pinconf_generic_dt_node_to_map(), thus needs OF. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-28pinctrl: tegra: Enable easier compile testingKrzysztof Kozlowski
Currently NVIDIA Tegra pin controller drivers cannot be compile tested, unless ARCH_TEGRA is selected. That partially defeats the purpose of compile testing, since ARCH_TEGRA is pulled when building platform kernels. Solve it and allow compile testing independently of ARCH_TEGRA choice which requires few less usual changes: 1. Descent in Makefile in to drivers/pinctrl/tegra/ unconditionally, because there is no menu option. 2. Depend on COMMON_CLK for PINCTRL_TEGRA20, because it uses clk_register_mux(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-27pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PMLad Prabhakar
On RZ/V2H(P), dedicated pins support pull-up/pull-down configuration via PIN_CFG_PUPD. Add PUPD handling for dedicated pins in the PM save/restore path. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resumeLad Prabhakar
Include the NOD (N-ch Open Drain) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cacheLad Prabhakar
Include PIN_CFG_IOLH_RZV2H in the IOLH capability checks when saving and restoring pin configuration registers. On RZ/V2H(P), RZ/V2N, and RZ/G3E, the IOLH configuration is defined by the PIN_CFG_IOLH_RZV2H capability. The previous implementation did not account for this, causing the IOLH registers to be skipped during PM save/restore. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resumeLad Prabhakar
Include the SR (Slew Rate) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Fix SMT register cache handlingLad Prabhakar
Store SMT register cache per bank instead of using a single array. On RZ/V2H(P), RZ/V2N, and RZ/G3E, the SMT register is split across two 32-bit registers: bits 0/8/16/24 control pins 0-3, while pins 4-7 are controlled by the corresponding bits in the next register. The previous implementation cached only a single SMT register, leading to incomplete save/restore of SMT state. Convert cache->smt to a per-bank array and allocate storage for both halves. Update suspend/resume handling to save and restore both SMT registers when present. Fixes: 837afa592c623 ("pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins ↵Biju Das
during suspend/resume When saving/restoring pull-up/down register state during suspend/resume, the second PUPD register access was incorrectly using the same base offset as the first, effectively reading/writing the same register twice instead of the adjacent one. Add the correct + 4 byte offset to the second RZG2L_PCTRL_REG_ACCESS32 call so that pupd[1][port] is properly saved and restored from the next 32-bit register in the PUPD register pair, covering pins 4–7 of ports with 4 or more pins. Fixes: b2bd65fbb617 ("pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260328090548.84124-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: qcom: ipq4019: mark gpio as a GPIO pin functionTil Kaiser
The qcom pinctrl core supports marking functions that represent GPIO mode via PINCTRL_GPIO_PINFUNCTION(), so that strict pinmuxing does not reject GPIO requests for pins that are muxed to the GPIO function. ipq4019 still describes its gpio function with QCA_PIN_FUNCTION(gpio), so it is not treated as a GPIO pin function. As a result, GPIO consumers can still conflict with pinctrl states that select the "gpio" function. Add a QCA_GPIO_PIN_FUNCTION() helper and use it for the ipq4019 gpio function, matching how the msm-based qcom drivers handle this. This allows ipq4019 to keep the GPIO-related pin configuration in DTS without tripping over strict pinmux ownership checks. Fixes: cc85cb96e2e4 ("pinctrl: qcom: make the pinmuxing strict") Signed-off-by: Til Kaiser <mail@tk154.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-27pinctrl: mediatek: moore: implement gpio_chip::get_direction()Bartosz Golaszewski
If the gpio_chip::get_direction() callback is not implemented by the GPIO controller driver, GPIOLIB emits a warning. Implement get_direction() for the GPIO part of pinctrl-moore. Fixes: 471e998c0e31 ("gpiolib: remove redundant callback check") Fixes: e623c4303ed1 ("gpiolib: sanitize the return value of gpio_chip::get_direction()") Reported-by: Frank Wunderlich <frank-w@public-files.de> Closes: https://lore.kernel.org/all/20260409132724.126258-1-linux@fw-web.de/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Tested-By: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-04-18Merge tag 'pinctrl-v7.1-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Perform basic checks on pin config properties so as not to allow directly contradictory settings such as setting a pin to more than one bias or drive mode - Handle input-threshold-voltage-microvolt property - Introduce pinctrl_gpio_get_config() handling in the core for SCMI GPIO using pin control New drivers: - GPIO-by-pin control driver (also appearing in the GPIO pull request) fulfilling a promise on a comment from Grant Likely many years ago: "can't GPIO just be a front-end for pin control?" it turns out it can, if and only if you design something new from scratch, such as SCMI - Broadcom BCM7038 as a pinctrl-single delegate - Mobileye EyeQ6Lplus OLB pin controller - Qualcomm Eliza and Hawi families TLMM pin controllers - Qualcomm SDM670 and Milos family LPASS LPI pin controllers - Qualcomm IPQ5210 pin controller - Realtek RTD1625 pin controller support - Rockchip RV1103B pin controller support - Texas Instruments AM62L as a pinctrl-single delegate Improvements: - Set config implementation for the Spacemit K1 pin controller" * tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (84 commits) pinctrl: qcom: Add Hawi pinctrl driver dt-bindings: pinctrl: qcom: Describe Hawi TLMM block dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema pinctrl: single: Add bcm7038-padconf compatible matching dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible pinctrl: qcom: sdm670-lpass-lpi: label variables as static pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description pinctrl: qcom: add sdm670 lpi tlmm dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property pinctrl: qcom: Introduce IPQ5210 TLMM driver dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs pinctrl: qcom: eliza: Fix interrupt target bit pinctrl: core: Don't use "proxy" headers pinctrl: amd: Support new ACPI ID AMDI0033 pinctrl: renesas: rzg2l: Drop superfluous blank line pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers ...
2026-04-17Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds
Pull MIPS updates from Thomas Bogendoerfer: - Support for Mobileye EyeQ6Lplus - Cleanups and fixes * tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS/mtd: Handle READY GPIO in generic NAND platform data MIPS/input: Move RB532 button to GPIO descriptors MIPS: validate DT bootargs before appending them MIPS: Alchemy: Remove unused forward declaration MAINTAINERS: Mobileye: Add EyeQ6Lplus files MIPS: config: add eyeq6lplus_defconfig MIPS: Add Mobileye EyeQ6Lplus evaluation board dts MIPS: Add Mobileye EyeQ6Lplus SoC dtsi clk: eyeq: Add Mobileye EyeQ6Lplus OLB clk: eyeq: Adjust PLL accuracy computation clk: eyeq: Skip post-divisor when computing PLL frequency pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB pinctrl: eyeq5: Use match data reset: eyeq: Add Mobileye EyeQ6Lplus OLB MIPS: Add Mobileye EyeQ6Lplus support dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC MIPS: dts: loongson64g-package: Switch to Loongson UART driver mips: pci-mt7620: rework initialization procedure mips: pci-mt7620: add more register init values ...
2026-04-16Merge tag 'soc-drivers-7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ...
generated by cgit v1.2.3 (git 2.0.4) at 2026-07-26 03:11:37 +0000