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2025-09-18Merge tag 'ib-mfd-gpio-input-pinctrl-pwm-v6.18' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next Pull changes from the immutable branch between MFD, GPIO, Input, Pinctrl and PWM trees containing the GPIO driver for max7360.
2025-09-16pinctrl: Add MAX7360 pinctrl driverMathieu Dubois-Briand
Add driver for Maxim Integrated MAX7360 pinctrl on the PORT pins. Pins can be used either for GPIO, PWM or rotary encoder functionalities. Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20250824-mdb-max7360-support-v14-3-435cfda2b1ea@bootlin.com Signed-off-by: Lee Jones <lee@kernel.org>
2025-09-14pinctrl: apple: Add "apple,t8103-pinctrl" as compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pinctrl" anymore [1]. Use "apple,t8103-pinctrl" as fallback compatible as it is the SoC the driver and bindings were written for. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-12pinctrl: Simplify printks with pOF formatKrzysztof Kozlowski
Print full device node name with %pOF format, so the code will be a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-12Merge tag 'renesas-pinctrl-for-v6.18-tag2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.18 (take two) - Improve suspend/resume support on RZ/G2L family SoCs, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-12Merge tag 'samsung-pinctrl-6.18' of ↵Linus Walleij
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.18 1. Add pin controller drivers for new Axis ARTPEC-8 SoC. The SoC shares all main blocks, including the pin controller, with Samsung SoC, so same drivers and bindings are used. 2. Drop remaining support for Samsung S3C2410 SoC pin controllers. The actual SoC support was removed in January 2023, so this is just remaining cleanup. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-10pinctrl: qcom: Add SDM660 LPASS LPI TLMMRichard Acayan
The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses predefined pin_offsets for each pin taken from downstream driver, which does not follow the usual 0x1000 distance between pins and uses an array with predefined offsets that do not follow any regular pattern [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Richard Acayan <mailingradian@gmail.com> Co-developed-by: Nickolay Goppen <setotau@mainlining.org> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-10pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsetsNickolay Goppen
By default pin_offset is calculated by formula: LPI_TLMM_REG_OFFSET * pin_id. However not all platforms are using this pin_offset formula (e.g. SDM660 LPASS LPI uses a predefined array of offsets [1]), so extend lpi_pingroup struct with pin_offset field, introduce extended LPI_PINGROUP_OFFSET macro with pin_offet field and introduce LPI_FLAG_USE_PREDEFINED_PIN_OFFSET flag. This adds an ability to use predefined offset for pin if it exists. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: airoha: fix wrong MDIO function bitmaksChristian Marangi
With further testing with an attached Aeonsemi it was discovered that the pinctrl MDIO function applied the wrong bitmask. The error was probably caused by the confusing documentation related to these bits. Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE is never actually set but instead it's set force enable to the 2 GPIO (gpio 1-2) for MDC and MDIO pin. The usage of GPIO might be confusing but this is just to instruct the SoC to not mess with those 2 PIN and as Benjamin reported it's also an Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function (that is configured by a different register) but it's really to actually ""enable"" those lines. Normally the SoC should autodetect this by HW but it seems AN7581 have problem with this and require this workaround to force enable the 2 pin. Applying this configuration permits correct functionality of any externally attached PHY. Cc: stable@vger.kernel.org Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Benjamin Larsson <benjamin.larsson@genexis.eu> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: airoha: fix wrong PHY LED mux value for LED1 GPIO46Christian Marangi
In all the MUX value for LED1 GPIO46 there is a Copy-Paste error where the MUX value is set to LED0_MODE_MASK instead of LED1_MODE_MASK. This wasn't notice as there were no board that made use of the secondary PHY LED but looking at the internal Documentation the actual value should be LED1_MODE_MASK similar to the other GPIO entry. Fix the wrong value to apply the correct MUX configuration. Cc: stable@vger.kernel.org Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: qcom: Add glymur pinctrl driverPankaj Patil
Add TLMM pinctrl driver to support pin configuration with pinctrl framework for Glymur SoC. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: qcom: sm8250: Add egpio supportSean Parker
This mirrors the egpio support added to sc7280/sm8450/etc. This change is necessary for GPIOs 146 - 179 (34 GPIOs) to be used as normal GPIOs. Signed-off-by: Sean Parker <sean.parker@viasat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVELLinus Walleij
This generic pin config property is confusingly named so let's rename it to make things clearer. There are already drivers in the tree that use PIN_CONFIG_OUTPUT to *read* the value of an output driven pin, which is a big semantic confusion for the head: are we then reading the setting of the output or the actual value/level that is put out on the pin? We already have PIN_CONFIG_OUTPUT_ENABLE that turns on driver buffers for output, so this can by logical conclusion only drive the voltage level if it should be any different. But if we read the pin, are we then reading the *setting* of the output value or the *actual* value we can see on the line? If the pin has not first been set into output mode with PIN_CONFIG_OUTPUT_ENABLE, but is instead in some input mode or tristate, what will reading this property actually return? Reading the current users reading this property it is clear that what we read is the logical level of the pin as 0 or 1 depending on if it is low or high. Rename it to PIN_CONFIG_LEVEL so it is crystal clear that we set or read the voltage level of the pin and nothing else. Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: keembay: fix double free in keembay_build_functions()Dan Carpenter
This kfree() was accidentally left over when we converted to devm_ and it would lead to a double free. Delete it. Fixes: 995bc9f4826e ("pinctrl: keembay: release allocated memory in detach path") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: spacemit: fix typo in PRI_TDI pin nameHendrik Hamerlinck
The datasheet lists this signal as PRI_TDI, not PRI_DTI. Fix the pin name to match the documentation and JTAG naming convention (TDI = Test Data In). Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: eswin: Fix regulator error check and Kconfig dependencyYulin Lu
Smatch reported the following warning in eic7700_pinctrl_probe(): drivers/pinctrl/pinctrl-eic7700.c:638 eic7700_pinctrl_probe() warn: passing zero to 'PTR_ERR' The root cause is that devm_regulator_get() may return NULL when CONFIG_REGULATOR is disabled. In such case, IS_ERR_OR_NULL() triggers PTR_ERR(NULL) which evaluates to 0, leading to passing a success code as an error. However, this driver cannot work without a regulator. To fix this: - Change the check from IS_ERR_OR_NULL() to IS_ERR() - Update Kconfig to explicitly select REGULATOR and REGULATOR_FIXED_VOLTAGE, ensuring that the regulator framework is always available. This resolves the Smatch warning and enforces the correct dependency. Suggested-by: Dan Carpenter <dan.carpenter@linaro.org> Fixes: 5b797bcc00ef ("pinctrl: eswin: Add EIC7700 pinctrl driver") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/linux-gpio/aKRGiZ-fai0bv0tG@stanley.mountain/ Signed-off-by: Yulin Lu <luyulin@eswincomputing.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: bcm: Add STB family pin controller driverIvan T. Ivanov
This driver provide pin muxing and configuration functionality for BCM2712 SoC used by RPi5. According to [1] this chip is an instance of the one used in Broadcom STB product line. [1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/ Cc: Jonathan Bell <jonathan@raspberrypi.com> Cc: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Reviewed-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Andrea della Porta <andrea.porta@suse.com> [linusw: Enable also for ARCH_BCM2835] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: qcom: make the pinmuxing strictBartosz Golaszewski
The strict flag in struct pinmux_ops disallows the usage of the same pin as a GPIO and for another function. Without it, a rouge user-space process with enough privileges (or even a buggy driver) can request a used pin as GPIO and drive it, potentially confusing devices or even crashing the system. Set it globally for all pinctrl-msm users. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functionsBartosz Golaszewski
Allow pins muxed to the "gpio" or "egpio" function to be requested as GPIOs even if pinmux_ops say the controller should be strict. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: qcom: add infrastructure for marking pin functions as GPIOsBartosz Golaszewski
Add a helper macro that wraps PINCTRL_GPIO_PINFUNCTION() for pinctrl-msm pin functions and assign the .function_is_gpio() callback in pinmux_ops. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: allow to mark pin functions as requestable GPIOsBartosz Golaszewski
The name of the pin function has no real meaning to pinctrl core and is there only for human readability of device properties. Some pins are muxed as GPIOs but for "strict" pinmuxers it's impossible to request them as GPIOs if they're bound to a devide - even if their function name explicitly says "gpio". Add a new field to struct pinfunction that allows to pass additional flags to pinctrl core. While we could go with a boolean "is_gpio" field, a flags field is more future-proof. If the PINFUNCTION_FLAG_GPIO is set for a given function, the pin muxed to it can be requested as GPIO even on strict pin controllers. Add a new callback to struct pinmux_ops - function_is_gpio() - that allows pinmux core to inspect a function and see if it's a GPIO one. Provide a generic implementation of this callback. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: qcom: use generic pin function helpersBartosz Golaszewski
With the pinmux core no longer duplicating memory used to store the struct pinfunction objects in .rodata, we can now use the existing infrastructure for storing and looking up pin functions in qualcomm drivers. Remove hand-crafted callbacks. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: make struct pinfunction a pointer in struct function_descBartosz Golaszewski
We currently duplicate the entire struct pinfunction object in pinmux_generic_add_pinfunction(). While this is inevitable when the arguments come in split through pinmux_generic_add_function(), users of pinmux_generic_add_pinfunction() will typically pass addresses of structures in .rodata, meaning we can try to avoid the duplication with the help from kmemdup_const(). To that end: don't wrap the entire struct pinfunction in struct function_desc but rather just store the address. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: constify pinmux_generic_get_function()Bartosz Golaszewski
With all users of struct function_desc limited to only accessing it using the dedicated function and never modifying it, we can now constify the return value of pinmux_generic_get_function() treewide. Reviewed-by: Andy Shevchenko <andy@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: keembay: use a dedicated structure for the pinfunction descriptionBartosz Golaszewski
struct function_desc is a wrapper around struct pinfunction with an additional void *data pointer. We're working towards reducing the usage of struct function_desc in pinctrl drivers - they should only be created by pinmux core and accessed by drivers using pinmux_generic_get_function(). This driver uses the data pointer so in order to stop using struct function_desc, we need to provide an alternative that also wraps the mux mode which is passed to pinctrl core as user data. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: keembay: release allocated memory in detach pathBartosz Golaszewski
Unlike all the other allocations in this driver, the memory for storing the pin function descriptions allocated with kcalloc() and later resized with krealloc() is never freed. Use devres like elsewhere to handle that. While at it - replace krealloc() with more suitable devm_krealloc_array(). Note: the logic in this module is pretty convoluted and could probably use some revisiting, we should probably be able to calculate the exact amount of memory needed in advance or even skip the allocation altogether and just add each function to the radix tree separately. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: imx: don't access the pin function radix tree directlyBartosz Golaszewski
The radix tree containing pin function descriptors should not be accessed directly by drivers. There are dedicated functions for it. I suppose this driver does it so that the memory containing the function description is not duplicated but we're going to address that shortly so convert it to using generic pinctrl APIs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: mediatek: moore: replace struct function_desc with struct pinfunctionBartosz Golaszewski
struct function_desc is a wrapper around struct pinfunction with an additional void *data pointer. This driver doesn't use the data pointer. We're also working towards reducing the usage of struct function_desc in pinctrl drivers - they should only be created by pinmux core and accessed by drivers using pinmux_generic_get_function(). Replace the struct function_desc objects in this driver with smaller struct pinfunction instances. Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: mediatek: mt7988: use PINCTRL_PIN_FUNCTION()Bartosz Golaszewski
We have a dedicated initializer macro for defining pin functions for mediatek drivers so use it here. Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: airoha: replace struct function_desc with struct pinfunctionBartosz Golaszewski
struct function_desc is a wrapper around struct pinfunction with an additional void *data pointer. This driver doesn't use the data pointer. We're also working towards reducing the usage of struct function_desc in pinctrl drivers - they should only be created by pinmux core and accessed by drivers using pinmux_generic_get_function(). Replace the struct function_desc objects in this driver with smaller struct pinfunction instances. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: ingenic: use struct pinfunction instead of struct function_descBartosz Golaszewski
struct function_desc is a wrapper around struct pinfunction with an additional void *data pointer. This driver doesn't use the data pointer. We're also working towards reducing the usage of struct function_desc in pinctrl drivers - they should only be created by pinmux core and accessed by drivers using pinmux_generic_get_function(). Replace the struct function_desc objects in this driver with smaller struct pinfunction instances. Acked-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: check the return value of pinmux_ops::get_function_name()Bartosz Golaszewski
While the API contract in docs doesn't specify it explicitly, the generic implementation of the get_function_name() callback from struct pinmux_ops - pinmux_generic_get_function_name() - can fail and return NULL. This is already checked in pinmux_check_ops() so add a similar check in pinmux_func_name_to_selector() instead of passing the returned pointer right down to strcmp() where the NULL can get dereferenced. This is normal operation when adding new pinfunctions. Cc: stable@vger.kernel.org Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: ma35: Use int type to store negative error codesQianfeng Rong
Change the 'ret' variable in ma35_pinctrl_parse_functions() from u32 to int, as it needs to store either negative error codes or zero returned by ma35_pinctrl_parse_groups(). No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: armada-37xx: Use int type to store negative error codesQianfeng Rong
In armada_37xx_gpio_direction_output(), the 'ret' variable might store the negative error codes returned by regmap_update_bits(), and in armada_37xx_edge_both_irq_swap_pol(), the 'ret' variable directly stores -1, so the type of the 'ret' variable needs to be changed to int in both cases. No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: renesas: r8a779g0: Fix trivial typo in SoC type commentMarek Vasut
Fix SoC type comment in the PFC table file, replace R8A779A0 likely copy-paste error with R8A779G0. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250904222806.193260-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08pinctrl: renesas: Use int type to store negative error codesQianfeng Rong
Change the 'ret' variable in sh_pfc_pinconf_group_set() from unsigned int to int, as it needs to store either negative error codes or zero returned by sh_pfc_pinconf_set(). No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Fixes: d0593c363f04ccc4 ("pinctrl: sh-pfc: Propagate errors on group config") Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250831084958.431913-4-rongqianfeng@vivo.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control ↵Biju Das
registers Renesas RZ/G3E supports a power-saving mode where power to most of the SoC components is lost, including the PIN controller. Save and restore the Schmitt control register contents to ensure the functionality is preserved after a suspend/resume cycle. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250819084022.20512-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08pinctrl: renesas: rzg2l: Fix OEN resumeBiju Das
Writing to the PFC_OEN register is controlled by the write protect register (PWPR). Currently the OEN register write in resume() is done without enabling write access in PWPR leading to incorrect operation. Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [geert: Move spin_*lock*() calls inside if-statements] Link: https://lore.kernel.org/20250817143024.165471-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08Merge tag 'v6.17-rc5' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next Linux 6.17-rc5
2025-09-03gpio: nomadik: don't print out global GPIO numbers in debugfs callbacksBartosz Golaszewski
In order to further limit the number of references to the GPIO base number stored in struct gpio_chip, replace the global GPIO numbers in the output of debugfs callbacks by hardware offsets. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250826-gpio-dbg-show-base-v1-2-7f27cd7f2256@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-09-02pinctrl: samsung: Drop unused S3C24xx driver dataKrzysztof Kozlowski
Drop unused declarations after S3C24xx SoC family removal in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"). Fixes: 1ea35b355722 ("ARM: s3c: remove s3c24xx specific hacks") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250830111657.126190-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-01pinctrl: samsung: Add ARTPEC-8 SoC specific configurationSeonGu Kang
Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250901051926.59970-3-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30Merge tag 'renesas-pinctrl-for-v6.18-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.18 - Add support for Output Enable (OEN) on RZ/G3E, - Add support for the RZ/T2H and RZ/N2H SoCs, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-29drivers: firmware: xilinx: Switch to new family code in ↵Jay Buddhabhatti
zynqmp_pm_get_family_info() Currently, the family code and subfamily code are derived from the PMC_TAP_IDCODE register. Versal, Versal NET share the same family code. Also some platforms share the same subfamily code, making it difficult to distinguish between platforms. Update zynqmp_pm_get_family_info() to use IDs derived from the compatible string instead of silicon ID codes derived from PMC_TAP_IDCODE register. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20250701123851.1314531-4-jay.buddhabhatti@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-28pinctrl: meson-gxl: add missing i2c_d pinmuxDa Xue
Amlogic GXL has 4 I2C attached to gpio-periphs. I2C_D is on GPIOX_10/11. Add the relevant func 3 pinmux per the datasheet for S805X/S905X/S905D. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Signed-off-by: Da Xue <da@libre.computer> Link: https://lore.kernel.org/20250821233335.1707559-1-da@libre.computer Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-27pinctrl: Add pinctrl_pm_select_init_state helper functionChristian Bruel
If a platform requires an initial pinctrl state during probing, this helper function provides the client with access to the same initial state. eg: xxx_suspend_noirq ... pinctrl_pm_select_sleep_state xxx resume_noirq pinctrl_pm_select_init_state ... pinctrl_pm_select_default_state Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patch.msgid.link/20250820075411.1178729-3-christian.bruel@foss.st.com
2025-08-22pinctrl: airoha: Fix return value in pinconf callbacksLorenzo Bianconi
Pinctrl stack requires ENOTSUPP error code if the parameter is not supported by the pinctrl driver. Fix the returned error code in pinconf callbacks if the operation is not supported. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/20250822-airoha-pinconf-err-val-fix-v1-1-87b4f264ced2@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-22pinctrl: amd: Don't access irq_data's hwirq member directlyMario Limonciello (AMD)
There is an irqd_to_hwirq() intended to get the hwirq number. Switch all use to it. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250821144942.2463014-1-superm1@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-22pinctrl: STMFX: add missing HAS_IOMEM dependencyRandy Dunlap
When building on ARCH=um (which does not set HAS_IOMEM), kconfig reports an unmet dependency caused by PINCTRL_STMFX. It selects MFD_STMFX, which depends on HAS_IOMEM. To stop this warning, PINCTRL_STMFX should also depend on HAS_IOMEM. kconfig warning: WARNING: unmet direct dependencies detected for MFD_STMFX Depends on [n]: HAS_IOMEM [=n] && I2C [=y] && OF [=y] Selected by [y]: - PINCTRL_STMFX [=y] && PINCTRL [=y] && I2C [=y] && OF_GPIO [=y] Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/20250815022721.1650885-1-rdunlap@infradead.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-22pinctrl: amd: Add PM debugging message for turning on/off wakesMario Limonciello (AMD)
The GPIOs for devices not in _AEI/_EVT such as touchpad or touchscreen won't have wakeup turned on until the suspend sequence starts. Due to code in amd_gpio_suspend_hibernate_common() masking the interrupt can make this difficult to follow what's going on. Add an explicit debugging message to tell when that was turned on/off. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://lore.kernel.org/20250814183430.3887973-2-superm1@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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