summaryrefslogtreecommitdiff
path: root/drivers/soc
AgeCommit message (Collapse)Author
2025-07-28Merge tag 'hardening-v6.17-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux Pull hardening updates from Kees Cook: - Introduce and start using TRAILING_OVERLAP() helper for fixing embedded flex array instances (Gustavo A. R. Silva) - mux: Convert mux_control_ops to a flex array member in mux_chip (Thorsten Blum) - string: Group str_has_prefix() and strstarts() (Andy Shevchenko) - Remove KCOV instrumentation from __init and __head (Ritesh Harjani, Kees Cook) - Refactor and rename stackleak feature to support Clang - Add KUnit test for seq_buf API - Fix KUnit fortify test under LTO * tag 'hardening-v6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: (22 commits) sched/task_stack: Add missing const qualifier to end_of_stack() kstack_erase: Support Clang stack depth tracking kstack_erase: Add -mgeneral-regs-only to silence Clang warnings init.h: Disable sanitizer coverage for __init and __head kstack_erase: Disable kstack_erase for all of arm compressed boot code x86: Handle KCOV __init vs inline mismatches arm64: Handle KCOV __init vs inline mismatches s390: Handle KCOV __init vs inline mismatches arm: Handle KCOV __init vs inline mismatches mips: Handle KCOV __init vs inline mismatch powerpc/mm/book3s64: Move kfence and debug_pagealloc related calls to __init section configs/hardening: Enable CONFIG_INIT_ON_FREE_DEFAULT_ON configs/hardening: Enable CONFIG_KSTACK_ERASE stackleak: Split KSTACK_ERASE_CFLAGS from GCC_PLUGINS_CFLAGS stackleak: Rename stackleak_track_stack to __sanitizer_cov_stack_depth stackleak: Rename STACKLEAK to KSTACK_ERASE seq_buf: Introduce KUnit tests string: Group str_has_prefix() and strstarts() kunit/fortify: Add back "volatile" for sizeof() constants acpi: nfit: intel: avoid multiple -Wflex-array-member-not-at-end warnings ...
2025-07-25Merge tag 'hisi-drivers-for-6.17' of https://github.com/hisilicon/linux-hisi ↵Arnd Bergmann
into soc/drivers HiSilicon driver updates for v6.17 - Print the hardware ID instead of the index in the HCCS driver * tag 'hisi-drivers-for-6.17' of https://github.com/hisilicon/linux-hisi: soc: hisilicon: kunpeng_hccs: Fix incorrect log information Link: https://lore.kernel.org/r/6879FFED.1050002@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-25Merge tag 'qcom-drivers-for-6.17-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers More Qualcomm driver updates for v6.17 Fix race condition during SCM driver initialization, in relation to tzmem and waitqueue irq handling, Make the rpmh RSC driver support version 4 of the IP block. Add SM7635 family and related PMICs to the socinfo driver. Also add support for retrieving the bootloader build details. * tag 'qcom-drivers-for-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface soc: qcom: socinfo: Add support to retrieve APPSBL build details soc: qcom: pmic_glink: fix OF node leak soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs soc: qcom: socinfo: Add SoC IDs for SM7635 family dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family firmware: qcom: scm: request the waitqueue irq *after* initializing SCM firmware: qcom: scm: initialize tzmem before marking SCM as available firmware: qcom: scm: take struct device as argument in SHM bridge enable firmware: qcom: scm: remove unused arguments from SHM bridge routines soc: qcom: rpmh-rsc: Add RSC version 4 support Link: https://lore.kernel.org/r/20250720030743.285440-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-24soc: apple: rtkit: Make shmem_destroy optionalSven Peter
shmem_destroy isn't always required for coprocessor-managed buffers but we still enforce that it exists. Just relax the check. Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Sven Peter <sven@kernel.org> Link: https://lore.kernel.org/r/20250610-smc-6-15-v7-4-556cafd771d3@kernel.org Signed-off-by: Lee Jones <lee@kernel.org>
2025-07-22Merge tag 'qcom-drivers-for-6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.17 Perform input validation in the MDT loader, as this was not properly done in the non-remoteproc cases. Fix endian issues in the QMI encoder/decoder. Support reading DDR statistic using the Qualcomm stats driver. Add support for reading TME firmware details to the socinfo driver. Document the Kryo 470 CPU, and add SM7150 to the DCC to DeviceTree bindings. * tag 'qcom-drivers-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: mdt_loader: Fix error return values in mdt_header_valid() dt-bindings: sram: qcom,imem: Add a number of missing compatibles dt-bindings: arm: cpus: Add Kryo 470 CPUs dt-bindings: sram: qcom,imem: Add the SM7150 compatible dt-bindings: soc: qcom: aoss-qmp: Add the SM7150 compatible dt-bindings: soc: qcom,dcc: Add the SM7150 compatible soc: qcom: socinfo: Add support to retrieve TME build details soc: qcom: fix endianness for QMI header soc: qcom: QMI encoding/decoding for big endian dt-bindings: soc: qcom: add qcom,qcs615-imem compatible soc: qcom: qcom_stats: Add QMP support for syncing ddr stats soc: qcom: qcom_stats: Add support to read DDR statistic soc: qcom: mdt_loader: Actually use the e_phoff soc: qcom: mdt_loader: Rename mdt_phdr_valid() soc: qcom: mdt_loader: Ensure we don't read past the ELF header Link: https://lore.kernel.org/r/20250715021454.14516-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-22soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platformsPraveen Talari
On the sa8255p platform, resources such as clocks,interconnects and TLMM (GPIO) configurations are managed by firmware. Use the `num_clks` field in platform data to distinguish whether resource control is performed by firmware or directly by the driver in linux. Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com> Link: https://lore.kernel.org/r/20250721174532.14022-4-quic_ptalari@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-21arm: Handle KCOV __init vs inline mismatchesKees Cook
When KCOV is enabled all functions get instrumented, unless the __no_sanitize_coverage attribute is used. To prepare for __no_sanitize_coverage being applied to __init functions, we have to handle differences in how GCC's inline optimizations get resolved. For arm this exposed several places where __init annotations were missing but ended up being "accidentally correct". Fix these cases and force several functions to be inline with __always_inline. Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20250717232519.2984886-5-kees@kernel.org Signed-off-by: Kees Cook <kees@kernel.org>
2025-07-21Merge tag 'tegra-for-6.17-soc' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Updates for v6.17-rc1 The bulk of this is the addition of Tegra264 support for various low- level components. This also adds fabric descriptors for the new Tegra254 and Tegra264 chips. * tag 'tegra-for-6.17-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Add support for CBB fabrics in Tegra254 soc/tegra: cbb: Add support for CBB fabrics in Tegra264 soc/tegra: cbb: Support HW lookup to get timed out target address soc/tegra: cbb: Improve handling for per SoC fabric data soc/tegra: cbb: Make error interrupt enable and status per SoC soc/tegra: cbb: Change master/slave to initiator/target soc/tegra: cbb: Clear ERR_FORCE register with ERR_STATUS soc/tegra: Add Tegra264 APBMISC compatible string soc/tegra: pmc: Add Tegra264 support soc/tegra: Enable support for Tegra264 Link: https://lore.kernel.org/r/20250711220943.2389322-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21soc: fsl: qe: convert set_multiple() to returning an integerBartosz Golaszewski
The conversion to using the new GPIO line setter callbacks missed the set_multiple() in this file. Convert it to using the new callback. Fixes: 52ccf19527fd ("soc: fsl: qe: use new GPIO line value setter callbacks") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-21Merge tag 'mtk-soc-for-v6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers MediaTek soc driver updates for v6.17 This adds a single cleanup commit for the mtk-mutex driver, clarifying the usage of the MUTEX_MOD1, MUTEX_MOD2 registers for applying display controller sub-component mute settings on all MediaTek SoCs. * tag 'mtk-soc-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: soc: mediatek: mtk-mutex: Fix confusing usage of MUTEX_MOD2 Link: https://lore.kernel.org/r/20250711083656.33538-4-angelogioacchino.delregno@collabora.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'soc_fsl-6.17-1' of https://github.com/chleroy/linux into soc/driversArnd Bergmann
FSL SOC Changes for 6.17: - Use dev_fwnode() instead of of_fwnode_handle() - Use new GPIO line value setter callbacks * tag 'soc_fsl-6.17-1' of https://github.com/chleroy/linux: soc: Use dev_fwnode() soc: fsl: qe: use new GPIO line value setter callbacks Link: https://lore.kernel.org/r/c947d537-cae5-44f0-abd8-0c558bac46d2@csgroup.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'aspeed-6.17-drivers-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/drivers ASPEED SoC driver updates for 6.17 The ASPEED LPC snoop driver was recently the cause of some concern. In addition to the initial fixes, the channel configuration paths are refactored to improve robustness against errors. * tag 'aspeed-6.17-drivers-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: soc: aspeed: lpc-snoop: Lift channel config to const structs soc: aspeed: lpc-snoop: Consolidate channel initialisation soc: aspeed: lpc-snoop: Use dev_err_probe() where possible soc: aspeed: lpc-snoop: Switch to devm_clk_get_enabled() soc: aspeed: lpc-snoop: Rearrange channel paths soc: aspeed: lpc-snoop: Rename 'channel' to 'index' in channel paths soc: aspeed: lpc-snoop: Constrain parameters in channel paths soc: aspeed: lpc-snoop: Ensure model_data is valid soc: aspeed: lpc-snoop: Don't disable channels that aren't enabled soc: aspeed: lpc-snoop: Cleanup resources in stack-order Link: https://lore.kernel.org/r/9123f151280e52c63dcb645cb07d4eee3462c067.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-18soc: hisilicon: kunpeng_hccs: Fix incorrect log informationHuisong Li
The hccs_get_all_spec_port_idle_sta() will tell user which port is busy when firmware doesn't allow to decrease HCCS lane number. However, the current log prints the index of die and port instead of the hardware ID user perceived. Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2025-07-16soc: qcom: socinfo: Add support to retrieve APPSBL build detailsKathiravan Thirumoorthy
Add support to retrieve APPS (Application Processor Subsystem) Bootloader image details from SMEM. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250711-appsbl_crm_version-v1-1-48b49b1dfdcf@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16soc: qcom: pmic_glink: fix OF node leakJohan Hovold
Make sure to drop the OF node reference taken when registering the auxiliary devices when the devices are later released. Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Cc: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250708085717.15922-1-johan@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDsRakesh Kota
Add the PMM8650AU and PMM8650AU_PSAIL PMIC SUBTYPE IDs and These PMICs are used by the qcs8300 and qcs9100 platforms. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250704113036.1627695-1-rakesh.kota@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICsLuca Weiss
Add the PM7550 and PMIV0108 to the pmic_models array. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250625-sm7635-socinfo-v1-3-be09d5c697b8@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16soc: qcom: socinfo: Add SoC IDs for SM7635 familyLuca Weiss
Add the entries for the 'volcano' family, namely SM7635, SM6650, SM6650P, QCM6690 and QCS6690. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250625-sm7635-socinfo-v1-2-be09d5c697b8@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16soc: qcom: rpmh-rsc: Add RSC version 4 supportMaulik Shah
Register offsets for v3 and v4 versions are backward compatible. Assign v3 offsets for v4 and all higher versions to avoid end up using v2 offsets. Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250623-rsc_v4-v1-1-275b27bc5e3c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-09soc/tegra: cbb: Add support for CBB fabrics in Tegra254Sumit Gupta
Add support for CBB 2.0 based fabrics in Tegra254 SoC using ACPI. Fabrics reporting errors are: C2C, GPU and Display_Cluster. Tegra254 uses a hardware based lookup to get target node address, so the target_map tables for each fabric are no longer needed. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: cbb: Add support for CBB fabrics in Tegra264Sumit Gupta
Add support for CBB 2.0 based fabrics in Tegra264 SoC using DT. Fabrics reporting errors are: SYSTEM, TOP0, UPHY0 and VISION. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: cbb: Support HW lookup to get timed out target addressSumit Gupta
Add support for hardware based lookup to get the address of the timed out target node. This features is added in upcoming SoCs and avoids the need for creating per fabric target_map tables in the driver. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: cbb: Improve handling for per SoC fabric dataSumit Gupta
Improve handling for the per SoC fabrics and targets. The below changes make them more flexible and ready for future SoC's. - Added SoC prefix to Fabric_ID enums. - Rename *lookup_target_timeout() to *sw_lookup_target_timeout() to make it separate from HW based lookup function to be added later. - Moved target_map within fabric_lookup table to make it easy to check whether SW vs HW lookup is supported and handle accordingly. - Slight improvements to some error prints. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: cbb: Make error interrupt enable and status per SoCSumit Gupta
Make the error interrupt enable and error status fields as per SoC. Both of these fields can change for different SoC's. Moving them to per SoC data helps to set or clear the required bits only for a SoC. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: cbb: Change master/slave to initiator/targetSumit Gupta
Change usage of 'Master/Slave' to 'Initiator/Target' as per the new convention. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: cbb: Clear ERR_FORCE register with ERR_STATUSSumit Gupta
When error is injected with the ERR_FORCE register, then this register is not auto cleared on clearing the ERR_STATUS register. This causes repeated interrupts on error injection. To fix, set the ERR_FORCE to zero along with clearing the ERR_STATUS register after handling error. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-09soc/tegra: pmc: Opt-out from genpd's common ->sync_state() supportUlf Hansson
Tegra implements its own specific ->sync_state() callback for the genpd providers. Let's set the GENPD_FLAG_NO_SYNC_STATE to inform genpd about it. Moreover, let's call of_genpd_sync_state() to make sure genpd tries to power off unused PM domains. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Colibri iMX8X Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> # TI AM62A,Xilinx ZynqMP ZCU106 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20250701114733.636510-10-ulf.hansson@linaro.org
2025-07-08soc: renesas: Sort Renesas Kconfig configsKuninori Morimoto
Renesas Kconfig is using "SoC serial number" for CONFIG symbol, but is using "SoC chip name" for menu description. Because of it, it looks random order when we run "make menuconfig". commit 6d5aded8d57fc ("soc: renesas: Sort driver description title") sorted Renesas Kconfig by menu description title order, but it makes confusable to add new config. Let's unify "ARMxx Platform support for ${CHIP_NUMBER} (${CHIP_NAME}), and sort it again. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/877c0xhk3z.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-08soc: Use dev_fwnode()Jiri Slaby (SUSE)
irq_domain_create_simple() takes fwnode as the first argument. It can be extracted from the struct device using dev_fwnode() helper instead of using of_node with of_fwnode_handle(). So use the dev_fwnode() helper. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Cc: Qiang Zhao <qiang.zhao@nxp.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxppc-dev@lists.ozlabs.org Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/linuxppc-dev/20250611104348.192092-19-jirislaby@kernel.org/ Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2025-07-08soc: fsl: qe: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250610-gpiochip-set-rv-soc-v1-1-1a0c36c9deed@linaro.org Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2025-07-08soc: aspeed: lpc-snoop: Lift channel config to const structsAndrew Jeffery
The shifts and masks for each channel are defined by hardware and are not something that changes at runtime. Accordingly, describe the information in an array of const structs and associate elements with each channel instance, removing the need for the switch and handling of its default case. Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-10-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Consolidate channel initialisationAndrew Jeffery
Previously, channel initialisation was a bit perilous with respect to resource cleanup in error paths. While the implementation had issues, it at least made an effort to eliminate some of its problems by first testing whether any channels were enabled, and bailing out if not. Having improved the robustness of resource handling in probe() we can now rearrange the initial channel test to be located with the subsequent test, and rework the unrolled conditional logic to use a loop for an improvement in readability. Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-9-3cdd59c934d3@codeconstruct.com.au Acked-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Use dev_err_probe() where possibleAndrew Jeffery
Exploit that it returns the provided error to eliminate some lines, and return the actual error involved rather than -ENODEV. Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-8-3cdd59c934d3@codeconstruct.com.au Acked-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Switch to devm_clk_get_enabled()Andrew Jeffery
Simplify clock handling as done in other drivers. Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-7-3cdd59c934d3@codeconstruct.com.au Acked-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Rearrange channel pathsAndrew Jeffery
Order assignments such that tests for conditions not involving resource acquisition are ordered before those testing acquired resources, and order managed resource acquisition before unmanaged where possible. This way we minimise the amount of manual cleanup required. In the process, improve readability of the code by introducing a channel pointer that takes the place of the repeated object lookups. Acked-by: Jean Delvare <jdelvare@suse.de> Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-6-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Rename 'channel' to 'index' in channel pathsAndrew Jeffery
We'll introduce another 'channel' variable shortly Acked-by: Jean Delvare <jdelvare@suse.de> Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-5-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Constrain parameters in channel pathsAndrew Jeffery
Ensure pointers and the channel index are valid before use. Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-4-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-08soc: aspeed: lpc-snoop: Ensure model_data is validAndrew Jeffery
of_device_get_match_data() can return NULL, though shouldn't in current circumstances. Regardless, initialise model_data closer to use so it's clear we need to test for validity prior to dereferencing. Acked-by: Jean Delvare <jdelvare@suse.de> Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-3-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-07arm64: defconfig: Enable Tegra HSP and BPMPThierry Reding
Selecting the IVC, HSP and BPMP drivers via Kconfig is problematic because it can create conflicting configurations. Instead, enable them in the default configuration. Link: https://lore.kernel.org/r/20250506133118.1011777-12-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-07soc/tegra: Add Tegra264 APBMISC compatible stringThierry Reding
Link: https://lore.kernel.org/r/20250506133118.1011777-9-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-07soc/tegra: pmc: Add Tegra264 supportThierry Reding
The PMC block on Tegra264 has undergone a few small changes since it's Tegra234 predecessor. Match on the new compatible string to select the updated SoC-specific data. Link: https://lore.kernel.org/r/20250506133118.1011777-8-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-07soc/tegra: Enable support for Tegra264Thierry Reding
Tegra264 is the successor to Tegra234, with various improvements and new hardware. Link: https://lore.kernel.org/r/20250506133118.1011777-7-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-04soc: qcom: ubwc: Fill in UBWC swizzle cfg for platforms that lack oneKonrad Dybcio
The UBWC 1.0 case is easy - it must be all 3 enabled. UBWC2.0 and 3.x require that level1 is removed, follow suit. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660983/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-04soc: qcom: ubwc: Add #defines for UBWC swizzle bitsKonrad Dybcio
Make the values a bit more meaningful. This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660981/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-04soc: qcom: ubwc: Fix SM6125's ubwc_swizzle valueKonrad Dybcio
The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of swizzling) is what we want on this platform (and others with a UBWC 1.0 encoder). Fix it to make mesa happy (the hardware doesn't care about the 2 higher bits, as they weren't consumed on this platform). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660980/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-04soc: qcom: Add UBWC config providerKonrad Dybcio
Add a file that will serve as a single source of truth for UBWC configuration data for various multimedia blocks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660959/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-02soc: aspeed: lpc-snoop: Don't disable channels that aren't enabledAndrew Jeffery
Mitigate e.g. the following: # echo 1e789080.lpc-snoop > /sys/bus/platform/drivers/aspeed-lpc-snoop/unbind ... [ 120.363594] Unable to handle kernel NULL pointer dereference at virtual address 00000004 when write [ 120.373866] [00000004] *pgd=00000000 [ 120.377910] Internal error: Oops: 805 [#1] SMP ARM [ 120.383306] CPU: 1 UID: 0 PID: 315 Comm: sh Not tainted 6.15.0-rc1-00009-g926217bc7d7d-dirty #20 NONE ... [ 120.679543] Call trace: [ 120.679559] misc_deregister from aspeed_lpc_snoop_remove+0x84/0xac [ 120.692462] aspeed_lpc_snoop_remove from platform_remove+0x28/0x38 [ 120.700996] platform_remove from device_release_driver_internal+0x188/0x200 ... Fixes: 9f4f9ae81d0a ("drivers/misc: add Aspeed LPC snoop driver") Cc: stable@vger.kernel.org Cc: Jean Delvare <jdelvare@suse.de> Acked-by: Jean Delvare <jdelvare@suse.de> Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-2-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-02soc: aspeed: lpc-snoop: Cleanup resources in stack-orderAndrew Jeffery
Free the kfifo after unregistering the miscdev in aspeed_lpc_disable_snoop() as the kfifo is initialised before the miscdev in aspeed_lpc_enable_snoop(). Fixes: 3772e5da4454 ("drivers/misc: Aspeed LPC snoop output using misc chardev") Cc: stable@vger.kernel.org Cc: Jean Delvare <jdelvare@suse.de> Acked-by: Jean Delvare <jdelvare@suse.de> Link: https://patch.msgid.link/20250616-aspeed-lpc-snoop-fixes-v2-1-3cdd59c934d3@codeconstruct.com.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-25soc: qcom: mdt_loader: Fix error return values in mdt_header_valid()Dan Carpenter
This function is supposed to return true for valid headers and false for invalid. In a couple places it returns -EINVAL instead which means the invalid headers are counted as true. Change it to return false. Fixes: 9f9967fed9d0 ("soc: qcom: mdt_loader: Ensure we don't read past the ELF header") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/db57c01c-bdcc-4a0f-95db-b0f2784ea91f@sabinyo.mountain Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-25soc: mediatek: mtk-mutex: Fix confusing usage of MUTEX_MOD2Jason-JH Lin
The usage of MUTEX_MOD1 and MUTEX_MOD2 for calculating mod settings over 32 has been confusing. To improve consistency and clarity, these defines need to fit into the same MUTEX_MOD define as possible. However, MUTEX_MOD1 cannot be directly used for all SoCs because, for example, the mod1 register (0x34) of MT2712 is not adjacent to its mod0 register (0x2c). To address this, a `mutex_mod1_reg` field is introduced in the mutex driver data structure. This allows all SoCs to use a unified MUTEX_MOD to determine their register offsets. With this change, the separate usage of MUTEX_MOD1 and MUTEX_MOD2 is eliminated, simplifying the logic for obtaining offsets and mod IDs. Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250624103928.408194-1-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-01-07 22:57:35 +0000