Age | Commit message (Collapse) | Author |
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Calculate the number of words in a transfer properly: if there are
129-131 bytes, then number of words is more than 32, therefore the
transfer should be handled with DMA rather than FIFO.
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Add stub runtime_pm calls which go through the flow of enabling and
disabling but don't actually do anything with the device itself as
there's nothing useful we can do. This provides the core PM framework
with information about when the device is idle, enabling chip wide
power savings.
Change-Id: Ie795c16840ccbe07e1a8bfac1a1c5a87281e6849
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/128184
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
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-enable warnings as errors compilation flag
-handle error of uninitialised variable
bug 949219
Change-Id: I9e754b1cbf086f99433d47aef793a8635185a25e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/118239
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sanjay Singh Rawat <srawat@nvidia.com>
Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Create all resource require for spi transfer before registering
spi master as the spi communication is possible during the
registration.
bug 1023003
Change-Id: I1f77385866f358effeffb89c6af53a6a2f1c8738
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/118267
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Add macro in the spi tegra driver for enabling/disabling
runtime PM specific to this driver.
Setting macro SPI_PM_RUNTIME_ENABLE to 1 will enable the
runtime pm and resetting to 0 make runtime pm disable.
The dynamic clock management i.e. enabling the clock before
transfer and disabling after transfer complete is done in
both the cases.
When runtime pm is enabled then clock control is done through
runtime pm callbacks otherwise it will be directly call the
clock control apis.
bug 1003103
Change-Id: I2544e8f3b3e5605e0247791653a5a0ed6c36e9b6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/112142
Reviewed-by: Automatic_Commit_Validation_User
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Check for valid entry on the message queue before
reading the transfer list from queue. If queue is
empty then do not start transfer.
Change-Id: If51a816780ab76700a7a1d7d8a025a3544590ad1
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/109469
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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When any error occurs in spi communication,
dump the spi registers for debug purpose
Change-Id: I5cf226d4b504c95a6abb8dcf5b8c0ba1ef44271c
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/109466
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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When computing required words for a transfer,
limit this to max possible size on given
sub transfer
Change-Id: Ia1a9290ae389e36ecb5a8d03be2982885a544a33
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/109462
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 995706
During device shutdown/rebooting, runtime PM is disabled. SPI bus
driver will fail to call tegra_spi_runtime_resume() to resume the
clock needed by tranferring. In this case, do not start transferring.
Change-Id: I42cc0763f55b6c90df00fbad68794939e903199a
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/109458
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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The dma allocation method for receive and transmit is
same and so instead of duplicating the same code for
rx and tx, making the function to have common code and
using the function for dma allocation.
This reduces duplicated code.
Change-Id: Ibe15eec896bc581bda8c68572eb1425c3bf6a7b2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/104465
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Using of devm_* function for resource allocation does not require
to free resource on code and hence it reduces code sizes.
Change-Id: Id6f0ba3cde2f351d5668ed28b098e5a829716a30
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/104464
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Slink controller have the fifo depth of 32 words in
rx and tx side. But some of places it was taken the
value as 4. Fixing this to 32 words.
Change-Id: I262127c59241ce75d4385464c21ee733a48b1475
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/104463
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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When any write is made to PPSB register, it take time
to actual happen in the register due to ARM-PPSB design.
Delay or readback is required to make sure that write is
completed. There is no worst case guaranteed delay and hence
doing the register read to make write completes actually.
Change-Id: Iefd25115e1a9f02c64e83f11a4e249ad9d086d16
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Cleaning up runtime pm implementation for the driver.
There is lots of duplicate code which is not require as
it is handled in the runtime framework.
Change-Id: I4494cdd3518cbcb90f24fb3387f38c9859b4f957
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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The Tx buffer to be synced with the direction of DMA_TO_DEVICE and
Rx buffer should be synced with direction of DMA_FROM_DEVICE.
bug 959947
Change-Id: I490a93e05723e3114c8ae3c640bb7eff23bcc75d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/103095
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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The Tegra spi's engine is design as it generates interrupt
when any error occurs and it keep transferring data. It does
not stop the engine once error occurred and interrupt generated.
This may cause reentry of ISR as on error case, isr get called
where it clears interrupt and because it is still in progress,
it again interrupts and schedule the thread.
The second time scheduling of the isr/thread can cause the issue
in queue management and sw state.
So Making the interrupt as ONESHOT so that the interrupt will not
get schedule until the engine is reset in error case.
Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/101547
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
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Merges of dma changes from mainline reported conflict and
it was not got resolved properly.
Fix the resolution issue.
Change-Id: I7edc5effc0b9a61363e77e6cc39eb62e315396d0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102590
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Add inline wrappers for device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to hide new parameter from current users of affected interfaces.
Convert current users to use new wrappers instead of direct calls.
Suggested by Russell King [https://lkml.org/lkml/2012/2/3/269].
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline commit
16052827d98fbc13c31ebad560af4bd53e2b4dd5
Change-Id: I929a49556539621a0546829e88b3caa498c94be2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/94463
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To terminate request from dma, use the tegra_dma_cancel() inplace of
tegra_dma_dequeue().
The api tegra_dma_dequeue() is getting to be obsolete.
Change-Id: I297e67433a2118377ecb9b028dcf8fa82e09f0e2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
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Making sure that SCLK frequency should be maintain on minimum
require value during spi transfer. This is require to proper
functioning of spi controller.
bug 949393
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89526
Cherry-picked from commit
7d83f658b39b2ab1a5105eec7649246fddea7325
Change-Id: I60fa0fef98e5f2882c646c29e1773194deddd6da
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90296
Reviewed-by: Automatic_Commit_Validation_User
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Fixing the logic to clear/set spi cs level on default command
register.
Change-Id: I55e130ecb02dae6e11ad7048730ed11df9848e94
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86888
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
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Removing checkpatch error and warnings from spi driver
resulted from checkpatch.
Change-Id: I92160e802781b583048f46a93dee7d2465689cc0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85163
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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When dma coherant buffer need to be access by cpu or apb dma,
it is require to calling the dma_sync_single_for_cpu() when cpu
wants to access it and dma_sync_single_for_device() when dma
wants to access the buffer.
Change-Id: I62fc7fced782f3fc2d145c0d5416a4c8cbe30715
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85138
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
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The dma client should use the tegra_dma_dequeue_req() for
dequeue the dma request.
Change-Id: I1f433c85ffec997d8c608e08509c48c72b27120a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77804
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Used run time apis for clock controls i.e. clock enable/
disable in place of direct clock apis.
Using of runtime pm api was already implemented but it was
missed on probe where it was calling clock_disable.
Fixing this issue.
bug 928541
Change-Id: I511467bd1cbe05f2a05d219d19236426a30d05d5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/78156
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
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Bug 886806
Original commit: http://git-master/r/59905
Change-Id: Ia8d64f3810d6157c6029180cd9a3cf98c2d3cb4c
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/74896
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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When fifo is read, it can contain valid data bits and random bits
in rest of the fifo.
Reading only valid bits from fifo and resetting rest to zero
before sending to client.
Change-Id: I961279048aada6087b323ab6730bf72706730917
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/70534
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Fixed warning message
Bug ID: 912669
Change-Id: I3090c35a5d0725102c101b10a99914510a272fa4
Reviewed-on: http://git-master/r/69444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Rebase-Id: Rbc628711479b187a90437bea94776066c7a58b54
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These changes have no effect if CONFIG_GCOV_KERNEL is not set in
defconfig. It is easier to trigger GCOV for kernel if this patch
is in by only setting the before mentioned flag.
Change-Id: I8aade309da2da62c4b3889bd84e4123ba8f182da
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/62999
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Rebase-Id: R4c238f707f1db600f188ae83426336753992b7be
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Change-Id: If544ad6382b8321f8c5e94e0a8a7679d36c48b67
Reviewed-on: http://git-master/r/52239
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/62044
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Rebase-Id: Rc0e69778b981cba9a5dfd1b55ece16d5f43cf22e
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The clock control apis can be sleepable in tegra platform as
spi require frequency/voltage boosting.
Moving the clock controls api out of spin lock context.
bug 874841
Reviewed-on: http://git-master/r/56869
(cherry picked from commit b316a4e4fd82f1af9af920079119c56bf271c3be)
Change-Id: I8fc824de02cb3af54f6331efa0500c79e806bb03
Reviewed-on: http://git-master/r/57315
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R601bd69547ec2612f42d24da29a2f8a5d3fb1fb8
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Avoiding the suspend of the system if the spi transfer is
in progress for current transfer queue.
bug 864987
Reviewed-on: http://git-master/r/56599
(cherry picked from commit 0ba8ed371f2937a095752a0edbc15ed75664644a)
Change-Id: Ife7ae8a7d66a66d047ee2c8829d16017571b4d58
Reviewed-on: http://git-master/r/57001
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Rc66d6c7ae51ea6709d5e47331fef30c87029b343
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Exporting with GPL flag of the api spi_tegra_register_callback()
for registering for callback.
Original-Change-Id: Ic3cbbca226071002824f1b6089dc2ccec796cc07
Reviewed-on: http://git-master/r/49663
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R0c7ce298c123e380398c512effe0b6b20685fdd9
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Providing the different clock source option through platform data
to select best clock source based on required interface frequency.
bug 851642
Original-Change-Id: I18bf817b63cf1afac7db3969f266cc5fcaeee81e
Reviewed-on: http://git-master/r/41226
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Ra4e4573414ef2c4e72cdcb4cd5625e242cfb4ec6
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- Initialized the read_words value.
- (tspi->irq < 0) is not valid
because tspi->irq is unsigned value.
Reviewed-on: http://git-master/r/37868
(cherry picked from commit 4c0d22c83294ca081e90f588fdcb67fdc54fff23)
Original-Change-Id: Ic37df9d29e305699abeda1f8b8aa48b7fcd9b394
Reviewed-on: http://git-master/r/39583
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R8e088031295c334cf3026ee8a49738605b7fcf7f
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Change SOC conditionals to make them more forward-looking.
Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Ra0885f203904e0bd4bdd06c23b6aa7e03e7ec3bc
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By changing the dma allocation API to take the client name, it is easy
to track who is allocated the DMA channels when we run out of the
DMA channels.
Original-Change-Id: I016011cfd74089fed0da1bc0f121800017ce124a
Reviewed-on: http://git-master/r/28031
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I048bcb87f95ee6d8ad2fdce993a1758dc5071666
Rebase-Id: R29b9645ecbe209f571018c6e707bfdd9cd65ad5d
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When spi device calls the setup, the interface to that device
should be configured immediately. For this, it is required
to configure controller in setup call.
Original-Change-Id: I77795c476729fe7403529a45cdf99d5732ad0784
Reviewed-on: http://git-master/r/27607
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Original-Change-Id: I9a3f200dbea7d8cc057bb5413e790c28578e77cf
Rebase-Id: R7e9907797bf951a9f7b9b6db0a440b3796dc977c
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Adding spi slave driver for tegra socs.
The interface is same as the master spi but spi controller
will work in slave mode.
Original-Change-Id: Ibf00e9d16e7bac675dd431a35e866bf56030f033
Reviewed-on: http://git-master/r/27605
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: I1d770ae52371bae5869b03c69f86c06fb9cdc9fa
Rebase-Id: R6d1726c2b899437eed4dd8681403ed0f63f53265
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Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496
Reviewed-on: http://git-master/r/27559
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1
Rebase-Id: R61892d66dc9efd02f691a3ac75f92dd5d6d17078
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Supporting the hw based CS to communicate to spi device. This
provides the constraints in hold and setup time of CS before
clock start and clock ends.
The hw based CS can be selected if spi client provide the option
through the device controler data and only one transfer per
message is requested.
Original-Change-Id: I56d5e466361cb8b3710646e01494ddac46791ae4
Reviewed-on: http://git-master/r/23988
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: I52b1dcdefa199cd11ae7f838c61411a6268a2d32
Rebase-Id: Rd9f2c70e8c8551ea5ca6ce698a172ef00c08ca67
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Following are the fixes;
- Supportng half duplex.
- Only using SW based CS.
- Write to readback with command register does not work. Fixing issue.
- Using cpu based transfer for smaller size and dma based for larger size.
- reading proper transfer status after every transaction.
bug 791149
bug 791780
Original-Change-Id: I293b3f1b571276f5d8fe4ad4da67f827926e4b73
Reviewed-on: http://git-master/r/20581
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Rebase-Id: R29f88f7509bdb182f05916ecf31e1090b1b9d017
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disable unstable packed spi mode
Original-Change-Id: I81a11a0f5dd9515ff1430ccfcc7d2ed7371e79b3
Reviewed-on: http://git-master/r/16105
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R010fbce5f63a377fa9661f3bdd89523c497989ec
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Enabled clocks at spi_setup
Fixed problem with endianness for 16 bit word size
Fixed issue with small packet size less than fifo depth
Fixed typo that enabled RX and TX by default
Integration from http://git-master/r/#change,14536
Original-Change-Id: I2cea3bdcb6a19780087671131a848095354105a3
Reviewed-on: http://git-master/r/15949
Reviewed-on: http://git-master/r/16048
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Ra7c9c381f2ae897d002853c9965252ba28dc28ac
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- DMA burst size can be set to 1, 4, or 8 depending on requested size
- PACKED MODE support
- When bits per word is 32, no endian conversion is needed; so use
memcpy to copy from client buf to dma buf or vice versa
- Do spi_complete operation in the last dma complete callback
- Reducing the loop-count from 500 to 50, thus making sure suspend is
not stuck.
bug 747979
bug 765062
Original-Change-Id: I67fe1405e1cda886e9229b26dff5ebd80fd67247
Reviewed-on: http://git-master/r/12799
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R34ee80275312587666359ed2e0e8dab468068daf
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for spi/slink, depending on transfer size,
burst size can be set to 1, 4, or 8.
bug 747979
Original-Change-Id: Ieae0285d374e7d0eb6c2c2e633f8cafbb2b51b3a
Reviewed-on: http://git-master/r/12076
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R366881cc8a4ba50cdd815b97f52b4e7d4dfb1ee6
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for spi/slink, set dma burst size based on
transfer size.
bug 747979
Original-Change-Id: I8c3c0a0410648a25190847590b9ac0304fb1105f
Reviewed-on: http://git-master/r/11752
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R63f68e541c427778a412c5f09e656fb18da5f05d
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To avoid running out of DMA channels, use the shared DMA channel
for all four Tegra spi controllers.
Change-Id: Iff644253cf7fae36aa2e42321a1ded35a728da4f
Signed-off-by: Colin Cross <ccross@android.com>
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Some SPI devices require a delay between the CS and when the clock
starts. Increase SS_SETUP to accommodate these devices.
Change-Id: I301e3583e70c722cadde5a9f91119881805dd3a5
Signed-off-by: Greg Meiste <w30289@motorola.com>
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