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path: root/drivers/usb/host/ehci-tegra.c
AgeCommit message (Collapse)Author
2011-09-18USB: irq: Remove IRQF_DISABLEDYong Zhang
This flag is a NOOP and can be removed now. Signed-off-by: Yong Zhang <yong.zhang0@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-03USB: EHCI: Support controllers with big endian capability regsJan Andersson
The two first HC capability registers (CAPLENGTH and HCIVERSION) are defined as one 8-bit and one 16-bit register. Most HC implementations have selected to treat these registers as part of a 32-bit register, giving the same layout for both big and small endian systems. This patch adds a new quirk, big_endian_capbase, to support controllers with big endian register interfaces that treat HCIVERSION and CAPLENGTH as individual registers. Signed-off-by: Jan Andersson <jan@gaisler.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-04-29USB: ehci: tegra: fix USB1 port reset issueJim Lin
Tegra USB1 port needs to issue Port Reset twice internally, otherwise it fails to enumerate devices attached to it Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Olof Johansson <olofj@chromium.org> [ squash two patches into one and minor style cleanups ] Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-03-11USB: ehci: tegra: Align DMA transfers to 32 bytesRobert Morell
The Tegra2 USB controller doesn't properly deal with misaligned DMA buffers, causing corruption. This is especially prevalent with USB network adapters, where skbuff alignment is often in the middle of a 4-byte dword. To avoid this, allocate a temporary buffer for the DMA if the provided buffer isn't sufficiently aligned. Signed-off-by: Robert Morell <rmorell@nvidia.com> Signed-off-by: Benoit Goby <benoit@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-03-11usb: host: Add EHCI driver for NVIDIA Tegra SoCsBenoit Goby
The Tegra 2 SoC has 3 EHCI compatible USB controllers. This patch adds the necessary glue to allow the ehci-hcd driver to work on Tegra 2 SoCs. The platform data is used to configure board-specific phy settings and to configure the operating mode, as one of the ports may be used as a otg port. For additional power saving, the driver supports powering down the phy on bus suspend when it is used, for example, to connect an internal device that use an out-of-band remote wakeup mechanism (e.g. a gpio). Signed-off-by: Benoit Goby <benoit@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>