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2018-08-24usb: dwc3: gadget: properly check ep cmdFelipe Balbi
The cmd argument we pass to dwc3_send_gadget_ep_cmd() could contain extra arguments embedded. When checking for StartTransfer command, we need to make sure to match only lower 4 bits which contain the actual command and ignore the rest. Reported-by: Janusz Dziedzic <januszx.dziedzic@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> (cherry picked from commit 5999914f227b20addf01297b3df24be6b4161f69)
2018-08-24MLK-16716 nvmem: imx-scu-ocotp do not read invalid addressPeng Fan
Fix: hexdump: /sys/bus/nvmem/devices/imx-ocotp0/nvmem: Input/output error Address space [272,543] is invalid address space on 8QXP, reading from SCU will get SC_ERR_PARAM. So ignore these words when reading fuse. BuildInfo: - SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF - U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-24MLK-16712 tty: serial: lpuart: keep per clock disabled during suspendFugang Duan
Keep per clock disabled during system suspend. BuildInfo: - SCFW 88456c73, IMX-MKIMAGE 06bc2767, ATF a438801 - U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g7953d47 Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16704-1: watchdog: imx8_wdt: add watchdog driver for i.mx8QM/QXPRobin Gong
This watchdog driver is a virtual driver in Linux and call ATF interface where call SCFW eventually. In SCFW, it's done by SCU timer tick instead of hardware watchdog.This is why we have to call ATF because such system resource owned by secure patition.Currently, booard reset happen if not ping this software watchdog in time in linux side, may change to partition reboot once SCFW support this feature in the future. BuildInfo: - SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb - U-Boot 2017.03-00097-gd7599cf Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16701 JPEG: add rum time pm supportFrank Li
Support run time pm Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Sandor Yu <sandor.yu@nxp.com>
2018-08-24MLK-16710 cpufreq: imx8mq: avoid duplicated OPP table initializationAnson Huang
On i.MX8MQ, since the OPP table is initialized in cpu-freq platform device register according to chip type, so no need to redo the OPP table initialization in cpu-freq driver, this patch adds check for OPP table initialization to avoid below warning during boot up: [ 1.468378] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 1501 [ 1.468388] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 1301 [ 1.468417] cpu cpu0: _of_add_opp_table_v1: Failed to add OPP 1300000000 [ 1.468425] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 1001 [ 1.468434] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 8001 [ 1.468443] cpu cpu0: _of_add_opp_table_v1: Failed to add OPP 800000000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-16705-1 soc: imx: pm-domains: add wakeup unit irqchip to manage wakeup ↵Anson Huang
source For a resource enabled as wakeup source, its power needs to be kept on during suspend, this is required by SCFW to support wakeup ability for a resource. This patch adds a virtual wakeup unit to support this function, wakeup unit is registered as a irqchip being a child of GIC, if a resource can be enabled as a wakeup source, needs to pass its irq number in device tree power domain node using "wakeup-irq = <x>" format, as power domain driver needs to map the irq number to resource ID, also needs to assign its interrupt parent to wakeup unit instead of GIC. During suspend, when power domain driver intends to power off a resource, it will skip power off operation if the resource is enabled as wakeup source. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-16708 clk: imx: change the nand_usdhc_bus clock's sourceBai Ping
Change NAND_USDHC_BUS clock's source to SYS PLL1 266M. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-16688 driver: media: mxc_jpeg: Remove the unused function to kill the ↵Jason Liu
build warnnings The patch fixes the following build warnnings by removing unused function: drivers/media/platform/imx8/mxc-jpeg.c:228:13: warning: ‘print_output’ defined but not used [-Wunused-function] static void print_output(void *addr) ^~~~~~~~~~~~ This patch also does the minor clean up by removing some commented-out code Signed-off-by: Jason Liu <jason.hui.liu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2018-08-24MLK-16684-3 ata: imx: enable imx8qm sataRichard Zhu
enable sata on imx8qm. sata function is relied on the usage of pcie ports. BuildInfo: - SCFW 9559d5ec, IMX-MKIMAGE 06bc2767, ATF - U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f Reviewed-by: Frank Li <frank.li@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-16684-2 clk: imx: correct the pd of the sata phy pclkRichard Zhu
Correct the pd of the sata phy pclk. BuildInfo: - SCFW 9559d5ec, IMX-MKIMAGE 06bc2767, ATF - U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f Reviewed-by: Frank Li <frank.li@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-16645-4 JPEG: Encode: fix wrong use dma descriptor addressFrank Li
Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Sandor Yu <sandor.yu@nxp.com>
2018-08-24MLK-16645-3 JPEG: fixed crash caused by call dma_free_coherence in irqFrank Li
move dma_free_coherence function to buf_cleanup Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Sandor Yu <sandor.yu@nxp.com>
2018-08-24MLK-16645-1: clk: mx8qxp: correct JPEG clock sourceFrank Li
Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Sandor Yu <sandor.yu@nxp.com>
2018-08-24MLK-16671-4 - [i.MX8QXP/Malone]: Add vpu malone decoder driverZhou Peng-B04994
Only build malone for ARCH_MXC_ARM64 Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
2018-08-24MLK-16671-3 - [i.MX8QXP/Malone]: Add vpu malone decoder driverZhou Peng-B04994
Refine makefile to fix yocto build issue: Remove redundant space after -D and -I Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
2018-08-24MLK-16681-1 soc: imx: add speed grading check for i.MX8MQ different partsAnson Huang
i.MX8MQ has different parts like consumer, industrial and auto etc., different parts have different cpu-freq set-points, this patch adds fuse check to select correct cpu-freq set-points for each part. The default dtb has all set-points available, then kernel will check fuse to disable those unused set-points, definition as below: OCOTP offset 0x440, bit [7:6] '00' - Consumer 0C to 95C '01' - Ext. Consumer -20C to 105C '10' - Industrial -40C to 105C '11' - Automotive -40C to 125C cpu-freq set-points definition as below (datasheet Rev-E): Normal Over-Drive Consumer 1GHz@0.9V 1.5GHz@1V Industrial 800MHz@0.9V 1.3GHz@1V Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-16671-2 - [i.MX8QXP/Malone]: Add vpu malone decoder driverZhou Peng-B04994
Add vpu module in device tree and makefile Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
2018-08-24MLK-16676-3 soc: imx: pm-domains: add debug console power managementAnson Huang
On i.MX8QM/i.MX8QXP, when "no_console_suspend" is added, need to keep debug uart power on for debug message output, support this case by reading debug uart resource from dtb and checking console suspend settings. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16676-1 soc: imx: pm-domains: support multiple early_power_on resourceAnson Huang
On i.MX8QM/i.MX8QXP, there could be multiple resources need to be powered on earlier after resume, current variable of index could be reset for different power domain nodes and cause resource id overwrite issue, fix the array index type to support multiple early power on case. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16671-1 - [i.MX8QXP/Malone]: Add vpu malone decoder driverZhou Peng-B04994
Integrate amphion release kernel functions Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
2018-08-24MLK-16502 - [i.MX8MQ/Hantro]: Implement dynamic clock adjustement in high ↵Zhou Peng-B04994
temperature Register thermal notifier and implment dynamic clock - One module parameter is added to enable or disable dynamic clock: 'hantro_dynamic_clock' Default, dynamic clock is disabled - One module parameter is added to adjust ratio: 'hantro_clock_ratio' Default, decrease to 1/2 clock when receiving hot event Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
2018-08-24MA-10480 Make CONFIG_I2C_IMX to depend on CONFIG_ARCH_MXC_ARM64guoyin.chen
imx8mscale evk uses the i2c imx driver to control the pfuze driver otherwise pfuze driver wont be probed with I2C_IMX Change-Id: Iaeacde58a4cbe34a3d18cb16814d2334c74c2b79 (cherry-picked from commit ad7200824fa740a1fe9d418d3f949ff97b083bdf) Signed-off-by: guoyin.chen <guoyin.chen@nxp.com>
2018-08-24MLK-16576 usb: phy: mxs: set hold_ring_off for USB2 PLL power upLi Jun
USB2 PLL use ring VCO, when the PLL power up, the ring VCO’s supply also ramp up. There is a possibility that the ring VCO start oscillation at multi nodes in this phase, especially for VCO which has many stages, then the multiwave will kept until PLL power down. Hold_ring_off(bit11) can force the VCO in one determined state when VCO supply start ramp up, to avoid this multiwave issue. Per IC design's suggestion it's better this bit can be off from 25us after pll power up to 25us before USB TX/RX. Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> (cherry picked from commit a094377f04c9ed2c8e702ee7bfab843caa03eb96)
2018-08-24MLK-16606-1 clk: imx8qm: add M4 I2C clocksDong Aisheng
There're two M4 I2C instances in MX8QM. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2018-08-24MLK-16595 rpmsg: imx: enable multi-core string demoRichard Zhu
Because that there are two M4 cores on iMX8QM. Enable the multi-core string echo support. BuildInfo: - SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0 - U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c Reviewed-by: Frank Li <frank.li@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-16597: hdmi: Fix kernel dump issueSandor Yu
Kernel will dump when CONFIG_CC_STACKPROTECTOR_STRONG is enable. [ 2.675537] CDN_API_HDMITX_Set_Mode_blocking ret = 0 [ 2.675550] Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in: ffff000008ad5a50 [ 2.675550] [ 2.675557] CPU: 2 PID: 1553 Comm: kworker/2:2 Not tainted 4.9.56-641868-gead64f8 #12 [ 2.675559] Hardware name: Freescale i.MX8MQ EVK (DT) [ 2.675576] Workqueue: events deferred_probe_work_func [ 2.675578] Call trace: [ 2.675587] [<ffff00000808974c>] dump_backtrace+0x0/0x1d0 [ 2.675594] [<ffff000008089930>] show_stack+0x14/0x1c [ 2.675602] [<ffff000008401650>] dump_stack+0x8c/0xac [ 2.675609] [<ffff0000081b0b24>] panic+0x13c/0x2a8 [ 2.675617] [<ffff0000080c5ec4>] print_tainted+0x0/0xa4 [ 2.675624] [<ffff000008ad5a50>] Afe_write+0x0/0x50 [ 2.675632] [<ffff00000849aff0>] hdmi_init.constprop.3+0x188/0x1d0 [ 2.675638] [<ffff00000849b264>] imx_hdmi_probe+0x22c/0x2ac [ 2.675645] [<ffff0000086d543c>] platform_drv_probe+0x50/0xc8 [ 2.675650] [<ffff0000086d3530>] driver_probe_device+0x218/0x2b8 [ 2.675655] [<ffff0000086d3710>] __device_attach_driver+0x98/0xe8 [ 2.675660] [<ffff0000086d126c>] bus_for_each_drv+0x60/0xb0 [ 2.675665] [<ffff0000086d31bc>] __device_attach+0xd4/0x128 [ 2.675669] [<ffff0000086d38f8>] device_initial_probe+0x10/0x18 [ 2.675674] [<ffff0000086d275c>] bus_probe_device+0x90/0x98 [ 2.675679] [<ffff0000086d2bf0>] deferred_probe_work_func+0x7c/0xb0 [ 2.675685] [<ffff0000080e1580>] process_one_work+0x144/0x434 [ 2.675690] [<ffff0000080e1ec4>] worker_thread+0x200/0x4a4 [ 2.675696] [<ffff0000080e81f0>] kthread+0xf0/0x104 [ 2.675701] [<ffff000008082e80>] ret_from_fork+0x10/0x50 It is cause by array variable access exceed. Fixed it with correct array size. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-08-24MLK-16600 gpu: imx: dpu: common: Initialize pixel link in resume() only if ↵Liu Ying
necessary We should initialize pixel link in resume() for DPUv2 which has pixel link quirks, but not for DPUv1 which hasn't the quirks. Fixes: 0d7fa2aa1a9f ("MLK-16581-6 gpu: imx: dpu: Add system power management support") Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16586-3 rpmsg: imx: enable multi-core rpmsgRichard Zhu
- Init multi-core mu power and clk. - enable the multi-core rpmsg support BuildInfo: - SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0 - U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com> Tested-by: Andy Duan <fugang.duan@nxp.com>
2018-08-24MLK-16586-1 clk: imx8qm: add the cm41 ipg clkRichard Zhu
Add the cm41 ipg clk BuildInfo: - SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0 - U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Tested-by: Andy Duan <fugang.duan@nxp.com>
2018-08-24MLK16557 soc:imx8qm/imx8qx - Resources can request low power idle mode only ↵Ranjani Vaidyanathan
when runtime-pm is enabled. Some drivers use runtime PM callbacks during suspend/resume also and this in turn results in SCFW calls requesting the resource to enter low power idle instead OFF state. This patch fixes this issue by ensuring that low power IDLE request is only valid when runtime PM is enabled. Runtime PM is disabled when the system is entering suspend state. BuildInfo: SCFW 7a725203, IMX-MKIMAGE ee6adff0, ATF 0 Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MGS-2717-2 [#ccc] Error message printed on board that didn't support gpu ↵Yuchou Gan
govern when rmmod galcore When rmmod galcore.ko on boards that didn't support gpu govern, some error message will be printed on console, do something to prevent this. Date: Oct 16, 2017 Signed-off-by: Yuchou Ganyuchou.gan@nxp.com Reviewed-by: Xianzhong xianzhong.li@nxp.com Reviewed-by: Prabhu Sundararaj prabhu.sundararaj@nxp.com
2018-08-24MLK-16581-7 drm/imx: ldb: Add system power management supportLiu Ying
This patch adds system power management support for imx-ldb drm driver by proper PHY power/exit/init handling where necessary and pixel link re-initialization in the resume operation. The driver depends on the imx-drm core driver to handle ldb bridge power management operations. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16581-6 gpu: imx: dpu: Add system power management supportLiu Ying
The dpu core driver currently depends on the client drivers to do suspend operations to leave dpu a cleaned up state machine status before the system enters sleep mode. When the system resumes, the dpu core driver resume operation will re-initialize the machine state by enabling intsteer lines, re-initializing pixel links and re-initializing dpu sub-units. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16581-5 gpu: imx: dpu: common: Add helper dpu_intsteer_enable_lines() ↵Liu Ying
support This patch adds helper dpu_intsteer_enable_lines() support so that users may enable intsteer lines with one function call. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16581-4 gpu: imx: framegen: Get pll & pixel clock rates before setting ↵Liu Ying
their rates Due to i.MX8 clock issue, we need to get pll and pixel clock rates before setting their rates when system resumes back from PM sleep mode, otherwise, we'll fail to set the clock rates. So, this is a workaround and it can be removed when the clock issue is properly fixed. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16581-3 drm/imx: ldb: Get bypass & pixel clock rates before setting ↵Liu Ying
their rates Due to i.MX8 clock issue, we need to get bypass and pixel clock rates before setting their rates when system resumes back from PM sleep mode, otherwise, we'll fail to set the clock rates. So, this is a workaround and it can be removed when the clock issue is properly fixed. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16581-2 phy: mixel-lvds-combo: Get PHY clock rate before setting it's rateLiu Ying
Due to i.MX8 clock issue, we need to get PHY clock rate before setting it's rate when system resumes back from PM sleep mode, otherwise, we'll fail to set the clock rate. So, this is a workaround and it can be removed when the clock issue is properly fixed. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-16581-1 phy: mixel-lvds: Get PHY clock rate before setting it's rateLiu Ying
Due to i.MX8 clock issue, we need to get PHY clock rate before setting it's rate when system resumes back from PM sleep mode, otherwise, we'll fail to set the clock rate. So, this is a workaround and it can be removed when the clock issue is properly fixed. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24drm: Take ownership of the dmabuf->obj when exportingChris Wilson
Currently the reference for the dmabuf->obj is incremented for the dmabuf in drm_gem_prime_handle_to_fd() (at the high level userspace interface), but is released in drm_gem_dmabuf_release() (the lowlevel handler). Improve the symmetry of the dmabuf->obj ownership by acquiring the reference in drm_gem_dmabuf_export(). This makes it easier to use the prime functions directly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Update kerneldoc.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161207214527.22533-1-chris@chris-wilson.co.uk Cherry-picked 72a93e8dd52c9feea42f1258d555e6070680a347 from https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/ This is required by VSI to implement DRM support. Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com> Acked-by: Prabhu Sundararaj <prabhu.sundararaj@nxp.com>
2018-08-24MLK-16571-4: lpspi: support nor chip access from lpspiHan Xu
i.MX8QM connects the AT45DB041E nor chip to lpspi, change the lpspi driver to request irq before bitbang starts, add both ipg and per clock for i.MX8QM and add gpio cs to keep the cs asserted during nor access. BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0 Reviewed-by: Pan Gao <pandy.gao@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com>
2018-08-24MLK-16571-1: Kconfig: arm64: enable lpspi for MXC_ARM64Han Xu
enable the lpspi config for arm64 in Kconfig BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0 Reviewed-by: Pan Gao <pandy.gao@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com>
2018-08-24gpu-viv: Fix build on imx6Leonard Crestez
Fixes: 83a60229d139 ("MGS-3214 gpu-viv: integrate 6.2.4 driver") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2018-08-24MGS-3214 gpu-viv: integrate 6.2.4 driverXianzhong
add dmabuf/gem feature through drm galcore, include more bug-fixing in gpu kernel driver. Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MLK-16585 net: fec: fixup: correct i.MX8QXP MAC address fuse mappingFugang Duan
i.MX8QXP has different fuse address with i.MX8QM, correct i.MX8QXP MAC fuse word address. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2018-08-24MGS-2717-2 [#ccc] GPU Scaling governorYuchou Gan
Implement the gpu scaling governor so that you can switch the clock rate in user space like this: echo "overdrive" > /sys/bus/platform/drivers/galcore/gpu_mode echo "nominal" > /sys/bus/platform/drivers/galcore/gpu_mode echo "underdrive" > /sys/bus/platform/drivers/galcore/gpu_mode or cat /sys/bus/platform/drivers/galcore/gpu_mode to get the supported modes/frequency and current running mode. Date: Oct 11, 2017 Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com> Reviewed-by: Xianzhong <xianzhong.li@nxp.com> Reviewed-by: Prabhu Sundararaj <prabhu.sundararaj@nxp.com>
2018-08-24MLK-16559 flexcan: make MB mode be able to receive extend frameDong Aisheng
By default Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits which will result in MB can't receive extend frames with random IDs. (CAN_CTRL2[EACEN] is 0) Let's enables the comparison of both Rx Mailbox filter’s IDE and RTR bit according to mask bits. Since mask bits are all set to 0 currently, it makes MB can receive both standard and extend frames. BuildInfo: - SCFW d0458f9f, IMX-MKIMAGE 1c6fc7d8, ATF a438801 - U-Boot 2017.03-00046-g32bb4c7 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2018-08-24MLK-16546-2 soc: imx: pm-domains: support early power on resource after resumeAnson Huang
On i.MX8QM/8QXP, for some resources which act as irq chip etc., they need to be powered on earlier than device resume phase, as they need to access registers, common power domain resume is too late, so add syscore resume callback in pm domain driver, for those resources with "early_power_on" property set, they will be powered on at syscore resume phase, by default, it supports 10 resources, and can be increased if needed. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13946-2: hdp: add i2s clock for imx8qm hdmi audioShengjiu Wang
hdmi audio need to enable the i2s clock and i2s_bypass clock Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2018-08-24MLK-13946-1: clk: imx8qm: fix the definition of HDMI I2S clockShengjiu Wang
The resource id of HDMI I2S clock is SC_R_HDMI_I2S, and SAI HDMITX and HDMIRX clock need FUNCTION_NAME paremeter. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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