| Age | Commit message (Collapse) | Author |
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1) In the interrupt handler, we access sync interrupt
control registers 2 times, and each time with spin
lock being held and then released, which may cause
potential racing on the registers. We see that
as long as the racing happens with two displays
enabled on the same IPU, one IPU display channel
will lose EOF interrupt and it makes its fb's pan
display ioctrl fail with timeout. This patch changes
to hold the spin lock one time for the whole irq
handler, as the handler should return quickly.
Holding and releasing the spin lock unnecessarily
may bring performance penalty as well.
2) We do not need to use spin_lock_irqsave() and
spin_unlock_irqrestore() in the interrupt handler,
as we are already in the hard irq context. Using
spin_lock() and spin_unlock() is enough to protect
the registers.
3) Clear an interrupt control bit as soon as its related
handler finishes.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c5d3731fa0880a65efafb4826d3722aacb79edd5)
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As we define ERR interrupt with 0 irq resource id and SYNC
interrupt with 1 irq resource id in platform-imx_ipuv3.c,
we wrongly assign them in IPUv3 driver.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 52c9fc323e0f72e53de6fe0c6f7012fe7adf14b4)
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In this patch:
1. Close audio PCM stream when video unblank and plugout event happens.
2. Set HDMI cable and blank state into HDMI core driver when
plug/unplug, blank/unblank events happens.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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In this patch, add support for:
1. Interface for HDMI audio to register PCM into HDMI core driver.
2. Interface for HDMI video driver to stop HDMI audio
3. Interface for HDMI video driver to inform the state of HDMI cable and
state of HDMI blank.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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add sys_close() to close opened file in cooling device
Signed-off-by: Rong Dian <b38775@freescale.com>
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-Update gpu driver to check the SoC temperature, if the thermal_hot flag
is set by thermal driver. GPU3D clock will be slown down to the minimum
value, the clock will be recovery when the flag is cleared by thermal driver.
-This patch depends on ENGR00220848, without it, kernel build can't pass.
Signed-off-by: Loren HUANG <b02279@freescale.com>
Acked-by: Lily Zhang
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clear thermal hot variable in cooling device when thermal temperature
falls then to get out of THERMAL_TRIP_HOT state
Signed-off-by: Rong Dian <b38775@freescale.com>
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Bootup Android without HDMI cable plugin, then plugin HDMI cable,
video mode in /sys/class/graphics/fb0/mode not same as actually
HDMI work video mode.
The root cause is in video mode point to one of video mode in
original video modelist, but the modelist will be updated when
HDMI cable plug to new monitor.
If HDMI original worked video mode can work on new monitor,
the HDMI and framebuffer will not updated, so HDMI actually
work mode not same as /sys/class/graphics/fb0/mode
Updated fbi mode pointer even if video mode no changed
in case moselist is updated, the issue will fixed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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return error number when set camera change mode fail, if not the
driver may continue to setup the video processing with wrong parameter.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Add V4L2 support -- driver part.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Set correct PITCH (aka, stride) for AS, PS, Output buffer.
This is needed for V4L2.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Replace BUG macro with error message
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Avoid release resource twice when timeout happen.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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At pc sends suspend/resume case, the udc_controller->usb_state should
keep unchange during the suspend/resume process, at former code, the
fsl_udc_resume set udc_controller->usb_state to USB_STATE_ATTACHED
unconditionally. In fact, USB_STATE_ATTACHED stands for initial state
and should be set when we try to run controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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- invalid data preparation is a reasonable path, so no need to set to
WARNING level, change it to DEBUG level.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Move spin_unlock_irqrestore to avoid calling mutex at atomic
environment, as dr_wake_up_enable will call mutex_lock
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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IPU: Clean up dead code
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
3.1 Writing command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~11MB/s (w) | ~5MB/s (w) | ~11MB/s (w) |
| | ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~5MB/s (w) | ~9MB/s (w) |
| | ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------
Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 67c2bd5edef363412a074e9b4130b5207dac8a7f)
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Disable LDB DI clock when suspend.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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EDID read will failed sometimes on some boards.
Read EDID twice if first one failed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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If we use the late_initcall(), then there is a time slot between
the exit of early uart console and the real console:
-->late_initcall(mxc_early_uart_console_disable)
......
-->imx_startup()
In this time slot, the clock will be closed, so the log printed during
the time slot is buffered, this is why we can not see the NFS's log.
Change the late_initcall() to late_initcall_sync() which eliminates the
time slot.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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export thermal hot variable for GPU
Signed-off-by: Rong Dian <b38775@freescale.com>
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1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
Signed-off-by: Rong Dian <b38775@freescale.com>
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Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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If this timeout is too small, it can't meet the require of some large
frame such as 2592x1944 and 1080p, and the IDMAC maybe in a chaotic
state, so at last access some invalid space caused the system hang.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Add flush_work_sync and cancel_work_sync at the overlay stop to
prevent moving data by DMA even when the space of those data address
is freed.
Signed-off-by: Yuxi Sun <b36102@freescale.com
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There is a limitation on mx6 phy low power flow. During phy enter low power mode
and out of low power mode with OWIE bit active,there will be abnormal usb wakeup
interrupt happen. So we should clear OWIE bit before phy out of low power mode.
Signed-off-by: make shi <b15407@freescale.com>
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When use ASRC ideal ratio mode for convert, PAIR C can't work properly.
However, when use PAIR C for internal ratio mode or non ratio mode
convert, it can work properly.
In this patch, Use PAIR B for 6 channel convert as a workaround.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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When use no ideal-ratio mode for ESAI playback, CPU should provide
accurate clock for input clock, which means input clock should be
divided by input sample rate. However, all our clock is from 24M crystal
and if the input sample rate equal to 44.1k or so, CPU can't provide
these clock.
In this patch, use ideal ratio mode thus CPU need not provide accurate
clock which can be divided by 44.1k.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Channel swap caused by 2 reason:
1. To avoid ASRC underflow error, ASRC driver would prefill ASRC input
FIFO with 160 samples. However, 160 can't be divided by 6. In this case,
channel data miss alignment. In this patch, prefill ASRC input
FIFO with 120, which can be divided by 2,4,6,8.
2. While start P2P playback, ESAI driver would first start SDMA, then
ASRC, and last ESAI. While start ESAI, the data is not ready, thus ESAI
underrun would happens and channel data miss alignment. In this patch,
delay 1 ms between ASRC's start and ESAI's start.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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pdata->lowpower may be accessed at two drivers together, assumed
the situation that host/device set phy to low power mode but
still not set the flag lowpower, at this time the wakeup occurs, as
the flag lowpower is still not set, the interrupt will be infinite loop
as no one will serve it.
This commit is for driver code and add protect at driver.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Currently, we support 2 cameras, which are relevant to
2 video devices respectively. This patch checks if video
device is opened to determine whether we need to power
down/on relevant camera when doing suspend/resume.
Also, this patch protects capture resources with busy
lock semaphore.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 874198b89a89aa6e792754a0a51c46084ed93d1a)
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Some TV support specific video mode that different with
CEA standard, and it's pixel clock not comply CEA standard.
But audio configuration paramter N and CTS should follow CEA standard.
So audio may not work in these specific video mode.
Filter video mode get from EDID, only keep standard CEA video mode
in the modelist.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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fix battery coulomb data for power down system ,define low battery
voltage for power down system is 3.42V
Signed-off-by: Rong Dian <b38775@freescale.com>
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Add back ground overlay support based on ipu device driver.
Default using this driver instead of prp_vf driver for back
ground overlay. when want using prp_vf back ground overlay,
unselect ipu deviece overlay drivers and choose to build
related driver as build-in.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Allocate DMA buffer from DMA zone, and the system can configure reserve dma
size through proc fs file under /proc/sys/vm/lowmem_reserve_ratio.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Allocate DMA buffer from DMA zone, and the system can configure reserve dma
size through proc fs file under /proc/sys/vm/lowmem_reserve_ratio.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Allocate DMA buffer from DMA zone, and the system can configure reserve dma zone
size through proc fs file under /proc/sys/vm/lowmem_reserve_ratio.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Early versions of this driver used a set of entropy generation parameters
inherited from QorIQ devices. Those parameters were a hardcoded set
based upon internally-suggested values, and worked well on QorIQ. However,
for certain mx6 devices, oscillator values were found to be exceeding
the upper limit, and so RNG instantiation was failing in those cases.
This code improves initialization by (a) making sure the oscillator
divider is set to a known value, and (b) converting the parameter selection
to a symbolic compiler-generated form, instead of using embedded
magic number constants.
The calculation is now based on the definition of RNG4_ENT_CLOCKS_SAMPLE,
which defaults to 1600 unless overridden by something. The lower limit
is then set as /4, and the upper limit set to *8.
Tested-by: Minnick Michael-B21710 <b21710@freescale.com>
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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fix Kconfig waring of defaults for choice values not supported
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Kernel dump when do wifi stress test with suspend and resume as below:
eth0: tx queue full!.
remove wake up source irq 103
PM: resume of devices complete after 348.934 msecs
Restarting tasks ... done.
------------[ cut here ]------------
WARNING: at net/sched/sch_generic.c:255 dev_watchdog+0x284/0x2a8()
NETDEV WATCHDOG: eth0 (fec): transmit queue 0 timed out
Modules linked in: ar6000
[<8004482c>] (unwind_backtrace+0x0/0xf8) from
[<80068cd0>] (warn_slowpath_common+0x4c/0x64)
[<80068cd0>] (warn_slowpath_common+0x4c/0x64)from
[<80068d7c>] (warn_slowpath_fmt+0x30/0x40)
[<80068d7c>] (warn_slowpath_fmt+0x30/0x40) from
[<803f0c50>] (dev_watchdog+0x284/0x2a8)
[<803f0c50>] (dev_watchdog+0x284/0x2a8) from
[<80074430>] (run_timer_softirq+0xec/0x214)
[<80074430>] (run_timer_softirq+0xec/0x214) from
[<8006e524>] (__do_softirq+0xac/0x140)
[<8006e524>] (__do_softirq+0xac/0x140) from
[<8006ea60>] (irq_exit+0x94/0x9c)
[<8006ea60>] (irq_exit+0x94/0x9c) from
[<80039240>] (do_local_timer+0x54/0x70)
[<80039240>] (do_local_timer+0x54/0x70) from
[<8003ea0c>] (__irq_svc+0x4c/0xe8)
Exception stack(0x80a2bf68 to 0x80a2bfb0)
bf60: 0000001f 80a3babc 80a2bfb0 00000000 80a2a000 80a7b8e4
bf80: 804befcc 80a3ee7c 1000406a 412fc09a 00000000 00000000 80a81440 80a2bfb0
bfa0: 8003fa64 8003fa68 60000013 ffffffff
[<8003ea0c>] (__irq_svc+0x4c/0xe8) from [<8003fa68>] (default_idle+0x24/0x28)
[<8003fa68>] (default_idle+0x24/0x28) from [<8003fc60>] (cpu_idle+0xbc/0xfc)
[<8003fc60>] (cpu_idle+0xbc/0xfc) from [<80008878>] (start_kernel+0x258/0x29c)
[<80008878>] (start_kernel+0x258/0x29c) from [<10008040>] (0x10008040)
---[ end trace 30671ac42e272c2d ]---
But ethernet and system still be alive. In sometime,the issue
will cause system hang like "nfs: server 10.192.242.179 not
responding, still trying".
The root cause is tx buffer descriptors are not cleaned when
ethernet resume back.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Show video to IPU DP/fb0 when bootup, the color space incorrect
It needs to set the correct SRM_MODE when enable DP.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Revert ENGR00212529 MX6x show video to fb0 when bootup,
the color space incorrect.
Update IPU DP CSC setting should not change the DP FG window's position setting,
it can be update when enabling IPU DP channel.
Otherwise, it will appear NFB4EOF_ERR and flip irq timeout errors.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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the original low memory killer only take care of system memory accounting,
but for so large shared memory occupy by GPU, and each process memory
killer account become unfair, very large 3D game will not killed firstly
if it going to background.
Add this account to let real large memory user get killed if going to background
eg, the "angry bird Space" will acquire 68,215,360 GPU memory for 1-6 toll-gate.
The test show it can quicker recovery from memory shortage situation,
since it's very like to be killed after add so much GPU memory for such 3D game.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Acked-by: Lily Zhang
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Add ipu device queue processing for overlay, and make it default.
This will instead prp_viewfinder work flow in the most user case.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Replace CSI_PRP_VF_MEM channel with CSI_MEM, then using ipu device
to do the processing or directly send to framebuffer if no processing
need to be perform.
Add the foreground overlay driver file name ipu_fg_overlay_sdc.c correspondding
to the former ipu_prp_vf_sdc.c
Discard the cam->vf_rotation parametter when uing the ipu device for processing
in the overlay, share the cam->rotation parametter with pp.
Signed-off-by: Yuxi sun <b36102@freescale.com>
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