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2015-01-15ENGR00300890-1 mtd: fix the build errorHuang Shijie
We may meet the built error: ------------------------------------------------------ drivers/built-in.o: In function `m25p_probe: clk-composite.c:(.text+0xed7b4): undefined reference to `spi_nor_scan drivers/built-in.o: In function `.LANCHOR1: clk-composite.c:(.data+0xe4a0): undefined reference to `spi_nor_ids make: *** [vmlinux] Error 1 ------------------------------------------------------ This error is caused by the missing dependency of SPI NOR framework. Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15serial: imx: disable the receiver ready interrupt for imx_stop_rxHuang Shijie
This patch disables the receiver ready interrupt for imx_stop_rx. It reduces the interrupt numbers when the uart is going to close or suspend. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-15serial: imx: remove the redundant codeHuang Shijie
In the imx_startup(), we will reset the uart port which will reset all the FIFOs, including the URXD. So the code to clear the RX FIFO is redundant. Just remove it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-15serial: imx: reset the uart port all the timeHuang Shijie
Current code resets the uart port only when it supports the irda mode. In actually, we also need to reset the uart port in the non-irda mode. A hang was caught in the following case: UART A transmits data to the other end. But the transmission maybe terminated. In some corner case, the TX FIFO maybe not empty. The kernel will hang at the imx_set_termios(): ............................................................ while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) barrier(); ............................................................ This patch resets the uart port all the time in the imx_startup(). And fix the hang. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-15serial: imx: Disable new features of autobaud detectionFabio Estevam
Bit 7 of UCR3 is described in the i.MX reference manuals (with the exception of i.MX1) as follows: ADNIMP: Autobaud Detection Not Improved-. Disables new features of autobaud detection (See Baud Rate Automatic Detection Protocol, for more details). 0 Autobaud detection new features selected 1 Keep old autobaud detection mechanism The "new features" mechanism occasionally cause the receiver to get out of sync and continuously produce received characters of '\xff'. In order to reproduce the problem: $ stty -F /dev/ttymxc0 19200 - Change the terminal baudrate to 19200 - Type in the console and it should look good - Change the terminal baudrate back to 115200 - Type 'b' in the console, then a stream of garbage characters is seen. Also rename the bit definition as per the reference manual. Tested on mx6q, mx6dl, mx6solo and mx53. Based on a patch from Eric Nelson for U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15serial: imx: Remove init() and exit() platform callbacksAlexander Shiyan
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15serial: imx: Use dev_name() for request_irq() to distinguish UARTsAlexander Shiyan
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15serial: imx: Use devm_ioremap_resource()Alexander Shiyan
Use devm_ioremap_resource() in order to make the code simpler and it gives proper codes on errors. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15serial: imx: always wake up the processes in the TX callbackHuang Shijie
The current code only wakes up the processes when the circle buffer has less data then the WAKEUP_CHARS. But sometimes, the circle buffer may has data more then the WAKEUP_CHARS, in such case, the processes will hang. This patch makes it always wakes up the processes in the TX callback. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-15mtd: nand: add "page" argument for read_subpage hookHuang Shijie
Add the "page" argument for the read_subpage hook. With this argument, the implementation of this hook could prints out more accurate information for debugging. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: gpmi: add gpmi support for imx6sxHuang Shijie
The gpmi's IP for imx6sx is nearly the same as the gpmi's IP for imx6q, except the following two new features: (1) the new BCH contoller has 62-BIT correcting ECC strength (The BCH for imx6q only has 40-BIT ECC strength). (2) add the hardware Randomizer support. This patch does the follow changes: (1) add a new macro GPMI_IS_MX6SX to represent the imx6sx's gpmi. (2) add a new macro GPMI_IS_MX6. We use this macro to initialize the same registers for both imx6sx and imx6q, and so on. (3) add a new gpmi_devdata instance, the gpmi_devdata_imx6sx, for imx6sx. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: gpmi: add gpmi_devdata{} to simplify the codeHuang Shijie
More and more chips use the GPMI controller, but these chips may use different version of the IPs for GPMI and BCH. Different IPs have different features, such as the BCH's maximum ECC strength: imx23/imx28 -- the BCH's maximum ECC strength is 20 imx6q -- the BCH's maximum ECC strength is 40 imx6sx -- the BCH's maximum ECC strength is 62 This patch does the following things: [1] add a new data structure, gpmi_devdata{}, to store the information for each IP. Besides the IP version, we store the following information: <1> BCH's maximum ECC strength. <2> the maximum chain delay in ns used by the EDO mode. but we may add more information in future. [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids. [3] simplify the code by using the ECC strength from gpmi_devdata, such as gpmi_check_ecc() and legacy_set_geometry(); [4] use the maximum chain delay to initialize the EDO mode, see gpmi_compute_edo_timing(). [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: gpmi: add subpage read supportHuang Shijie
1) Why add the subpage read support? The page size of the nand chip becomes larger and larger, the imx6 has to supports the 16K page or even bigger page. But sometimes, the upper layer only needs a small part of the page, such as 512 bytes or less. For example, ubiattach may only read 64 bytes per page. 2) We only enable the subpage read support when it meets the conditions: <1> the chip is imx6 (or later chips) which can supports large nand page. <2> the size of ECC parity is byte aligned. If the size of ECC parity is not byte aligned, the calling of NAND_CMD_RNDOUT will fail. 3) What does this patch do? This patch will fake a virtual small page for the subpage read, and call the gpmi_ecc_read_page() to do the real work. In order to fake a virtual small page, the patch changes the BCH registers and the bch_geometry{}. After the subpage read finished, we will restore them back. 4) Performace: 4.1) Tested with Toshiba TC58NVG2S0F(4096 + 224) with the following command: #ubiattach /dev/ubi_ctrl -m 4 The detail information of /dev/mtd4 shows below: -------------------------------------------------------------- #mtdinfo /dev/mtd4 mtd4 Name: test Type: nand Eraseblock size: 262144 bytes, 256.0 KiB Amount of eraseblocks: 1856 (486539264 bytes, 464.0 MiB) Minimum input/output unit size: 4096 bytes Sub-page size: 4096 bytes OOB size: 224 bytes Character device major/minor: 90:8 Bad blocks are allowed: true Device is writable: true -------------------------------------------------------------- 4.2) Before this patch: -------------------------------------------------------------- [ 94.530495] UBI: attaching mtd4 to ubi0 [ 98.928850] UBI: scanning is finished [ 98.953594] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0 [ 98.958562] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes [ 98.964076] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096 [ 98.969518] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192 [ 98.975128] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0 [ 98.979843] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128 [ 98.985878] UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 2024916145 [ 98.993635] UBI: available PEBs: 0, total reserved PEBs: 1856, PEBs reserved for bad PEB handling: 40 [ 99.001807] UBI: background thread "ubi_bgt0d" started, PID 831 -------------------------------------------------------------- The attach time is about 98.9 - 94.5 = 4.4s 4.3) After this patch: -------------------------------------------------------------- [ 286.464906] UBI: attaching mtd4 to ubi0 [ 289.186129] UBI: scanning is finished [ 289.211416] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0 [ 289.216360] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes [ 289.221858] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096 [ 289.227293] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192 [ 289.232878] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0 [ 289.237628] UBI: user volume: 0, internal volumes: 1, max. volumes count: 128 [ 289.243553] UBI: max/mean erase counter: 1/1, WL threshold: 4096, image sequence number: 2024916145 [ 289.251348] UBI: available PEBs: 1812, total reserved PEBs: 44, PEBs reserved for bad PEB handling: 40 [ 289.259417] UBI: background thread "ubi_bgt0d" started, PID 847 -------------------------------------------------------------- The attach time is about 289.18 - 286.46 = 2.7s 4.4) The conclusion: We achieve (4.4 - 2.7) / 4.4 = 38.6% faster in the ubiattach. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: gpmi: do not use the mtd->writesizeHuang Shijie
The nfc_geo->payload_size is equal to the mtd->writesize now, use the nfc_geo->payload_size to replace the mtd->writesize. This patch makes preparation for the gpmi's subpage read support. In the subpage support, the nfc_geo->payload_size maybe smaller then the mtd->writesize. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: spi-nor: Enable Dual and Quad SPI read transfers for s25sl032pGeert Uytterhoeven
Spansion s25sl032p supports Dual and Quad SPI transfers, hence set the SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: unify read opcode variants with ST SPI FSMBrian Norris
serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*Brian Norris
Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: add the copyright informationHuang Shijie
Add the copyright information for spi-nor.c and spi-nor.h. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: spi-nor: EXPORT symbols which could be used by module driversBrian Norris
Fix errors like this: ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined! ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: fsl-quadspi: fix __iomem annotationsBrian Norris
This corrects some sparse warnings: drivers/mtd/spi-nor/fsl-quadspi.c:281:31: warning: incorrect type in initializer (different address spaces) [sparse] drivers/mtd/spi-nor/fsl-quadspi.c:281:31: expected void *[noderef] <asn:2>base [sparse] drivers/mtd/spi-nor/fsl-quadspi.c:281:31: got void [noderef] <asn:2>*iobase [sparse] (etc.) Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: unify read opcode variants with ST SPI FSMBrian Norris
serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*Brian Norris
Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: Add Freescale QuadSPI driverHuang Shijie
(0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: spi-nor: add a helper to find the spi_device_idHuang Shijie
Add the spi_nor_match_id() to find the proper spi_device_id with the NOR flash's name in the spi_nor_ids table. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-01-15mtd: spi-nor: add the framework for SPI NORHuang Shijie
This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased to include additional m25p_ids[] entry] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: Revive dual read supportGeert Uytterhoeven
Commit 03e296f613affcc2671c1e86d8c25ecad867204e ("mtd: m25p80: use the SPI nor framework") accidentally removed support for Dual SPI read transfers. Add it back. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*Brian Norris
Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: use the SPI nor frameworkBrian Norris
Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: add Macronix mx66l1g55g 1Gbit SPI flashBrian Norris
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: add support for the Spansion s25fl008k chipKuninori Morimoto
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: Use positive logic to check JEDEC IDAxel Lin
For slightly better readability. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: delete non-required instances of include <linux/init.h>Paul Gortmaker
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> [Brian: dropped one incorrect hunk] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: Enable Dual SPI read transfers for s25fl256s1 and s25fl512sGeert Uytterhoeven
Spansion s25fl256s1 and s25fl512s support Dual SPI transfers, hence set the M25P80_DUAL_READ flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15mtd: m25p80: Add dual read supportGeert Uytterhoeven
Add support for Dual SPI read transfers, which is supported by some Spansion SPI FLASHes. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2015-01-15ENGR00269945: pinctrl: support pinctrl setting assertion via gpiosShawn Guo
It's pretty common that on some reference design or validation boards, one pin could be used by two devices on board, and the pin route is controlled by a GPIO. So to assert the pin for given device, not only the pinmux controller in SoC needs to be set up properly but also the GPIO needs to be pulled up/down. The patch adds support of a device tree property "pinctrl-assert-gpios" under client device node. It plays pretty much like a board level pin multiplexer, and steers the pin route by controlling the GPIOs. When client device has the property represent in its node, pinctrl device tree mapping function will firstly pull up/down the GPIOs to assert the pins for the device at board level. [shawn.guo: cherry-pick commit e5a718edab82 from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00269945: gpio: pca953x: add device_reset() callShawn Guo
The pca953x type of devices, e.g. max7310, may have a reset which needs to be handled to get the device start working. Add a device_reset() call for that, and defer the probe if the reset controller for that is not ready yet. [shawn.guo: cherry-pick commit e95dae89011e from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/gpio/gpio-pca953x.c
2015-01-15ENGR00269945: reset: build in CONFIG_RESET_GPIO by defaultShawn Guo
GPIO is widely used as the reset control for various devices. Let's build the support in by default. [shawn.guo: cherry-pick commit 795fcb3bc5bb from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00269945: reset: register gpio-reset driver in arch_initcallShawn Guo
It's a little bit late to register gpio-reset driver at module_init time, because gpio-reset provides reset control via gpio for other devices which are mostly probed at module_init time too. And it becomes even worse, when the gpio comes from IO expander on I2C bus, e.g. pca953x. In that case, gpio-reset needs to be ready before I2C bus driver which is generally ready at subsys_initcall time. Let's register gpio-reset driver in arch_initcall() to have it ready early enough. The defer probe mechanism is not used here, because a reset controller driver should be reasonably registered early than other devices. More importantly, defer probe doe not help in some nasty cases, e.g. the gpio-pca953x device itself needs a reset from gpio-reset driver start working. [shawn.guo: cherry-pick commit 7153f05108ef from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15reset: Add driver for gpio-controlled reset pinsPhilipp Zabel
This driver implements a reset controller device that toggle a gpio connected to a reset pin of a peripheral IC. The delay between assertion and de-assertion of the reset signal can be configured via device tree. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Pavel Machek <pavel@ucw.cz> [shawn.guo: cherry-pick commit 27e3604c82cb from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/reset/Makefile
2015-01-15ENGR00317981: gpu-viv: use runtime pm for VDDPU managementShawn Guo
On kernel 3.14, we use generic power domain for VDDPU management. In that case, GPU driver does not need to call regulator API to manage VDDPU anymore. Instead, it only needs to call runtime pm, which is already being used by the driver. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15drivercore: Bind/unbind power domain on probe/removeTomasz Figa
On a number of platforms, devices are part of controllable power domains, which need to be enabled before such devices can be accessed and may be powered down when the device is idle to save some power. This means that on systems that support power domain control using generic power domains subsystem, it is necessary to add device to its power domain before binding a driver to it and remove it from its power domain after its driver is unbound to make sure that an unused device does not affect power domain state. Since this is not limited to particular busses and specific archs/platforms, it is more convenient to do the above directly in driver core, just as done with pinctrl default configuration. This patch adds necessary code to really_probe() and __device_release_driver() to achieve this and maintain consistent stack-like ordering of operations happening when binding and unbinding a driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com> [on i.MX6 GK802] Tested-by: Philipp Zabel <philipp.zabel@gmail.com> Reviewed-by: Mark Brown <broonie@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> [shawn.guo: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/31029] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15base: power: Add generic OF-based power domain look-upTomasz Figa
This patch introduces generic code to perform power domain look-up using device tree and automatically bind devices to their power domains. Generic device tree binding is introduced to specify power domains of devices in their device tree nodes. Backwards compatibility with legacy Samsung-specific power domain bindings is provided, but for now the new code is not compiled when CONFIG_ARCH_EXYNOS is selected to avoid collision with legacy code. This will change as soon as Exynos power domain code gets converted to use the generic framework in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Mark Brown <broonie@linaro.org> Reviewed-by: Kevin Hilman <khilman@linaro.org> Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com> [on i.MX6 GK802] Tested-by: Philipp Zabel <philipp.zabel@gmail.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> [shawn.guo: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/31029] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00317981: regulator: anatop: force vddpu to use same voltage level as vddsocShawn Guo
The anatop on i.MX6 requires that vddpu use the same voltage level as vddsoc. It's a quick hacking to force the check whenever vddpu is about to be enabled. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15regulator: anatop: Remove checking control_reg in [set|get]_voltage_selAxel Lin
Remove checking control_reg in [set|get]_voltage_sel and then convert to use regulator_[set|get]_voltage_sel_regmap for [set|get]_voltage_sel callbacks. The anatop-reg-offset property is a required property rather than optional property. So the question is what is the meaning of setting anatop-reg-offset to 0? If 0 is a valid setting for anatop-reg-offset and it has special meaning, we had better document it in the binding document. Otherwise, remove the testing for control_reg in the driver. No anatop voltage regulator node in the dts files set anatop-reg-offset to 0. So I think it's safe to remove testing if control_reg is 0. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> [shawn.guo: cherry-pick commit 114c5748d540 from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15regulator: anatop: Add bypass support to digital LDOsPhilipp Zabel
The ARM, PU, and SOC LDOs in the i.MX6 PMU can operate in bypass mode. This allows to use external switching regulators for cpu voltage scaling. Since bypass and power gating modes are not configured with their own bits, but via the voltage target bitfield, store bypass state to be restored when reenabling the regulator. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> [shawn.guo: cherry-pick commit d38018f2019c from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15regulator: anatop: Add power gating support to digital LDOsPhilipp Zabel
The ARM, PU, and SOC LDOs in the i.MX6 PMU can completely gate their power output. Since power gating is configured by writing zero to the voltage target bitfield,, store a copy of the voltage selector to be restored when reenabling the regulator. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> [shawn.guo: cherry-pick commit 605ebd35f059 from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00317981: media: mxc_pxp_v4l2: change __s32 to __u32Shawn Guo
Commit f90580ca0133 ([media] videodev2: Set vb2_rect's width and height as unsigned) changes v4l2_rect's width and height from __s32 to __u32, and thus we see the build error below. CC drivers/media/platform/mxc/output/mxc_pxp_v4l2.o drivers/media/platform/mxc/output/mxc_pxp_v4l2.c: In function ‘pxp_try_fmt_output_overlay’: drivers/media/platform/mxc/output/mxc_pxp_v4l2.c:605:16: warning: comparison of distinct pointer types lacks a cast [enabled by default] drivers/media/platform/mxc/output/mxc_pxp_v4l2.c:607:17: warning: comparison of distinct pointer types lacks a cast [enabled by default] Fix the error by changing __s32 to __u32. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00317981: media: forward mxc video output drivers to 3.14 kernelShawn Guo
Forward imx_3.10.y mxc video output drivers to 3.14 kernel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00268508 backlight:Correct the setting for bd props.fb_blankLiu Ying
The patch of "ENGR00264855 backlight: Support backlight shared by multiple fbs" doesn't consider that bd->props.fb_blank could be shared by several framebuffers which use the same backlight device. This causes the pwm backlight wrongly check the fb blank status. This patch corrects the setting for the fb blank status by considering all the framebuffers in question to fix the issue. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 68b97d114629f22f64b3d8c14d0a0b7d07d6ebb2) [shawn.guo: cherry-pick commit 8a03a96fba08 from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2015-01-15ENGR00264855 backlight: Support backlight shared by multiple fbsLiu Ying
One backlight device may shared by multiple framebuffers. We don't hope blanking one of the framebuffers may turn the backlight off for all the other framebuffers, since they are likely active to show display content. This patch adds logic to record each framebuffer's backlight usage to determine the backlight device use count and whether the backlight should be turned on or off. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 37cbf741e4dff1f757f3ade6bb861d9a2af70693) [shawn.guo: cherry-pick commit d62e7e8a788b from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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