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2020-01-23MLK-23258-3 dts: Fix PCIE suspend/resume issueRanjani Vaidyanathan
Fix the parent-child power domain dependency to handle different PCIE usecases. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-12-23LF-580 dt-bindings: imx: correct i2c4/uart1 clocks IDFugang Duan
Current i2c4/uart1 clocks ID have conflict with pwm2/pwm3, correct them. Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-21MLK-22998-1 dt-bindings: Update SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit 6dcd0242ae Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-11-08MLK-22934-2: clk: imx8qxp: Remove unused audio clockShengjiu Wang
Remove below audio clocks from clk tree. IMX8QXP_ACM_AUD_CLK0_CLK IMX8QXP_ACM_AUD_CLK1_CLK, IMX8QXP_ACM_ASRC0_MUX_CLK_SEL IMX8QXP_ACM_ASRC0_MUX_CLK_CLK IMX8QXP_ACM_ASRC1_MUX_CLK_CLK IMX8QXP_ACM_ASRC1_MUX_CLK_SEL There are no these clocks physically. which are added wrongly before, so remove them. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-08MLK-22934-1: clk: imx8qm: Remove unused audio clockShengjiu Wang
Remove below audio clocks from clk tree. IMX8QM_ACM_AUD_CLK0_CLK IMX8QM_ACM_AUD_CLK1_CLK, IMX8QM_ACM_ASRC1_MUX_CLK_CLK IMX8QM_ACM_ASRC1_MUX_CLK_SEL There are no these clocks physically. which are added wrongly before, so remove them. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-07-17MLK-22265 dt-bindings: pinctrl: imx8mm: Update head fileAnson Huang
Update i.MX8MM pinctrl head file according to reference manual Rev.1, 03/2019. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2019-06-25MLK-21963-1 reset: Add driver for dispmix resetFancy Fang
This is an reset driver to implement a reset controller device DISPMIX on IMX8MM and IMX8MN platforms. Dispmix reset is used to reset or enable related buses and clks for the submodules in DISPMIX. All the dispmix resets are divided into three subgroups: sft_rstn, clk_en and mipi_rst, and each of them contains several reset lines to control several different modules on and off in DISPMIX which doesn't require the standard reset flow, but only line assert and deassert operations. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2019-06-04MLK-21700-3 imx8mm: Switch to imx8m_clk_compositeLeonard Crestez
This is a large change but realigns us with upstream is useful and make git diff useful. This was already done on imx8mq after that SOC was upstreamed. Mixing dts and driver changes is intentional because changes only compile together. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> (cherry picked from commit 29845d2ebf6708ef87213328a4ce0f29cef7722a)
2019-05-27MLK-21823-1 dt-bindings: add i.MX8MN clock and pin headerBai Ping
Add i.MX8MN clock and pin definition. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-04-08MLK-21393 soc: imx: update SCFW APIAnson Huang
This patch updates SCFW API to v1.7, based on below commit: 252281d48647 ("SCF-105: Update wiki.") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-03-11MLK-21051 dt-bindings: pinctrl: Sync SCFW header to commit ef4a5057Leonard Crestez
Replace manually added pads with defines from SCFW export package. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-03-11MLK-20958-1 imx8: Sync SCFW API to v1.4Leonard Crestez
Many whitespace and formatting changes were skipped Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-03-05MLK-20718-1: clk: imx8qm: Add DSI phy_ref clockRobert Chiras
Add the missing clocks for the DSI PHY_REF: IMX8QM_MIPI0_DSI_PHY_CLK and IMX8QM_MIPI1_DSI_PHY_CLK. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-15MLK-20930-1 arm64: dts: freescale: update resource IDAnson Huang
Update resource ID table to SCFW commit: 004247e14afc ("SCF-341 Fix bug in setting large slice clock divider") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-02-12MLK-20899 soc: imx: update SCFW APIsAnson Huang
Update SCFW APIs to SCFW commit: 5c03342369e8 ("SCF-105: Change links in wiki index.") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-20769-01 clk: imx: Add sim hsio clock for imx8mmJacky Bai
For the sim_hsio clock, it is used by the HSIO mix. previously, we keep this clock gate always-on, and don't expose it into linux. In order to save power, we need to runtime enable/disable this clock. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-02-12MLK-20588 clk: imx8qxp: Corret LPCG registers and bits for MIPI SSYe Li
There are some problems in the 8QXP MIPI SS clock tree relating with LPCG: 1. i2c0 and i2c1 uses wrong registers and bits. i2c0 lpcg acutally is at offset 0x10 and i2c1 is at 0x14, ipg_clk and ipg_clk_s at bit 16 and i2c_clk is bit 0. 2. pwm uses wrong bit for 32k_clk, should be bit 4. 3. gpio uses wrong bit for ipg_clk, should be bit 16. Also since the ipg_clk and ipg_clk_s share same LPCG offset and bits, we only need to register one clock. So remove ipg_clk_s from clock tree. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-20222-2 ARM64:dts: Update SCFW APIRanjani Vaidyanathan
Update SCFW API to the following commit: " ("430d1e3646fbe75e339e18abf2330565eac906e0") Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Fri Nov 2 15:25:45 2018 -0500 SCF-105: RN updates. " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12clk: imx8mq: Switch to newly added composite-8m clockAbel Vesa
This needs to be one individual change since otherwise the driver and the dtbs won't build anymore. This updates all the dts and dtsi files, the clock index defines and the imx8mq clock driver itself Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-19575-1 imx8mm: clock: Add gpmi and apbh-dma clockYe Li
The gpmi clock is from NAND clock root, while aphb-dma clock is from NAND_USDHC_BUS_CLK_ROOT. Both share same clock gate CCGR_NAND. We use imx_clk_gate2_shared2 to create two clocks for them. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-19225: dt-bindings: pinctrl: imx8mm: fix sai1 pdm inputsAdrian Alonso
Fix PDM input select options, add missing daisy chain select option for routing PDM bitsream inputs from SAI1_RXDx pads. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (cherry picked from commit 8a6f7ddd5ba852fbc4511415506453ba1c575d6a)
2019-02-12MLK-17481-1: clk: imx8qm: Add DSP clocksDaniel Baluta
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db)
2019-02-12MLK-19174 arm64: dts: imx8qm: set enet IO voltage to 1.8vAndy Duan
By default, imx8qm b0 silicon set the IO voltage to 2.5v, but the arm2 board is designed as 1.8v voltage for enet IO, so force the IO voltage to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like: For ENET0: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB For ENET1: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA The pin setting: 1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000 2.5V : bit4=1, bit[30]=1, bit[2:0]=010 For 2.5v IO timing test, HW board need to do some rework: - Force PHY work at 2.5v mode - Supply 1.8v voltage to VDD_ENETx Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-19113-1 ARM64: imx: enable l1.1 aspm for imx8mmRichard Zhu
In the L1.1 ASPM implementation, the CLK_REQ# should be configured as open drain, pull up and input mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-19088-1 ARM64: imx: change the clkreq to opendrain inputRichard Zhu
In the L1.1 ASPM implementation, the CLK_REQ# should be configured as open drain, pull up and input mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-19038: dt-bindings: pinctrl: imx8mm add SAI1 PDM pinsAdrian Alonso
Add SAI1 PDM pin definitions for imx8mm SoC. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (cherry picked from commit 1ada53b6b48dc6e7360b75403bd0796b4bf52cf9)
2019-02-12MLK-18427-01 driver: clk: imx: Add dram core and alt root clkBai Ping
On i.MX8MM, it has an dram_alt clock source that can be used when DDRC clock rate is lower than 667MHz, so add this clock. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 303867c769e3c0758b9ee8fcf31d8cc3c632a80d)
2019-02-12MLK-18861: mx8qxp: Add the missing LCDIF clocks to clock driverAdriana Reus
Add LCDIF PLL resource and clocks, and power domain for it. Add Pixel link clocks and set it from bypass path. Muxes were added so that the slices can choose the bypass input (lcd_pxl_bypass_div and elcdif_pll_div). clk summary example: lcd_pxl_bypass_div 2 2 24000000 lcd_pxl_sel 1 1 24000000 lcd_pxl_div 1 1 24000000 lcd_pxl_clk 1 1 24000000 elcdif_pll_div 1 1 792000000 elcdif_pll 2 2 792000000 lcd_sel 1 1 792000000 lcd_div 1 1 79200000 lcd_clk 1 1 79200000 Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
2019-02-12MLK-18660-1 include: define the pd and lpcg of the lsio muRichard Zhu
In order to replace the M4_MU# by the LSIO MU in the RPMSG usage. Define the PD and LPCG address of the LSIO MU for iMX8. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-18617-2 clk: imx: clk-imx8qxp: Add MIPI PWM_DIV & PWM_CLK clk definitionsLiu Ying
This patch adds the MIPI PWM_DIV and PWM_CLK clock definitions. The PWM_DIV clock is the parent clock of PWM_CLK clock. The PWM_CLK will be used as the 'per' clock by the PWM driver. Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit a32d7b4bcca3da7bd154eaf46cf04852279d2c87)
2019-02-12MLK-18625-2 include: dts: imx8mq clk rename external pll sourceAdrian Alonso
External differential clock phy_27m can be set to all plls, rename from VIDEO2_PHY_27M to CLK_PHY_27M to avoid confusion as clock source is the same option for all plls Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> (cherry picked from commit e4ac6dff8fa2eda6f5c2ed35cfea3550c59916da)
2019-02-12MLK-18362-1 clk: imx8mm: add clock for csiRobby Cai
add csi clock, CLKO1 for MCLK, and also BUS clock Signed-off-by: Robby Cai <robby.cai@nxp.com>
2019-02-12MLK-16784-1 dt-bindings: pinctrl: add i.MX8MM PDM pinsCosmin-Gabriel Samoila
Add iMX8MM PDM pins header. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
2019-02-12MLK-18381-2 clk: imx8mm: add the mu root clkRichard Zhu
- mu is used by rpmsg on imx8mm, add the mu root clk. - check the m4 is enable or not. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-18267-2: clk: update clock tree for imx8qm hdmi rxSandor Yu
Add hdmi rx clocks define. Add hdmi rx power domain name. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-18277-01 clk: imx8mm: correct the gpu 2d/3d clock treeBai Ping
fix the gpu2d/3d clock tree on i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-18205-2 dt-bindings: clock: add i.MX8MM clock headerPeng Fan
Add i.MX8MM clock definition. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-18205-1 dt-bindings: pinctrl: add i.MX8MM pins headerBai Ping
Add i.MX8MM pins definition. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-18220-2 XRDC:Fix power domain and clock entries in DTSRanjani Vaidyanathan
Ensure that every resource is associated with a power domain and clocks required. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-17747: dsp: use the name of dsp instead of hifiWeiguang Kong
In order to avoid the name problem going forward with integration with Qcom, Qcom has their own dsp and hifi is competitor, so the hifi name should not be used in our code. So use the name of dsp instead of hifi to fix this problem. Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
2019-02-12MLK-17877 ARM64: dts: imx8qxp: change enet to 1.8v timing setting for B0 siliconFugang Duan
i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default, but MEK and ARM2 board only support 1.8V IO. So change the IO voltage as 1.8V setting. Set the MAC RGMII timing as TX no delay and RX delay mode as the default setting for MEK and ARM2 board. Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing and avoid CRC error, MEK base board and ARM2 cpu board should remove the driver device for the secord enet port. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-17908: ARM64: dts: Add power domains for HDMI resourcesSandor Yu
Add power domain PD_HDMI_PLL_0/1 and PD_HDMI_I2S. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-17230-2: CI_PI: add power domain names for CI_PI ssGuoniu.Zhou
Add power domain macro names for CI_PI subsystem. Reviewed-by: Sandor.Yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> (cherry picked from commit fd8318f4455ceafda963681ce05effd0ad81d714)
2019-02-12MLK-17230-1: CI_PI: register clocks for CI_PI ssGuoniu.Zhou
Register clocks for CI_PI subsystem. Reviewed-by: Sandor.Yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> (cherry picked from commit d29308ec4fa29addd049c114520d7628e9e921d7)
2019-02-12MLK-17729: ARM64: dts: Add power domains for display resourcesOliver Brown
Some resources are being enabled without the associated resource being powered up. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-02-12MLK-17634-9: clk: imx8m: add VIDEO2_PLL2 clock treeLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17491-46 clk: imx7ulp: add missing ↵Dong Aisheng
sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used by other devices later. All these clocks use the same divider as ddr_div, so ulp_div_table is used. Besides that, all these clocks need to be controlled by M4, so CLK_DIVIDER_READ_ONLY is also specified. Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver") Cc: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-02-12MLK-17491-21 clk: imx7ulp: fix RTC OSC clock nameDong Aisheng
'CKIL' clock name is derived from MX6 SoC series which is invalid for MX7ULP (can't find it from RM). Changing it to the correct 'ROSC' which is defined in RM. The exist 'OSC' name is also changed accordingly which should be SOSC (System OSC). Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver") Cc: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-02-12MLK-17461-1: clk: define hdmi pixel select clockSandor Yu
Define hdmi pixel select clocks. Define av_pll_bypass clock. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2019-02-12MLK-17341-5: imx8x: Rename imx8 mipi csi i2c power domainSandor Yu
Rename imx8x mipi csi i2c power domain. Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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