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We are missing spba clock in imx6sl's clock tree, thus add it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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In order to optmize low power IDLE numbers all PLLs should be in bypass.
On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency
is limited to 4MHz due to an internal divide by 6 divider.
For customer who don't require higher uart speeds add "uart_at_4M"
to the kernel command line.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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There's a enet clock gate missing in clock tree, thus add it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add support to scale the DDR frequency between 400MHz and 24MHz.
Add support to scale AHB between 132MHz and 24MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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There's a dividor for pll4_audio clock missing in clock tree, thus add it.
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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There is no OSC clock source option for gpt on i.mx6sl, it
can only source from perclk, and perclk can be from OSC.
As perclk is clock source of many low speed devices, set
it to be from OSC, this can avoid freq varying when bus
clk(ipg) is scaled.
Signed-off-by: Anson Huang <b20788@freescale.com>
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GPT clock is system clock source, need to avoid freq varying,
as system bus clock(ipg) may be changed, for i.mx6 series SOCs,
all of them except i.mx6q TO1.0 support sourcing GPT clk from
OSC directly, so switch gpt clock to OSC if the SOCs support
this feature, as OSC freq is constant.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The fec/enet driver calculates MDC rate with the formula below.
ref_freq / ((MII_SPEED + 1) x 2)
The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec. This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.
Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Commit 1f2c5fd5f0486566f73aa0149577d5f69df90bcc upstream.
Add clock support for Vybrid VF610. It uses dtc macro support to
define all clock IDs in vf610-clock.h to keep clock IDs coherence
between kernel and DT.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Commit 45fe6810347b0a83561a13d9ee656c899a309fc0 upstream.
Add clock support for i.MX6 SoloLite. It uses the dtc marco support to
define all clock IDs in imx6sl-clock.h, which will be included by both
clock driver and device tree sources, so that the data will stay sync
all the time between kernel and DT.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The ARM GIC binding defines a few custom cells and flags for its IRQ
specifier. Provide names for those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
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Many IRQ device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
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Many GPIO device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
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