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path: root/include/linux/mmc/sdhci.h
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2014-06-11mmc: sdhci: Use pre-allocated DMA buffersNaveen Kumar Arepalli
Use pre-allocated DMA buffers for ADMA descriptor and Bounce buffer instead of dynamic DMA mapping. This improves SDHCI driver performance by reducing dynamic DMA mapping overhead. Bug 1486735 Change-Id: Ic9c646437be047d33304339eccc48a825f0a8bcc Reviewed-on: http://git-master/r/380885 Cherry-picked from commit 7ffcc4cf1a1cec42610c1b55c30b3ec28547a11e Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com> Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Change-Id: If850a534ba9fbfd169b4fbefd35ca5922b1d1254 Reviewed-on: http://git-master/r/416955 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: R Raj Kumar <rrajk@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> (cherry picked from commit 9e58888afe4e66e83eece0a8332c8e7440bd1bcf) Reviewed-on: http://git-master/r/419444
2014-03-10mmc: sdhci: reduce SDIO delayed clk gate timeoutBitan Biswas
Delayed clock gate timeout for SDIO reduced from 20msec to 1msec - debugfs node added to change delayed clock gate timeout bug 1414742 bug 1453205 Change-Id: I875b6651aa739b5601cfed1bbe90c327a14a7bda Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/374156 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2014-01-30mmc: sdhci: data transfer statisticsBitan Biswas
sdhci debugfs nodes to enable collection of data transfer statistics. - collect following performance details: average performance in kbps best performance in kbps Worst performance in kbps - enable statistics collection # echo 1 > enable_sdhci_perf_stats - show statistics # cat sdhci_perf_stats - clear performance data # cat reset_sdhci_perf_stats Change-Id: I47eed32bfa6424c84ed7c6d9c029db84b96b6f86 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/328769 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-12-30EDP: remove old system EDP framework (emmc support)Timo Alho
This reverts commit 32609d0a9896ec47c522fd4cd0ca11ff0d27f046. Revised system edp software framework has been put in place. This patch removes old system edp client support from emmc/microsd driver code. Bug 1431977 Change-Id: I419f3f243af54579a12417e3a12f841c8d925410 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/350404 GVS: Gerrit_Virtual_Submit Reviewed-by: R Raj Kumar <rrajk@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-11-22mmc: sdhci: enable EMMC delayed clock gatingBitan Biswas
Aggressive clock gating was reported as degrading random performance numbers. Similar to SDIO we are enabling delayed clock gating of EMMC. This reduces the overhead of clock enable and disable. - clock gating happens if EMMC interface is idle for over 20msec bug 1372006 Change-Id: If9f08af6d5ae55e4c30aeef0a36d8c9fdd5fe5a8 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/328775 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
2013-10-29mmc: host: sdhci: sdio delayed clock gatePavan Kunapuli
Aggressive clock gate degrades sdio performance. Hence, sdio clock gate is delayed. - sdio clock gate is done if no further transaction starts within 20msec interval bug 1299485 Change-Id: Icb7a647bd4c725372173ea65894524f393220843 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/304725 Reviewed-by: Automatic_Commit_Validation_User
2013-10-28mmc: add revised system-EDP supportTimo Alho
This patch adds support to revised system-EDP framework Change-Id: Idcd9498046f31e2ecdead9638505b79b4a92eefe Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/301696 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-09-16mmc: tegra: Remove chip specific hw_opsPavan Kunapuli
Removed chip specific hw_ops. There really is only one callback being used currently to handle T30 clock stabilization bug. Added a quirk2 to handle clock stabilization WAR for T30. Added nvquirk to selectively enable HS200 capability. Bug 1330567 Reviewed-on: http://git-master/r/260565 (cherry picked from commit 80a3a19595e472381eee4624edd0dce74367b7f3) Change-Id: I2c2e7a07677c4c4fc7262643ae94537c786110fe Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/269190 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-16mmc: sdhci: Use quirks2 for defining new quirksPavan Kunapuli
Revert back quirks to 32 bits long and use quirks2 to define any new required quirks. Bug 1330567 Reviewed-on: http://git-master/r/260564 (cherry picked from commit 836c16ce754c154856369cc2d5494ece77aa573c) Change-Id: I5e7095fb18b2ccd19df44338e42b2a69d94be787 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/269189 GVS: Gerrit_Virtual_Submit Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14mmc: sdhci: Enable host clock before reg accessPavan Kunapuli
Some SDMMC controllers require host clock to be enabled before accessing the controller registers. Define SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK to handle this behavior. Ensure clock is enabled before register accesses in suspend/resume path. Enabled SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK for Tegra SDMMC controllers. Bug 1328858 Change-Id: I732d0597a715c96bc546beb4bba1beb86e51c302 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/255600 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-14mmc: sdhci: add 64bit DMA mode supportShridhar Rasal
- Configure UPPER_ADMA_ADDRESS register if controller version is 4.0 and supports 64 bit DMA addressing -Set HOST_VERSION_4_EN and ADDRESSING_64BIT_EN bits of AMCD12_ERR register for controller version >4.00. bug 1276024 Change-Id: I4dfc042092526ec7bcae2455067caff8c93a3e99 Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/232061 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-14mmc: add edp states supported datarrajk
Added edp support in mmc. Bug 1160688 Change-Id: I1d34d9b483ba7b20717bc4017df01e8b442d696a Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/216865 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14mmc: sdhci: Use SDHCI Quirks to fix t30 h/w issue.Naveen Kumar Arepalli
Use SDHCI_QUIRK_DISABLE_CARD_CLOCK quirk to disable card clock before internal clock Use SDHCI_QUIRK_DO_DUMMY_WRITE quirk to do a dummy write Bug 1239457 Change-Id: I35f66f59303f9b58b17b66c5f83cdd8d14facdc3 Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-on: http://git-master/r/215477 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-14mmc: host: Add SD/SDIO error stats supportrrajk
Adding Debugfs support for SD/SDIO error stats reports to debug the system. Bug 1170517 Change-Id: I4f0d6659cdbeb6ce8360bd0cf5d69584e7830fdc Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/164244 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14sdhci: add proper macro valuesShridhar Rasal
set quirks macros values properly wrt change in number of quirks and its data type. bug 919232 Change-Id: I9e980ffd4363ddfe5bd950932285513b27f44eaf Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/77802 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd8520be9adb81d8c917c7be492d3be43be4daf8d
2013-09-14mmc: sdhci: quirk for not calculate max_discard_toShridhar Rasal
Adding SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO for not to calculate max_discard_to which is deviation in setting max_discard. For some host controllers, combination of 1) calculated non-zero value of max_discard_to and 2) erase_group_def not set can result into setting max_discard value to pref_erase in sectors which is very less, so it takes long time for erase. With this change host controller can specify to calculate max_discard_to and based on that max_discard value will be set. bug 930767 Change-Id: I2c64ef8a6821620f2a65c06e25d2af68e3554a75 Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/79839 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: Ra9fba9c1554085f1b83733877621954f4d7fbf90
2013-09-14sdhci: Add option for non std freq tuningPavan Kunapuli
Adding option for non std freq tuning for host controllers that have deviation in the tuning procedure. Bug 920089 Change-Id: I8ca6962c6f0380c1160460e5094c47aee241d6e3 Reviewed-on: http://git-master/r/72603 Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I97cceb39fd27b159823ebce6706c5e74e53deccd Reviewed-on: http://git-master/r/77303 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: R7c1252a883f6ca8098f68fec40fd1949729b6d2a
2013-09-14mmc: sdhci: changing sdhci quirks data type to u64naveenk
Kernel 3.1 has more than 32 quirks changing quirks type to u64 Bug 921653 Change-Id: Id6607347e6e48cfa1534f1260e277f6e2f7a42ee Signed-off-by: naveenk <naveenk@nvidia.com> Reviewed-on: http://git-master/r/73167 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R85cc748bb7fdf8c2c287c78b5e2775892c14e2fe
2013-09-14mmc: Add support for non-standard voltage switchingPavan Kunapuli
Adding quirk SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING and callback switch_signal_voltage in sdhci_ops to support non standard signal voltage switching. Bug 906650 Change-Id: If5538fb3177770ccb103305a7b3f0f7a6a8b92e6 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/67137 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: R509e56592e164a43f0b07e2c4c23ee86773414bc
2013-09-14sdhci: Don't set SDIO card intr in resume by defaultPavan Kunapuli
Enable SDIO card interrupt in resume only if it is set before suspend. Bug 902633 Change-Id: I2ade8c204ddfa97e41d5c0e5bec67d07e68f81ad Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/66099 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: Rb2ba0ae696df9104840566a794780730d6da845f
2013-02-24mmc: sdhci: enhance preset value functionKevin Liu
4d55c5a1 ("mmc: sdhci: enable preset value after uhs initialization") added preset value support and enabled it by default during sd card init. Below are the enhancements introduced by this patch: 1. In current code, preset value is enabled after setting clock finished, which means the clock is manually set by driver firstly and then suddenly switched to preset value at this point. So the first setting is useless and unnecessary. What's more, the first clock setting may differ from the preset one. The better way is enable preset value just after switch to UHS mode so the preset value can take effect immediately. So move preset value enable from mmc_sd_init_card to sdhci_set_ios which will be called during set timing. 2. In current code, preset value is disabled at the beginning of mmc_attach_sd. It's too late since low freq (400khz) should be set in mmc_power_up. So move preset value disable to sdhci_set_ios which will be called during power up. 3. host->clock and ios->drv_type should also be updated according to the preset value if it's enabled. Current code missed this. 4. This patch also introduce a quirk to disable preset value in case preset value doesn't work. This patch has been verified on sdhci-pxav3 platform with both preset enabled and disabled. Signed-off-by: Kevin Liu <kliu5@marvell.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-12-06mmc: sdhci: add quirk for lack of 1.8v supportDaniel Drake
The OLPC XO-1.75 laptop includes a SDHCI controller which is 1.8v capable, and it truthfully reports so in its capabilities. This alternate voltage is used for driving new "UHS-I" SD cards at their full speed. However, what the controller doesn't know is that the motherboard physically doesn't have a 1.8v supply available. Add a quirk so that systems such as this one can override disable 1.8v support, adding support for UHS-I cards (by running them at 3.3v). This avoids a problem where the system would first try to run the card at 1.8v, fail, and then not be able to fully reset the card to retry at the normal 3.3v voltage. This is more appropriate than using the MISSING_CAPS quirk, which is intended for cases where the SDHCI controller is actually lying about its capabilities, and would force us to somehow override both caps words from another source. Signed-off-by: Daniel Drake <dsd@laptop.org> Reviewed-by: Philip Rakity <prakity@nvidia.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-12-06mmc: Standardise capability typeLee Jones
There are discrepancies with regards to how MMC capabilities are carried throughout the subsystem. Let's standardise them to eliminate any confusion. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-11-07mmc: sdhci-of-esdhc: disable CMD23 for some Freescale SoCsJerry Huang
CMD23 causes lots of errors in kernel on some freescale SoCs (P1020, P1021, P1022, P1024, P1025 and P4080) when MMC card used, which is because these controllers does not support CMD23, even on the SoCs which declares CMD23 is supported. Therefore, we'll not use CMD23. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-09-04mmc: sdhci: Add regulator support for vccq (voltage regualor)Philip Rakity
On some systems the host controller does not support vccq signaling. This is supplied by a dedicated regulator (vqmmc). Add support for this regulator. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-07-22mmc: sdhci: Introduce new flag SDHCI_USING_RETUNING_TIMERAaron Lu
Add a new flag of SDHCI_USING_RETUNING_TIMER to represent if the host is using a retuning timer for the card inserted. This flag is set when the host does tuning the first time for the card and the host's retuning mode is 1. This flag is used afterwards whenever needs to decide if the host is currently using a retuning timer. This flag is cleared when the card is removed in sdhci_reinit. The set/clear of the flag and the start/stop of the retuning timer is associated with the card's init/remove time, so there is no need to touch it when the host is to be removed as at that time the card should have already been removed. Signed-off-by: Aaron Lu <aaron.lu@amd.com> Reviewed-by: Girish K S <girish.shivananjappa@linaro.org> Reviewed-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-07-22mmc: sdhci: Allow caps[1] to be set via SDHCI_QUIRK_MISSING_CAPSPhilip Rakity
Currently only the capability_0 register can be set if SDHCI_QUIRK_MISSING_CAPS is defined. This is a problem when the capability_1 register also needs changing. Use the quirk SDHCI_QUIRK_MISSING_CAPS to allow both registers to be set. Redefining caps[1] is useful when the board design does not support 1.8v vccq so UHS modes are not available. The code that calls sdhci_add_host can then detect this condition and adjust the caps so the UHS mode will not be attempted on UHS cards. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-03-27mmc: sdhci: add quirk for keeping card power during suspendAdrian Hunter
Add quirk SDHCI_QUIRK2_HOST_OFF_CARD_ON to cater for the case when the card keeps power during suspend but the host controller does not i.e. the card power is not controlled by the host controller. In that case, the controller must be fully reset on resume. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-01-12mmc: host: Adds support for eMMC 4.5 HS200 modeGirish K S
This patch adds support for the HS200 mode on the host side. Also enables the tuning feature required when the HS200 mode is selected. Signed-off-by: Girish K S <girish.shivananjappa@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-01-11mmc: sdhci-pci: remove SDHCI_QUIRK2_OWN_CARD_DETECTIONAdrian Hunter
Even if a driver provides separate card detection, an interrupt is still needed to abort mmc requests that are in progress. SDHCI_QUIRK2_OWN_CARD_DETECTION prevents that, so remove it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-10-26mmc: sdhci-pci: add runtime pm supportAdrian Hunter
Ths patch allows runtime PM for sdhci-pci, runtime suspending after inactivity of 50ms and ensuring runtime resume before SDHC registers are accessed. During runtime suspend, interrupts are masked. The host controller state is restored at runtime resume. For Medfield, the host controller's card detect mechanism is supplanted by an always-on GPIO which provides for card detect wake-up. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-07-20mmc: Standardize header file inclusion checks.Robert P. J. Day
Standardize the checks for multiple MMC header file inclusion, including adding comments to terminating #endif's, and fixing one incorrect comment. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-25mmc: sdhci: Auto-CMD23 support.Andrei Warkentin
Enables Auto-CMD23 support where available (SDHCI 3.0 controllers) Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Tested-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-25mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI.Andrei Warkentin
Implements support for multiblock transfers bounded by SET_BLOCK_COUNT (CMD23). Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sdhci: add support for retuning mode 1Arindam Nath
Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sdhci: add support for programmable clock modeArindam Nath
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sd: add support for tuning during uhs initializationArindam Nath
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sdhci: Fix read-only detection with JMicron 388 chipTakashi Iwai
On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-01-08mmc: sdhci: add quirk for max len ADMA descriptorsOlof Johansson
Some controllers misparse segment length 0 as being 0, not 65536. Add a quirk to deal with it. Signed-off-by: Olof Johansson <olof@lixom.net> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-01-08mmc: Add support for JMicron 388 SD/MMC controllerTakashi Iwai
JMicron 388 SD/MMC combo controller supports the 1.8V low-voltage for SD, but MMC doesn't work with the low-voltage, resulting in an error at probing. This patch adds the support for multiple voltage mask per device type, so that SD works with 1.8V while MMC forces 3.3V. Here new ocr_avail_* fields for each device are introduced, so that the actual OCR mask is switched dynamically. Also, the restriction of low-voltage in core/sd.c is removed when the bit is allowed explicitly via ocr_avail_sd mask. This patch was rewritten from scratch based on Aries' original code. Signed-off-by: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-23mmc: sdhci: split up sdhci.h for sdhci-pltfm usersGiuseppe Cavallaro
Some platforms based on sdhci-pltfm need to set their own quirks. Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h. This patch splits drivers/mmc/host/sdhci.h into two parts: * drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors. * include/linux/mmc/sdhci.h includes the sdhci structure and quirks. Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h. This patch avoids adding/changing the calls/flags in the sdhci_pltfm_data structure. It has been tested on STM platforms (e.g. STx7106, STx7108, STx5206) where the driver is configured and used as shown in the example below: [snip] static int mmc_pad_resources(struct sdhci_host *sdhci) { if (!devm_stm_pad_claim(sdhci->mmc->parent, &stx7108_mmc_pad_config, dev_name(sdhci->mmc->parent))) return -ENODEV; return 0; } static struct sdhci_pltfm_data stx7108_mmc_platform_data = { .init = mmc_pad_resources, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; static struct platform_device stx7108_mmc_device = { .name = "sdhci", [snip] Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h, and no modifications should be needed on other sdhci-<XXX> drivers. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
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