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path: root/include/linux/mmc/sdhci.h
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2015-10-11mmc: sdhci: handle busy-end interrupt during commandChanho Min
It is fully legal for a controller to start handling busy-end interrupt before it has signaled that the command has completed. So make sure we do things in the proper order, Or it results that command interrupt is ignored so it can cause unexpected operations. This is founded at some toshiba emmc with the bellow warning. "mmc0: Got command interrupt 0x00000001 even though no command operation was in progress." This issue has been also reported by Youssef TRIKI: It is not specific to Toshiba devices, and happens with eMMC devices as well as SD card which support Auto-CMD12 rather than CMD23. Also, similar patch is submitted by: Gwendal Grignou <gwendal@chromium.org> Changes since v1: Fixed conflict with the next of git.linaro.org/people/ulf.hansson/mmc.git and Tested if issue is fixed again. Signed-off-by: Hankyung Yu <hankyung.yu@lge.com> Signed-off-by: Chanho Min <chanho.min@lge.com> Tested-by: Youssef TRIKI <youssef.triki@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit e99783a45220a2c5f5a598e0e81213ecf2dbcf2f)
2015-10-09mmc: sdhci-pci: add runtime pm supportAdrian Hunter
Ths patch allows runtime PM for sdhci-pci, runtime suspending after inactivity of 50ms and ensuring runtime resume before SDHC registers are accessed. During runtime suspend, interrupts are masked. The host controller state is restored at runtime resume. For Medfield, the host controller's card detect mechanism is supplanted by an always-on GPIO which provides for card detect wake-up. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org> (cherry picked from commit 66fd8ad5100b5003046aa744a4f12fa31bb831f9)
2013-04-18mmc: sdhci: add quirk for lack of 1.8v supportDaniel Drake
The OLPC XO-1.75 laptop includes a SDHCI controller which is 1.8v capable, and it truthfully reports so in its capabilities. This alternate voltage is used for driving new "UHS-I" SD cards at their full speed. However, what the controller doesn't know is that the motherboard physically doesn't have a 1.8v supply available. Add a quirk so that systems such as this one can override disable 1.8v support, adding support for UHS-I cards (by running them at 3.3v). This avoids a problem where the system would first try to run the card at 1.8v, fail, and then not be able to fully reset the card to retry at the normal 3.3v voltage. This is more appropriate than using the MISSING_CAPS quirk, which is intended for cases where the SDHCI controller is actually lying about its capabilities, and would force us to somehow override both caps words from another source. Signed-off-by: Daniel Drake <dsd@laptop.org> Reviewed-by: Philip Rakity <prakity@nvidia.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-02-13sdhci: add proper macro valuesShridhar Rasal
set quirks macros values properly wrt change in number of quirks and its data type. bug 919232 Change-Id: I9e980ffd4363ddfe5bd950932285513b27f44eaf Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/77802 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-02-09mmc: sdhci: quirk for not calculate max_discard_toShridhar Rasal
Adding SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO for not to calculate max_discard_to which is deviation in setting max_discard. For some host controllers, combination of 1) calculated non-zero value of max_discard_to and 2) erase_group_def not set can result into setting max_discard value to pref_erase in sectors which is very less, so it takes long time for erase. With this change host controller can specify to calculate max_discard_to and based on that max_discard value will be set. bug 930767 Change-Id: I2c64ef8a6821620f2a65c06e25d2af68e3554a75 Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/79839 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-01-30sdhci: Add option for non std freq tuningPavan Kunapuli
Adding option for non std freq tuning for host controllers that have deviation in the tuning procedure. Bug 920089 Change-Id: I8ca6962c6f0380c1160460e5094c47aee241d6e3 Reviewed-on: http://git-master/r/72603 Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I97cceb39fd27b159823ebce6706c5e74e53deccd Reviewed-on: http://git-master/r/77303 Reviewed-by: Automatic_Commit_Validation_User
2012-01-04mmc: sdhci: changing sdhci quirks data type to u64naveenk
Kernel 3.1 has more than 32 quirks changing quirks type to u64 Bug 921653 Change-Id: Id6607347e6e48cfa1534f1260e277f6e2f7a42ee Signed-off-by: naveenk <naveenk@nvidia.com> Reviewed-on: http://git-master/r/73167 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-08mmc: Add support for non-standard voltage switchingPavan Kunapuli
Adding quirk SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING and callback switch_signal_voltage in sdhci_ops to support non standard signal voltage switching. Bug 906650 Change-Id: If5538fb3177770ccb103305a7b3f0f7a6a8b92e6 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/67137 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2011-11-30sdhci: Don't set SDIO card intr in resume by defaultPavan Kunapuli
Enable SDIO card interrupt in resume only if it is set before suspend. Bug 902633 Change-Id: I2ade8c204ddfa97e41d5c0e5bec67d07e68f81ad Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/66099 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: Rb2ba0ae696df9104840566a794780730d6da845f
2011-07-20mmc: Standardize header file inclusion checks.Robert P. J. Day
Standardize the checks for multiple MMC header file inclusion, including adding comments to terminating #endif's, and fixing one incorrect comment. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-25mmc: sdhci: Auto-CMD23 support.Andrei Warkentin
Enables Auto-CMD23 support where available (SDHCI 3.0 controllers) Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Tested-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-25mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI.Andrei Warkentin
Implements support for multiblock transfers bounded by SET_BLOCK_COUNT (CMD23). Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sdhci: add support for retuning mode 1Arindam Nath
Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sdhci: add support for programmable clock modeArindam Nath
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sd: add support for tuning during uhs initializationArindam Nath
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-24mmc: sdhci: Fix read-only detection with JMicron 388 chipTakashi Iwai
On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-01-08mmc: sdhci: add quirk for max len ADMA descriptorsOlof Johansson
Some controllers misparse segment length 0 as being 0, not 65536. Add a quirk to deal with it. Signed-off-by: Olof Johansson <olof@lixom.net> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-01-08mmc: Add support for JMicron 388 SD/MMC controllerTakashi Iwai
JMicron 388 SD/MMC combo controller supports the 1.8V low-voltage for SD, but MMC doesn't work with the low-voltage, resulting in an error at probing. This patch adds the support for multiple voltage mask per device type, so that SD works with 1.8V while MMC forces 3.3V. Here new ocr_avail_* fields for each device are introduced, so that the actual OCR mask is switched dynamically. Also, the restriction of low-voltage in core/sd.c is removed when the bit is allowed explicitly via ocr_avail_sd mask. This patch was rewritten from scratch based on Aries' original code. Signed-off-by: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-23mmc: sdhci: split up sdhci.h for sdhci-pltfm usersGiuseppe Cavallaro
Some platforms based on sdhci-pltfm need to set their own quirks. Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h. This patch splits drivers/mmc/host/sdhci.h into two parts: * drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors. * include/linux/mmc/sdhci.h includes the sdhci structure and quirks. Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h. This patch avoids adding/changing the calls/flags in the sdhci_pltfm_data structure. It has been tested on STM platforms (e.g. STx7106, STx7108, STx5206) where the driver is configured and used as shown in the example below: [snip] static int mmc_pad_resources(struct sdhci_host *sdhci) { if (!devm_stm_pad_claim(sdhci->mmc->parent, &stx7108_mmc_pad_config, dev_name(sdhci->mmc->parent))) return -ENODEV; return 0; } static struct sdhci_pltfm_data stx7108_mmc_platform_data = { .init = mmc_pad_resources, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; static struct platform_device stx7108_mmc_device = { .name = "sdhci", [snip] Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h, and no modifications should be needed on other sdhci-<XXX> drivers. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>