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CPU register read did not have access to nvhost power management.
Due to this only modules that were powered on previously are actually
accessible via the API. This patch refactors CPU access to:
* Move mutexes to sync point, as they're sync point operations
* Move register address spaces to nvhost_device
* Call register read with access to the respective nvhost_device
* Initialize module completely at boot-up so that register reads
can be done without an initialized channel.
Reviewed-on: http://git-master/r/75275
Change-Id: I0db38cef7b2cd92dc64e7f55d227bdd2fdb8f752
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77764
Reviewed-by: Automatic_Commit_Validation_User
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Some hardware architectures require that only select MSB bits be
supplied to them for addresses. They do the reverse transformation while
accessing the actual memory.
Bug 857531
Change-Id: I215f099ff0ee86daff1c1eb1e5b70edf8ae856d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/66654
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Shashank Garg <sgarg@nvidia.com>
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Add interface for setting priority of a channel. When the priority is
low, wait for channel to become empty before submitting it.
Bug 864407
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/57237
(cherry picked from commit 75228616ee2c3073e391c529aecb3f82be3fc5a4)
Change-Id: I2f346918ae15427b826a2ec0c28bee6bc72dc859
Reviewed-on: http://git-master/r/59595
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rfb9ae7e88bec3a0c1e8f51f49f3e6f473d853b21
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In this change, nvhost_cdma starts a timer (if a timeout is specified
in the userctx), for the buffer at the head of the sync_queue that has
not reached its syncpt threshold.
If the timeout fires, nvhost_cdma initiates a channel / module reset.
It then detects up to where in the sync_queue it stopped execution
(based on the current HW syncpt value).
For any remaining uncompleted buffers in the context, nvhost_cdma NOPs
the entry and CPU incrs the syncpt to where it should be had it completed.
If one of the sync_queue entries belongs to another context, it still
does the syncpt incrs for this context, but via the PB as a GATHER opcode,
At the end, CDMA is restarted, so buffers are refetched (either with
NOP slots, or GATHERs to incr syncpts). This appears as though the
buffer has completed (and the associated resources released).
For testing, debugfs entries have been added under /d/tegra_nvhost
force_timeout_val - set the timeout value, in ms
force_timeout_channel - channel ID, were timeouts checks occur
force_timeout_pid - process ID to set the userctx
The idea is to set the timeout_val, then the timeout_channel (e.g. for
3D, the channel ID is 1) and then the process ID, gotten from running
adb shell ps.
Bug 625545
Original-Change-Id: I659e9255f1105f3439ce23e9169a19739b83ea52
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/42655
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R89759c129e2db8f7dbf83a6066fc29947f95cc27
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To prepare for kernel modularization, nvhost include files need to be
moved from mach-tegra/include to kernel/include. At the same time
user space specific part is split into nvhost_ioctl.h.
Bug 854182
Original-Change-Id: I3694a40d786028733310ecf5b59341282af571be
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/43211
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc4fadf65d59ddfb5bb924e7adfccd39e86a0b2c7
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