summaryrefslogtreecommitdiff
path: root/include/soc
AgeCommit message (Collapse)Author
2018-08-31MLK-19380 driver: soc: update the noc QoS setting on imx8mqBai Ping
update the noc QoS setting for CPU & VPU on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Jian Li <jian.li@nxp.com> (cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac)
2018-08-24MLK-19305-1 soc: imx: add PAD wakeup supportAnson Huang
Add PAD wakeup support for i.MX8 platforms with system controller present, with PAD wakeup feature enabled, the corresponding resource's power is no need to be kept enabled when linux suspend, thus save a sub-system's power consumption. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-17481-1: clk: imx8qm: Add DSP clocksDaniel Baluta
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2018-08-24MLK-19034 clk: imx8qm: Fix clk_unused crashTeo Hall
Remove unused ROMCP clks and related as LPCG no longer exists Signed-off-by: Teo Hall <teo.hall@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-18987 soc: imx8: sc: types: Add SC_C_SYNC_CTRL into enum sc_ctrl_eLiu Ying
This patch adds SC_C_SYNC_CTRL into enum sc_ctrl_e to sync with SCU firmware commit <1db854d7d521> (SCF-151: Added new SC_C_SYNC_CTRL to control both control signals at the same time.). Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-18861: mx8qxp: Add the missing LCDIF clocks to clock driverAdriana Reus
Add LCDIF PLL resource and clocks, and power domain for it. Add Pixel link clocks and set it from bypass path. Muxes were added so that the slices can choose the bypass input (lcd_pxl_bypass_div and elcdif_pll_div). clk summary example: lcd_pxl_bypass_div 2 2 24000000 lcd_pxl_sel 1 1 24000000 lcd_pxl_div 1 1 24000000 lcd_pxl_clk 1 1 24000000 elcdif_pll_div 1 1 792000000 elcdif_pll 2 2 792000000 lcd_sel 1 1 792000000 lcd_div 1 1 79200000 lcd_clk 1 1 79200000 Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
2018-08-24MLK-18660-1 include: define the pd and lpcg of the lsio muRichard Zhu
In order to replace the M4_MU# by the LSIO MU in the RPMSG usage. Define the PD and LPCG address of the LSIO MU for iMX8. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-18632-2 soc: imx: add support for setting wakeup source in ATFAnson Huang
To support lowest power mode for suspend, if no wakeup source from non-secure partition is enabled, IRQSTEER can be powered off when suspend, otherwise, IRQSTEER needs to be powered on to support wakeup, so need to pass WU domain wakeup source info to ATF, then ATF will decide if to power off IRQSTEER when system suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-18592-1 soc: imx: use vendor hvc to communiate with SCUPeng Fan
Let Dom0 use hvc to trap to xen to communicate with SCU. xen could reuse the MU used by Dom0 before. By reusing the MU in Dom0, xen has power to control resources owned by DomU. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-24MLK-18483-01 soc: imx8: sc: types: add ipg stop misc controls for CONN ENETAndy Duan
- Sync with scu firmware commit 576011819ce3 (SCF-81: Added API to control MIPI CSI calibration.) and commit 095a0d7dbc0b (SCF-85: Add direct control of ENET IPG stop control) - Add ipg stop misc controls for CONN ENET. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2018-08-24MLK-17747: dsp: use the name of dsp instead of hifiWeiguang Kong
In order to avoid the name problem going forward with integration with Qcom, Qcom has their own dsp and hifi is competitor, so the hifi name should not be used in our code. So use the name of dsp instead of hifi to fix this problem. Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
2018-08-24MLK-18101-1 include: soc: imx8: sc: types: Add SC_C_SEL0 for B0 imx8qxp boardYuchou Gan
Add SC_C_SEL0 for imx8qm/qxp B0. Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
2018-08-24MLK-17230-1: CI_PI: register clocks for CI_PI ssGuoniu.Zhou
Register clocks for CI_PI subsystem. Reviewed-by: Sandor.Yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> (cherry picked from commit d29308ec4fa29addd049c114520d7628e9e921d7)
2018-08-24MLK-17561-1 soc:imx8: Update to the latest SCFW API based on commit:Ranjani Vaidyanathan
" commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5 Author: Chuck Cannon <chuck.cannon@freescale.com> Date: Tue Feb 6 08:54:16 2018 -0600 Add unique ID API call. Required to get info needed for SECO fuse programming. Added info command to DM. " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MLK-17369: soc:imx8qm/qxp: Add controls for display controller resetsOliver Brown
" commit cfdb9821531da523fd1f01536eb67c8b8451477f Author: Oliver Brown <oliver.brown@nxp.com> Date: Tue Jan 2 07:46:06 2018 -0600 dc: Add controls for display controller resets. " Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-08-24MLK-17083 soc: imx: limit VPU/CPU bandwidth for lcdif on i.MX8MQAnson Huang
Config NOC to limit bandwidth to 4GB for both VPU and CPU to avoid lcdif flickering only when lcdif is enabled. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
2018-08-24MLK-16891: watchdog: imx8_wdt: add pre_timeout notificationRobin Gong
Add pre_timeout set and notification for i.mx8qm/qxp. BuildInfo: - SCFW 36ff24f3, IMX-MKIMAGE 05d3d4a7, ATF 93dd1cc - U-Boot 2017.03-00684-g28c5243 Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16765-1: soc: i.MX8: Update to the latest SCFW APIRobin Gong
Update since new button/wdog interface added on scfw: commit e7d95e1e306a Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16760 soc: imx: support i.MX8MQ new revision SoCAnson Huang
On i.MX8MQ, the new revision SoC does NOT update the revision info in ANATOP_DIGPROG register, to support dynamic SOC id/revision detection, only reading info from ANATOP_DIGPROG is not working now, change to read SOC id/revision from ATF which is in secure world. The ATF will read the ANATOP_DIGPROG as well as ROM version to decide the SOC revision. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-16746 imx8mq: support m4Peng Fan
Support M4/A53 work together 1. add imx_src_is_m4_enabled 2. introduce a new dts dedicated for m4 3. add more pwm nodes 4. Since clk initialization is at very early stage, add m4 enabled check in the beginning of clk code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-16689-03 driver: soc: Add busfreq driver for imx8mqBai Ping
Add busfreq driver support on i.MX8MQ. The busfreq driver is mainly used for dynamic DDR frequency change for power saving feature. When there is no peripheral or DMA device has direct access to DDR memory, we can lower the DDR frequency to save power. Currently, we support frequency setpoint for LPDDR4: (1): 3200mts, the DDRC core clock is sourced from 800MHz dram_pll, the DDRC apb clock is 200MHz. (2): 400mts, the DDRC core clock is source from sys1_pll_400m, the DDRC apb clock is is sourced from sys1_pll_40m. (3): 100mts, the DDRC core clock is sourced from sys1_pll_100m, the DDRC apb clock is sourced from sys1_pll_40m. In our busfreq driver, we have three mode supported: * high bus mode <-----> 3200mts; * audio bus mode <-----> 400mts; * low bus mode <-----> 100mts; The actual DDR frequency is done in ARM trusted firmware by calling the SMCC SiP service call. BuildInfo: - IMX-MKIMAGE: 05d3d4a7d7, ATF: 724cc2b890 - SPL/Uboot: f72c10d2db; Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16704-1: watchdog: imx8_wdt: add watchdog driver for i.mx8QM/QXPRobin Gong
This watchdog driver is a virtual driver in Linux and call ATF interface where call SCFW eventually. In SCFW, it's done by SCU timer tick instead of hardware watchdog.This is why we have to call ATF because such system resource owned by secure patition.Currently, booard reset happen if not ping this software watchdog in time in linux side, may change to partition reboot once SCFW support this feature in the future. BuildInfo: - SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb - U-Boot 2017.03-00097-gd7599cf Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16702 soc:imx8qm/qxp Adding additional frequenciesOliver Brown
Adding defines for 864 MHz and 432 MHz from the following commits: " commit 655ed33f3b2e158ea92ab96c3999a5bd73791d76 Author: Oliver Brown <oliver.brown@nxp.com> Date: Thu Oct 26 11:49:49 2017 -0500 MIPI DSI V2: Adding define for 432 MHz. " " commit 88456c73b3c1ffde496622f2e66614a46a073410 Author: Oliver Brown <oliver.brown@nxp.com> Date: Tue Oct 17 10:53:58 2017 -0500 MIPI DSI: change the fixed clocks to allow for a 27MHz PHY reference clock. " Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-08-24MLK-16606-1 clk: imx8qm: add M4 I2C clocksDong Aisheng
There're two M4 I2C instances in MX8QM. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2018-08-24MLK-16351 rtc: imx-sc: use SIP to set RTC timeAnson Huang
For system controller RTC, as it belongs SC_R_SYSTEM, and SC_R_SYSTEM is assigned in ARM-Trusted-Firmware, so here needs to use SIP to trap into ATF to do set time, or system controller firmware will return error since linux kernel does NOT own this system resource. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16264 soc:imx8qm/imx8qxp: Update to the latest SCFW APIRanjani Vaidyanathan
Update uboot to the latest SCFW based on commit: " commit 129c16e312334af7b07d71d6dccac1cda1808b93 Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Date: Thu Aug 24 16:50:59 2017 -0500 Add support to change DRC clock rate. " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MLK-16244-2 cpufreq: imx8: add SIP cpu-freq supportAnson Huang
Add SIP cpu-freq support, the CPU hardware frequency scale will be performed by ARM Trusted Firmware, and add cpu-freq suspend support, MAX frequency will be used during suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16062-1: Fix PXL mipi csi0/1 clock gate register addressSandor Yu
mipi csi0/1 clock gate register address swapped. It will cause mipi csi0/1 failed to work. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-08-24MLK-16077-2: clk: imx: update cm40 clock for imx8qxpShengjiu Wang
Add cm40 I2C clock for imx8qxp Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2018-08-24MLK-16030-2 soc: imx: gpc: add power domain namesAnson Huang
Add power domain names for i.MX8MQ, currently only 11 power domains support runtime ON/OFF. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-16028 clk: imx8qm: add clk for dsi0 i2c0Gao Pan
add clk for dsi0 i2c0 Signed-off-by: Gao Pan <pandy.gao@nxp.com>
2018-08-24MLK-16005-1 drivers: soc: refine the imx8 soc revision supportJason Liu
This patch is to refine the imx8 soc revision support. The imx8qm and imx8qxp will go through the SCU API to get the silicon ID and REVISION. imx8mq will go through the anatop interface to get the ID/REV. Since the silicon ID/REV need be set as early as possible, thus refine it by using the early_initcall for the early initialization. For the SCU API interface, this need be called after the MU interface initialized. Signed-off-by: Jason Liu <jason.hui.liu@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2018-08-24MLK-15319 imx8qm/imx8qx: Update to SCFW API based on commit:Ranjani Vaidyanathan
" commit a645f3c4c529e1f8cc5a624a047a3af56cfd39e1 Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Date: Thu Jun 29 15:21:53 2017 -0500 Turn off all HDMI-TX clocks by default. This is required for setting the rate of the DIG PLL. Add code to enable/disable the correct clocks before SECO accesses the HDMI SS. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MLK-15149-01 driver: soc: add gpc power domain support on i.mx8mqBai Ping
Add generic power domain driver support on i.mx8mq. The power domain on/off operations need to use the SIP service call to trap into secure monitor to handle it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-15128-7 clk: imx: add i.mx8mq clock driver supportAnson Huang
Add i.MX8MQ clock driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-15128-6 soc: imx: add psci gpc support for i.mx8mqAnson Huang
Add i.MX8MQ PSCI GPC virtual driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-15001-5 clk: imx8qxp: Add some clocks support for DC and MIPI-LVDS SSsLiu Ying
This patch adds some clocks support for DC and MIPI-LVDS subsystems. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2018-08-24MLK-14998: i.MX8: Update to the latest SCFW APIRanjani Vaidyanathan
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MLK-13972-1 soc: scfw: imx8qxp: fix audio LPCGsViorel Suman
Cleanup audio LPCGs: add missing, fix names, remove unneeded. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2018-08-24MLK-14599-1 soc:imx8:Update SCFW APIRanjani Vaidyanathan
Update SCFW API to the following commit in SCFW git: " 'commit: ("a620caf7444c45715b68b5cf128219005598365f")' Author: Mike <michael.kjar@nxp.com> Date: Thu Mar 30 18:35:27 2017 -0500 Added a DDR Stress Test to the test folder - New DDR test is like the stress test where we increment/sweep the DDR freq - More tests may be added as development continues - Modified mx8qm/soc.h to boot the A72 to DDR when building with option qmddr " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MLK-13911-5 soc: scfw: imx8: add SCFWAnson Huang
Add i.MX8 SCFW API support. Based on below commit: (fcd0efb5f2550712bd7d27f1279e51f7f687f71d) Fix MX8 MU driver to follow Linux coding conventions. Remove unused functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-08-24MLK-11488-9 arm: imx: add A9-M4 clk shared managementAnson Huang
As A9 and M4 share many resources on i.MX6SX, especially for clk and power related resource, so we need to handle the hardware conflict between these two cores, there are two cases that we need to consider currently: clk management: for every clk node, only when both A9 and M4 do NOT need it, then we can disable it from hardware; Here we use MU and hardware SEMA4 to achieve our goal, MU is for communiation between A9 and M4, SEMA4 is to protect the shared memory. For clk management, we use shared memory to maintain the clk status for both A9 and M4 side, and this shared memory is protected by hardware SEMA4, A9 and M4 will maintain their own clk tree info in their SW environment, and get other CORE's clk tree info from shared memory to decide whether to perform a hardware setting change when they plan to. Signed-off-by: Anson Huang <b20788@freescale.com>
2018-08-03memory: tegra: Apply interrupts mask per SoCDmitry Osipenko
[ Upstream commit 1c74d5c0de0c2cc29fef97a19251da2ad6f579bd ] Currently we are enabling handling of interrupts specific to Tegra124+ which happen to overlap with previous generations. Let's specify interrupts mask per SoC generation for consistency and in a preparation of squashing of Tegra20 driver into the common one that will enable handling of GART faults which may be undesirable by newer generations. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-04-13fsl/qe: add bit description for SYNL register for GUMRHolger Brunck
[ Upstream commit c7f235a7c2d09b1b83671ba2d93ebee981554467 ] Add the bitmask for the two bit SYNL register according to the QUICK Engine Reference Manual. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-24net: ethernet: ucc_geth: fix MEM_PART_MURAM modeChristophe Leroy
[ Upstream commit 8b8642af15ed14b9a7a34d3401afbcc274533e13 ] Since commit 5093bb965a163 ("powerpc/QE: switch to the cpm_muram implementation"), muram area is not part of immrbar mapping anymore so immrbar_virt_to_phys() is not usable anymore. Fixes: 5093bb965a163 ("powerpc/QE: switch to the cpm_muram implementation") Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Li Yang <pku.leo@gmail.com> Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-12ARM: at91: define LPDDR typesAlexandre Belloni
commit e3f0a4017c2143b4b813df6a93e8cf79e3f76936 upstream. The Atmel MPDDR controller support LPDDR2 and LPDDR3 memories, add their types. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Reichel <sre@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-10-14Merge tag 'powerpc-4.9-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull more powerpc updates from Michael Ellerman: "Some more powerpc updates for 4.9: Freescale updates from Scott Wood: - qbman support (a prerequisite for datapath drivers such as ethernet) - a PCI DMA fix+improvement - reset handler changes - more 8xx optimizations - some cleanups and fixes.' Fixes: - selftests/powerpc: Add missing binaries to .gitignores (Michael Ellerman) - selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes (Michael Ellerman) - powerpc/pseries: Fix stack corruption in htpe code (Laurent Dufour) - powerpc/64s: Fix power4_fixup_nap placement (Nicholas Piggin) - powerpc/64: Fix incorrect return value from __copy_tofrom_user (Paul Mackerras) - powerpc/mm/hash64: Fix might_have_hea() check (Michael Ellerman) Other: - MAINTAINERS: Remove myself from PA Semi entries (Olof Johansson) - MAINTAINERS: Drop separate pseries entry (Michael Ellerman) - MAINTAINERS: Update powerpc website & add selftests (Michael Ellerman): * tag 'powerpc-4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (35 commits) powerpc/mm/hash64: Fix might_have_hea() check powerpc/64: Fix incorrect return value from __copy_tofrom_user powerpc/64s: Fix power4_fixup_nap placement powerpc/pseries: Fix stack corruption in htpe code selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes MAINTAINERS: Update powerpc website & add selftests MAINTAINERS: Drop separate pseries entry MAINTAINERS: Remove myself from PA Semi entries selftests/powerpc: Add missing binaries to .gitignores arch/powerpc: Add CONFIG_FSL_DPAA to corenetXX_smp_defconfig soc/qman: Add self-test for QMan driver soc/bman: Add self-test for BMan driver soc/fsl: Introduce DPAA 1.x QMan device driver soc/fsl: Introduce DPAA 1.x BMan device driver powerpc/8xx: make user addr DTLB miss the short path powerpc/8xx: Move additional DTLBMiss handlers out of exception area powerpc/8xx: use r3 to scratch CR in ITLBmiss soc/fsl/qe: fix gpio save_regs functions powerpc/8xx: add dedicated machine check handler powerpc/8xx: add system_reset_exception ...
2016-10-04Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk framework updates from Stephen Boyd: "The core clk framework changes are small again. They're mostly minor fixes that weren't causing enough problems (or any problems when we're just clarifying things) to warrant sending outside the merge window. The majority of changes are in drivers for various SoCs. Full details are in the logs, but here's the summary. Core: - Better support for DeviceTree overlays with the addition of the CLK_OF_DECLARE_DRIVER macro. Now we won't probe a clk driver for a device node that matched during of_clk_init(), unless the driver uses CLK_OF_DECLARE_DRIVER instead of CLK_OF_DECLARE. This allows overlays to work cleanly for drivers that must probe before the device model is ready, and also after it's ready when an overlay is loaded. - Clarification in the code around how clk_hw pointers are returned from of clk providers - Proper migration of prepare/enable counts to parents when the clk tree is constructed New Drivers: - Socionext's UniPhier SoCs - Loongson1C - ZTE ZX296718 - Qualcomm MDM9615 - Amlogic GXBB AO clocks and resets - Broadcom BCM53573 ILP - Maxim MAX77620 Updates: - Four Allwinner SoCs are migrated to the new style clk driver (A31, A31s, A23 and A33) - Exynos 5xxx audio and DRAM clks - Loongson1B AC97, DMA and NAND clks - Rockchip DDR clks and rk3399 driver tweaks - Renesas R-Car M3-W (r8a7796) SoC SDHI interface and Watchdog timer clks - Renasas R-Car H3 and M3-W CMT clks and RAVB+Thermal clks for M3-W - Amlogic GXBB MMC gate clks - at91 sama5d4 sckc - Removal of STiH415 and STiH416 clk support as the SoC is being removed - Rework of STiH4xx clk support for new style bindings - Continuation of driver migration to clk_hw based registration APIs - xgene PMD support - bcm2835 critical clk markings - ARM versatile ICST" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (199 commits) CLK: Add Loongson1C clock support clk: Loongson1: Make use of GENMASK clk: Loongson1: Update clocks of Loongson1B clk: Loongson1: Refactor Loongson1 clock clk: change the type of clk_hw_onecell_data.num to unsigned int clk: zx296718: register driver earlier with core_initcall clk: mvebu: dynamically allocate resources in Armada CP110 system controller clk: mvebu: fix setting unwanted flags in CP110 gate clock clk: nxp: clk-lpc32xx: Unmap region obtained by of_iomap clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap clk: sunxi-ng: Fix reset offset for the A23 and A33 clk: at91: sckc: optimize boot time clk: at91: Add sama5d4 sckc support clk: at91: move slow clock controller clocks to sckc.c clk: imx6: initialize GPU clocks clk: imx6: fix i.MX6DL clock tree to reflect reality clk: imx53: Add clocks configuration clk: uniphier: add clock data for UniPhier SoCs clk: uniphier: add core support code for UniPhier clock driver clk: bcm: Add driver for BCM53573 ILP clock ...
2016-09-25soc/fsl: Introduce DPAA 1.x QMan device driverClaudiu Manoil
This driver enables the Freescale DPAA 1.x Queue Manager block. QMan is a hardware accelerator that manages frame queues. It allows CPUs and other accelerators connected to the SoC datapath to enqueue and dequeue ethernet frames, thus providing the infrastructure for data exchange among CPUs and datapath accelerators. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25soc/fsl: Introduce DPAA 1.x BMan device driverClaudiu Manoil
This driver enables the Freescale DPAA 1.x Buffer Manager block. BMan is a hardware accelerator that manages buffer pools. It allows CPUs and other accelerators connected to the SoC datapath to acquire and release buffers during data processing. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-20 20:38:00 +0000