summaryrefslogtreecommitdiff
path: root/include/soc
AgeCommit message (Collapse)Author
2019-12-05SSI-87: soc: imx: secvio: Add support for SNVS secvio and tamper via SCFWFranck LENORMAND
The driver register an IRQ handle to SCU for security violation interrupt. When an interruption is fired, the driver inform the user. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2019-12-05SSI-87: soc:imx: Add sc_seco_secvio_dgo_config to headerFranck LENORMAND
The function sc_seco_secvio_dgo_config is not declared in the header. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2019-11-21MLK-22998-3 soc:imx: Update SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit 6dcd0242ae Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-06-20MLK-21399 irqchip: gic-v3: Rework the ERR11171 workaroundAbel Vesa
Instead of just raising irq0 for all the cores, we mask the irq0 for all the non-target cores, this way waking up only the core we want. All of this is done now in TF-A. Also, since this new workaround doesn't need the IOMUX_GPR1 register here in kernel, the IOMUX_GPR reg entry inside the gic dts node can be removed. In order for this to work, the following commit is needed in TF-A: 0e91ff59720d0756 ("MLK-21399 plat: imx8mq: gpc: Workaround for ERR11171") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-04-08MLK-21393 soc: imx: update SCFW APIAnson Huang
This patch updates SCFW API to v1.7, based on below commit: 252281d48647 ("SCF-105: Update wiki.") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-03-11MLK-20958-1 imx8: Sync SCFW API to v1.4Leonard Crestez
Many whitespace and formatting changes were skipped Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-02-27MLK-20996 soc: imx: update SCFW APIsAnson Huang
Update SCFW APIs to SCFW commit: e7a99eb96207 ("SCF-351: Add API to change boot parms.") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-15MLK-20930-2 soc: imx: update SCFW APIsAnson Huang
Update SCFW APIs to SCFW commit: 004247e14afc ("SCF-341 Fix bug in setting large slice clock divider") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-02-12MLK-20890-1 soc: imx8: Add support to read HDCP fuse.Oliver Brown
Added function to read HDCP disable fuse. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-02-12MLK-20899 soc: imx: update SCFW APIsAnson Huang
Update SCFW APIs to SCFW commit: 5c03342369e8 ("SCF-105: Change links in wiki index.") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-20691-1: rpmsg: imx_rpmsg: add new partition reset interruptRobin Gong
Add new partition reset interrupt group to know M4 reset and restore back at rpmsg level later. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-20222-1 soc: Update SCFW APIRanjani Vaidyanathan
Update SCFW API to the following commit: " ("430d1e3646fbe75e339e18abf2330565eac906e0") Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Fri Nov 2 15:25:45 2018 -0500 SCF-105: RN updates. " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-19380 driver: soc: update the noc QoS setting on imx8mqBai Ping
update the noc QoS setting for CPU & VPU on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Jian Li <jian.li@nxp.com> (cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac)
2019-02-12MLK-18987 soc: imx8: sc: types: Add SC_C_SYNC_CTRL into enum sc_ctrl_eLiu Ying
This patch adds SC_C_SYNC_CTRL into enum sc_ctrl_e to sync with SCU firmware commit <1db854d7d521> (SCF-151: Added new SC_C_SYNC_CTRL to control both control signals at the same time.). Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 9e4a5892dad642f76e3bb0d46c77c4a59bbcae3d)
2019-02-12MLK-19305-1 soc: imx: add PAD wakeup supportAnson Huang
Add PAD wakeup support for i.MX8 platforms with system controller present, with PAD wakeup feature enabled, the corresponding resource's power is no need to be kept enabled when linux suspend, thus save a sub-system's power consumption. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 3b5d781273b22461de9aaea337f9da9b2fdb643e)
2019-02-12MLK-17481-1: clk: imx8qm: Add DSP clocksDaniel Baluta
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db)
2019-02-12MLK-19034 clk: imx8qm: Fix clk_unused crashTeo Hall
Remove unused ROMCP clks and related as LPCG no longer exists Signed-off-by: Teo Hall <teo.hall@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 1c15332dffe7e41f0b9d367b96dd426798ec8b06)
2019-02-12MLK-18861: mx8qxp: Add the missing LCDIF clocks to clock driverAdriana Reus
Add LCDIF PLL resource and clocks, and power domain for it. Add Pixel link clocks and set it from bypass path. Muxes were added so that the slices can choose the bypass input (lcd_pxl_bypass_div and elcdif_pll_div). clk summary example: lcd_pxl_bypass_div 2 2 24000000 lcd_pxl_sel 1 1 24000000 lcd_pxl_div 1 1 24000000 lcd_pxl_clk 1 1 24000000 elcdif_pll_div 1 1 792000000 elcdif_pll 2 2 792000000 lcd_sel 1 1 792000000 lcd_div 1 1 79200000 lcd_clk 1 1 79200000 Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
2019-02-12MLK-18660-1 include: define the pd and lpcg of the lsio muRichard Zhu
In order to replace the M4_MU# by the LSIO MU in the RPMSG usage. Define the PD and LPCG address of the LSIO MU for iMX8. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-18632-2 soc: imx: add support for setting wakeup source in ATFAnson Huang
To support lowest power mode for suspend, if no wakeup source from non-secure partition is enabled, IRQSTEER can be powered off when suspend, otherwise, IRQSTEER needs to be powered on to support wakeup, so need to pass WU domain wakeup source info to ATF, then ATF will decide if to power off IRQSTEER when system suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-18592-1 soc: imx: use vendor hvc to communiate with SCUPeng Fan
Let Dom0 use hvc to trap to xen to communicate with SCU. xen could reuse the MU used by Dom0 before. By reusing the MU in Dom0, xen has power to control resources owned by DomU. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-02-12MLK-18483-01 soc: imx8: sc: types: add ipg stop misc controls for CONN ENETAndy Duan
- Sync with scu firmware commit 576011819ce3 (SCF-81: Added API to control MIPI CSI calibration.) and commit 095a0d7dbc0b (SCF-85: Add direct control of ENET IPG stop control) - Add ipg stop misc controls for CONN ENET. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-02-12MLK-17747: dsp: use the name of dsp instead of hifiWeiguang Kong
In order to avoid the name problem going forward with integration with Qcom, Qcom has their own dsp and hifi is competitor, so the hifi name should not be used in our code. So use the name of dsp instead of hifi to fix this problem. Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
2019-02-12MLK-18101-1 include: soc: imx8: sc: types: Add SC_C_SEL0 for B0 imx8qxp boardYuchou Gan
Add SC_C_SEL0 for imx8qm/qxp B0. Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
2019-02-12MLK-17230-1: CI_PI: register clocks for CI_PI ssGuoniu.Zhou
Register clocks for CI_PI subsystem. Reviewed-by: Sandor.Yu <sandor.yu@nxp.com> Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> (cherry picked from commit d29308ec4fa29addd049c114520d7628e9e921d7)
2019-02-12MLK-17369: soc:imx8qm/qxp: Add controls for display controller resetsOliver Brown
" commit cfdb9821531da523fd1f01536eb67c8b8451477f Author: Oliver Brown <oliver.brown@nxp.com> Date: Tue Jan 2 07:46:06 2018 -0600 dc: Add controls for display controller resets. " Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-02-12MLK-17083 soc: imx: limit VPU/CPU bandwidth for lcdif on i.MX8MQAnson Huang
Config NOC to limit bandwidth to 4GB for both VPU and CPU to avoid lcdif flickering only when lcdif is enabled. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
2019-02-12MLK-16891: watchdog: imx8_wdt: add pre_timeout notificationRobin Gong
Add pre_timeout set and notification for i.mx8qm/qxp. BuildInfo: - SCFW 36ff24f3, IMX-MKIMAGE 05d3d4a7, ATF 93dd1cc - U-Boot 2017.03-00684-g28c5243 Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16760 soc: imx: support i.MX8MQ new revision SoCAnson Huang
On i.MX8MQ, the new revision SoC does NOT update the revision info in ANATOP_DIGPROG register, to support dynamic SOC id/revision detection, only reading info from ANATOP_DIGPROG is not working now, change to read SOC id/revision from ATF which is in secure world. The ATF will read the ANATOP_DIGPROG as well as ROM version to decide the SOC revision. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-16746 imx8mq: support m4Peng Fan
Support M4/A53 work together 1. add imx_src_is_m4_enabled 2. introduce a new dts dedicated for m4 3. add more pwm nodes 4. Since clk initialization is at very early stage, add m4 enabled check in the beginning of clk code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-16689-03 driver: soc: Add busfreq driver for imx8mqBai Ping
Add busfreq driver support on i.MX8MQ. The busfreq driver is mainly used for dynamic DDR frequency change for power saving feature. When there is no peripheral or DMA device has direct access to DDR memory, we can lower the DDR frequency to save power. Currently, we support frequency setpoint for LPDDR4: (1): 3200mts, the DDRC core clock is sourced from 800MHz dram_pll, the DDRC apb clock is 200MHz. (2): 400mts, the DDRC core clock is source from sys1_pll_400m, the DDRC apb clock is is sourced from sys1_pll_40m. (3): 100mts, the DDRC core clock is sourced from sys1_pll_100m, the DDRC apb clock is sourced from sys1_pll_40m. In our busfreq driver, we have three mode supported: * high bus mode <-----> 3200mts; * audio bus mode <-----> 400mts; * low bus mode <-----> 100mts; The actual DDR frequency is done in ARM trusted firmware by calling the SMCC SiP service call. BuildInfo: - IMX-MKIMAGE: 05d3d4a7d7, ATF: 724cc2b890 - SPL/Uboot: f72c10d2db; Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16704-1: watchdog: imx8_wdt: add watchdog driver for i.mx8QM/QXPRobin Gong
This watchdog driver is a virtual driver in Linux and call ATF interface where call SCFW eventually. In SCFW, it's done by SCU timer tick instead of hardware watchdog.This is why we have to call ATF because such system resource owned by secure patition.Currently, booard reset happen if not ping this software watchdog in time in linux side, may change to partition reboot once SCFW support this feature in the future. BuildInfo: - SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb - U-Boot 2017.03-00097-gd7599cf Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16606-1 clk: imx8qm: add M4 I2C clocksDong Aisheng
There're two M4 I2C instances in MX8QM. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-02-12MLK-16351 rtc: imx-sc: use SIP to set RTC timeAnson Huang
For system controller RTC, as it belongs SC_R_SYSTEM, and SC_R_SYSTEM is assigned in ARM-Trusted-Firmware, so here needs to use SIP to trap into ATF to do set time, or system controller firmware will return error since linux kernel does NOT own this system resource. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16244-2 cpufreq: imx8: add SIP cpu-freq supportAnson Huang
Add SIP cpu-freq support, the CPU hardware frequency scale will be performed by ARM Trusted Firmware, and add cpu-freq suspend support, MAX frequency will be used during suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16062-1: Fix PXL mipi csi0/1 clock gate register addressSandor Yu
mipi csi0/1 clock gate register address swapped. It will cause mipi csi0/1 failed to work. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2019-02-12MLK-16077-2: clk: imx: update cm40 clock for imx8qxpShengjiu Wang
Add cm40 I2C clock for imx8qxp Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2019-02-12MLK-16030-2 soc: imx: gpc: add power domain namesAnson Huang
Add power domain names for i.MX8MQ, currently only 11 power domains support runtime ON/OFF. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-16028 clk: imx8qm: add clk for dsi0 i2c0Gao Pan
add clk for dsi0 i2c0 Signed-off-by: Gao Pan <pandy.gao@nxp.com>
2019-02-12MLK-16005-1 drivers: soc: refine the imx8 soc revision supportJason Liu
This patch is to refine the imx8 soc revision support. The imx8qm and imx8qxp will go through the SCU API to get the silicon ID and REVISION. imx8mq will go through the anatop interface to get the ID/REV. Since the silicon ID/REV need be set as early as possible, thus refine it by using the early_initcall for the early initialization. For the SCU API interface, this need be called after the MU interface initialized. Signed-off-by: Jason Liu <jason.hui.liu@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2019-02-12MLK-15149-01 driver: soc: add gpc power domain support on i.mx8mqBai Ping
Add generic power domain driver support on i.mx8mq. The power domain on/off operations need to use the SIP service call to trap into secure monitor to handle it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-15128-7 clk: imx: add i.mx8mq clock driver supportAnson Huang
Add i.MX8MQ clock driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-15128-6 soc: imx: add psci gpc support for i.mx8mqAnson Huang
Add i.MX8MQ PSCI GPC virtual driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-15001-5 clk: imx8qxp: Add some clocks support for DC and MIPI-LVDS SSsLiu Ying
This patch adds some clocks support for DC and MIPI-LVDS subsystems. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-13972-1 soc: scfw: imx8qxp: fix audio LPCGsViorel Suman
Cleanup audio LPCGs: add missing, fix names, remove unneeded. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-02-12MLK-13911-5 soc: scfw: imx8: add SCFWAnson Huang
Add i.MX8 SCFW API support. Based on below commit: (fcd0efb5f2550712bd7d27f1279e51f7f687f71d) Fix MX8 MU driver to follow Linux coding conventions. Remove unused functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Added to drivers/soc/imx instead of drivers/soc/imx8 Skipped imx8 imx_rpmsg code Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-11488-9 arm: imx: add A9-M4 clk shared managementAnson Huang
As A9 and M4 share many resources on i.MX6SX, especially for clk and power related resource, so we need to handle the hardware conflict between these two cores, there are two cases that we need to consider currently: clk management: for every clk node, only when both A9 and M4 do NOT need it, then we can disable it from hardware; Here we use MU and hardware SEMA4 to achieve our goal, MU is for communiation between A9 and M4, SEMA4 is to protect the shared memory. For clk management, we use shared memory to maintain the clk status for both A9 and M4 side, and this shared memory is protected by hardware SEMA4, A9 and M4 will maintain their own clk tree info in their SW environment, and get other CORE's clk tree info from shared memory to decide whether to perform a hardware setting change when they plan to. Signed-off-by: Anson Huang <b20788@freescale.com> Also made SOC_IMX6SX select IMX_SEMA4 as part of this commit to fix build failures. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2018-08-03memory: tegra: Apply interrupts mask per SoCDmitry Osipenko
[ Upstream commit 1c74d5c0de0c2cc29fef97a19251da2ad6f579bd ] Currently we are enabling handling of interrupts specific to Tegra124+ which happen to overlap with previous generations. Let's specify interrupts mask per SoC generation for consistency and in a preparation of squashing of Tegra20 driver into the common one that will enable handling of GART faults which may be undesirable by newer generations. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-06-21soc: bcm2835: Make !RASPBERRYPI_FIRMWARE dummies return failureGeert Uytterhoeven
[ Upstream commit 144345a4a8c3b497a3f60d3af9d6071a37660186 ] If CONFIG_RASPBERRYPI_FIRMWARE=n: drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_polarity’: drivers/gpio/gpio-raspberrypi-exp.c:71: warning: ‘get.polarity’ is used uninitialized in this function drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_direction’: drivers/gpio/gpio-raspberrypi-exp.c:150: warning: ‘get.direction’ is used uninitialized in this function The dummy firmware interface functions return 0, which means success, causing subsequent code to make use of the never initialized output parameter. Fix this by making the dummy functions return an error code (-ENOSYS) instead. Note that this assumes the firmware always fills in the requested data in the CONFIG_RASPBERRYPI_FIRMWARE=y case. Fixes: d45f1a563b92dac7 ("staging: vc04_services: fix up rpi firmware functions") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-05-30ARC: mcip: update MCIP debug mask when the new cpu came onlineEugeniy Paltsev
[ Upstream commit f3205de98db2fc8083796dd5ad81b191e436fab8 ] As of today we use hardcoded MCIP debug mask, so if we launch kernel via debugger and kick fever cores than HW has all cpus hang at the momemt of setup MCIP debug mask. So update MCIP debug mask when the new cpu came online, instead of use hardcoded MCIP debug mask. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-19 22:44:22 +0000