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Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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This is 10-bit per channel YUV420 semi-planar.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
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EA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
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Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
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This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
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Since other USB 2.0 host may need it, like USB2 for XHCI. We move
this design to HCD core.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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This patch fixes playback for movies with unaligned widths/heights and
adds cropping functionality for tiled formats. Untiled formats will not
have this feature as cropping is a DTRC function.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Fix some typos for enum entry names of scaler_scale_mode_t.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Add handling code to support tiled and compressed pixel source
layout. The tiled only layout will bypass DEC400D and be resolved
by DPR, since DEC400D is only responsible for decompression.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add a new fb modifier for Vivante compressed and tiled
pixle layout which can be decompressed by DEC400D module
in DCSS.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Define hdmi pixel select clocks.
Define av_pll_bypass clock.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
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In order to support multi-fifo sdma script, the audio driver need to send
the fifo number to dma driver through dma_slave_config, and the cpu_dai
driver should config fifo_num for the audio platform driver, then platform
driver can config fifo_num to dma.
So add new variable fifo_num for struct snd_dmaengine_dai_dma_data.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
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In order to support multi-fifo sdma script, the audio driver need to send
the fifo number to dma driver through dma_slave_config, so add src_fifo_num
and dst_fifo_num two new variable for struct dma_slave_config.
src_fifo_num: bit 0-7 is the fifo number, bit:8-11 is the fifo offset;
dst_fifo_num: same as src_fifo_num
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
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update sdma script for multi fifo SAI on i.mx8MQ.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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This patch effectively enables DTRC module in DCSS to decode tiled
formats from VPU:
* uncompressed G1;
* uncompressed G2;
* compressed G2;
Compressed G2 formats need to pass on the decompression table offsets,
by using the 'dtrc_dec_ofs' property. This is a 64 bit value like below:
64--------48----------32---------16---------0
|<- chroma table ofs ->|<- luma table ofs ->|
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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These formats will be used by VPU and DCSS.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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The DPU spec tells us that we need to wait for all pending frames to
be completed when a display stream is disabled. It turns out
that the hardcoded 60-microsecond timeout value is not enough for
some low refresh rate video modes, e.g., 1920x1080@24, which makes
the display stream be disabled incorrectly(leave the hardware an
incorrect machine status). The SoC design indicates that there are
two pending frames to complete in the worst case. This patch waits
for at most three frame duration(which is enough for sure) so that
the hardware may flush out all the pending frames. In case the clock
subsystem provides us a pixel clock with wrong rate and causes the
timeout value be unreasonably long, we truncate it to wait for at
most three seconds.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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"
commit cfdb9821531da523fd1f01536eb67c8b8451477f
Author: Oliver Brown <oliver.brown@nxp.com>
Date: Tue Jan 2 07:46:06 2018 -0600
dc: Add controls for display controller resets.
"
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
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Currently the clock parent actually is failed to be restored in power
domain driver due to the set_parent will bail out early as the clk core
already cached the same old parent.
Implement a CLK_SET_PARENT_NOCACHE flag in clk core and register all
SC mux clocks with this flag to make sure the clk core won't bypass
the SC clock parent setting.
[ Aisheng: "Add commit message" ]
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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Configure dprc to enable prefetch for dpu blit.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
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Add struct drm_imx_dpu_frame_info.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
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Rename imx8x mipi csi i2c power domain.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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In order to avoid license problem of Cadence header files, these
license files has been wrappered into a library and new interface
has been abstracted to replace the interface of Cadence header
files.
So update the mxc_hifi4.h file to provide new interface for
user space to use.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
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On i.MX7ULP B0 chip, SNVS is located on M4 domain,
all RTC related functions need to use RPMSG channel
to communicate with M4 to proceed hardware operation.
The RTC RPMSG channel index is 6.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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This patch makes the necessary changes so that, for downscaling ratios
more than 3:1 and up to 7:1 (for video) and 5:1 (for graphics), the
WRSCL/RDSRC path will be used. This way the DRAM bandwidth will be lower
and spread evenly across the frame time.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
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When scaling up/down, DCSS has limits that cannot be exceeded. This
patch adds checks before the plane is updated and rejects those planes
that exceed the up/down scale limits.
Currently, the limit is 3:1 for downscaling and 1:3 for upscaling for
both video and graphics channels.
When support for WR_SCL/RD_SRC will be added, these limits will increase
to the following values:
* video: 7:1 downscale, 1:7 upscale
* graphics: 5:1 downscale, 1:5 upscale
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then enable the display controller, wait for the frame
index starting to move and finally switch TCON to operation mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds framegen timestamp support for the frame index feature.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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When we use prefetch, we use DPR and PRG to do frame input cropping.
Thus, the stride of fetcheco is the stride of cropped frame, which means
the value of the stride is cropped_width * bytes_per_pixel. Since the
pixel format has to be NV12 or NV21 when we use prefetch, we assume the
cropped_width stands for how many UV we have in bytes for one line, while
bytes_per_pixel should be 8bits for every U or V component. Also, to
address TKT339017, when we use prefetch engine for fetcheco, we need to
round the stride up to the fetcheco burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetcheco_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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When we use prefetch, we use DPR and PRG to do frame input cropping. Thus,
the stride of fetchdecode is the stride of cropped frame, which means the
value of the stride is cropped_width * bytes_per_pixel. Also, to address
TKT339017, when we use prefetch engine for fetchdecode, we need to round
the frame stride up to the fetchdecode burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetchdecode_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds helper fetcheco_set_burstlength() so that
the burst length of fetcheco can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16. When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16. This alignment operation can address
the issue recorded by TKT343664.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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fetchdecode_set_burstlength()
This patch adds helper fetchdecode_set_burstlength() so that
the burst length of fetchdecode can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16. When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16. This alignment operation can address
the issue recorded by TKT343664.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds some helpers to set/get fetcheco off pin.
We need to pin fetcheco off when the primary plane is disabled and the
relevant fetcheco is feed by prefetch engine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds DPR support for fetchdecode in the DPU base driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds IMX8QXP_DC0_DPR1_APB_CLK and IMX8QXP_DC0_DPR1_B_CLK clocks
support.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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We will support DPR interrupts via DPU core driver.
In order to distinguish bewteen the inner DPU interrupts and the DPR
interrupts, let's rename some software stuffs which are related to
DPU interrupts so that they may show they are DPU inner explicitly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds the base
driver support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds the base driver support
for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Amphion VPU has a tiled layout using 8x128 pixel vertical strips,
where each strip contains 1x16 groups of 8x8 pixels in a row-major layout.
Signed-off-by: Song Bing <bing.song@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
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domains
Currently the generic power domain suspend code pm_genpd_suspend_noirq
will try to power off a domain used by devices in genpd_sync_poweroff
if its status is not GPD_STATE_ACTIVE.
However, for power domains supporting multiple low power states, it may
already enter an intermediate low power state by runtime PM before system
suspend and the status is already GPD_STATE_POWER_OFF which results in
then the power domain stay at an intermediate low power state during
system suspend.
Let's give the power domain a chance to switch to the deepest state in
case it's already off but in an intermediate low power state.
Due to power domain is alway off, so no need to check device wakeup
case anymore.
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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