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In the uart_handle_cts_change(), uart_write_wakeup() is called after
we call @uart_port->ops->start_tx().
The Documentation/serial/driver tells us:
-----------------------------------------------
start_tx(port)
Start transmitting characters.
Locking: port->lock taken.
Interrupts: locally disabled.
-----------------------------------------------
So when the uart_write_wakeup() is called, the port->lock is taken by
the upper. See the following callstack:
|_ uart_write_wakeup
|_ tty_wakeup
|_ ld->ops->write_wakeup
With the port->lock held, we call the @write_wakeup. Some implemetation of
the @write_wakeup does not notice that the port->lock is held, and it still
tries to send data with uart_write() which will try to grab the prot->lock.
A dead lock occurs, see the following log caught in the Bluetooth by uart:
--------------------------------------------------------------------
BUG: spinlock lockup suspected on CPU#0, swapper/0/0
lock: 0xdc3f4410, .magic: dead4ead, .owner: swapper/0/0, .owner_cpu: 0
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.10.17-16839-ge4a1bef #1320
[<80014cbc>] (unwind_backtrace+0x0/0x138) from [<8001251c>] (show_stack+0x10/0x14)
[<8001251c>] (show_stack+0x10/0x14) from [<802816ac>] (do_raw_spin_lock+0x108/0x184)
[<802816ac>] (do_raw_spin_lock+0x108/0x184) from [<806a22b0>] (_raw_spin_lock_irqsave+0x54/0x60)
[<806a22b0>] (_raw_spin_lock_irqsave+0x54/0x60) from [<802f5754>] (uart_write+0x38/0xe0)
[<802f5754>] (uart_write+0x38/0xe0) from [<80455270>] (hci_uart_tx_wakeup+0xa4/0x168)
[<80455270>] (hci_uart_tx_wakeup+0xa4/0x168) from [<802dab18>] (tty_wakeup+0x50/0x5c)
[<802dab18>] (tty_wakeup+0x50/0x5c) from [<802f81a4>] (imx_rtsint+0x50/0x80)
[<802f81a4>] (imx_rtsint+0x50/0x80) from [<802f88f4>] (imx_int+0x158/0x17c)
[<802f88f4>] (imx_int+0x158/0x17c) from [<8007abe0>] (handle_irq_event_percpu+0x50/0x194)
[<8007abe0>] (handle_irq_event_percpu+0x50/0x194) from [<8007ad60>] (handle_irq_event+0x3c/0x5c)
--------------------------------------------------------------------
This patch adds more limits to the @write_wakeup, the one who wants to
implemet the @write_wakeup should follow the limits which avoid the deadlock.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Since we've fixed the clock's shared-gate issue, we no longer
need this gate clock. Thus drop it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit c368f9011aebb877aaffc6e4c5d12c7893b552b0)
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If an architecture has futex_atomic_cmpxchg_inatomic() implemented and there
is no runtime check necessary, allow to skip the test within futex_init().
This allows to get rid of some code which would always give the same result,
and also allows the compiler to optimize a couple of if statements away.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Finn Thain <fthain@telegraphics.com.au>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Link: http://lkml.kernel.org/r/20140302120947.GA3641@osiris
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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update the struct of sdma script platform data.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add imx6sx vadc gpr register define.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Other USB drivers may want to use OTG final state machine
implementation, so make this header available for them.
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry-picked from commit 5653668c9585441926dd2575791f6b5bb84bb254)
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- add linux sema4 driver, that mandatory required by mcc.
- use volatile types in sema4 structure
- align the port definiton a9 is 1, m4 is 2.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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- inherited mcc ver 001.002 from vibryd mqx release.
- use mu general int4 as the cpu2cpu int (num is 122 at a9 side).
- add linux wait_event/wake_up mechanism on the buffer management
of share memory
- replace wait_event_interruptible### by wait_event###, so the sleep
task wouldn't be waken up by reboot or CTRL+C signals.
- use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX
exchanges.
- regmap_bits_updat can't write 1 to clear the bit-set asr, use
regmap_read/write
- fix mu irq clear hang issue
only do the regmap once in the isr register func, and
replace the multi-regmap operations in the kinds of mx6sx mcc related
apis by one global imx_mu_reg.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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- inherited mcc ver 001.002 from vibryd mqx release.
- let lwevent related codes mqx specified.
- use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX
exchanges.
- add some modification in mcc common codes, since all the shm
access should be protected by sema4.
- double check the list head, and make the recv more robust.
Acked-by: Shawn Guo
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add check_xrun and device_reset for dmaengine_pcm
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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To support a wider variety of backlight setups, introduce an optional
enable GPIO. Legacy users of the platform data already have a means of
supporting GPIOs by using the .init(), .exit() and .notify() hooks. DT
users however cannot use those, so an alternative method is required.
In order to ease the introduction of the optional enable GPIO, make it
available in the platform data first, so that existing users can be
converted. Once that has happened a second patch will add code to make
use of it in the driver.
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit 2b9b1620349e325f184c68cddf3b484499c163c0)
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Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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On Solo X, SPDIF and AUDIO clocks shares one single gate to switch two
entirely different clock routes:
SPDIF <-- <---- SPDIF_PODF ----....
\ /
gate1
/ \
AUDIO <-- <---- AUDIO_PODF ----....
The two audio modules would easily cause conflict during clock operations
if running in the same time:
SPDIF <-- gate1 <---- SPDIF_PODF ----....
AUDIO <-- gate1 <---- AUDIO_PODF ----....
To keep them safe, we here have to merge them into one gate clock and limit
their rates and parent identical:
<---- SPDIF_PODF ----....
/
SPDIF, AUDIO <-- gate1
\
<---- AUDIO_PODF ----....
[ The only disadvantage of this modification is that we can not separately
set a different clock rates and clock sources to SPDIF and AUDIO clock. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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This patch adds SAI script support to imx-sdma.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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There's one clock for SAI memory access missing in the clock tree. Thus add it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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GET_FEATURES and SET_FEATURES also need byte-addressing on 16-bit devices.
Signed-off-by: David Mosberger <davidm@egauge.net>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch makes it possible to set the chipidea udc into full-speed only mode.
It is set by the oftree property "maximum-speed = full-speed".
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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this helper will be used for controllers which
want to work at a lower speed even though they
support higher USB transfer rates.
One such case is Texas Instruments' AM437x
SoC where it uses a USB3 controller without
a USB3 PHY, rendering the controller USB2-only.
Signed-off-by: Felipe Balbi <balbi@ti.com>
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This patch adds LDB mux ctrl bit definitions for imx6sx.
The bit DISP_MUX_LDB_MUX_CTRL is defined in the register IOMUXC_GPR5.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch adds LVDS mux ctrl bit definitions for imx6dl.
The bits LVDS0/1_MUX_CTL are defined in the register IOMUXC_GPR3.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit f2518480c7b744296a5587990a54e3a284d932b8)
Conflicts:
drivers/regulator/pfuze100-regulator.c
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According to imx6sx RM, there are three clock providers for ASRC:
Module clock Clock root Gate
asrck_clock_d spdif0_clk_root N/A
ipg_clk ahb_clk_root asrc_clk_enable
mem_clk ahb_clk_root asrc_clk_enable
while the current clock tree describes a clock named 'ASRC' that only
describes the asrc_clk_enable function.
Thus this patch first adds the other missing clocks to ASRC.
[ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk
to ASRC in the devicetree directly. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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ASRC needs three clocks from SoC, they are:
mem_clk: Peripheral access clock
ipg_clk: Peripheral clock
asrck_clk: ASRC module clock
while the current driver only maintains two of them and has confusing
clock names. Thus fix it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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- add mandatory pcie related clks in imx6sx clks tree
- add pcie dts in imx6sx dts
- add pcie kconfig option in imx6sx soc config
- add pcie regulate into dts
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add the "page" argument for the read_subpage hook. With this argument,
the implementation of this hook could prints out more accurate information
for debugging.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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For the casual device driver writer, it is hard to remember when to use
init_completion (to init a completion structure) or INIT_COMPLETION (to
*reinit* a completion structure). Furthermore, while all other
completion functions exepct a pointer as a parameter, INIT_COMPLETION
does not. To make it easier to remember which function to use and to
make code more readable, introduce a new inline function with the proper
name and consistent argument type. Update the kernel-doc for
init_completion while we are here.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13)
Cc: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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Add a resource managed devm_iio_device_alloc()/devm_iio_device_free()
to automatically clean up any allocations made by IIO drivers,
thus leading to simplified IIO drivers code.
In addition, this will allow IIO drivers to use other devm_*() API
(like devm_request_irq) and don't care about the race between
iio_device_free() and the release of resources by Device core
during driver removing.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Oleksandr Kravchenko <o.v.kravchenko@globallogic.com>
Tested-by: Oleksandr Kravchenko <o.v.kravchenko@globallogic.com>
Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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This commit adds simple helpers to obtain the devicetree properties
that specify the ECC strength and ECC step size to use on a given
NAND controller.
Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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It seems the include guard was copied from of_net.h.
Signed-off-by: Philipp Rosenberger <philipp.rosenberger@xse.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Just like the rest of the subsystems, let's add the required no-op
functions to implement stubs when CONFIG_OF=n.
This prevents MTD drivers from having ugly ifdefs in their code,
and instead hide the ifdef monster in the header closet (far away
from people's sight).
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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We currently has asrc_* clocks in the imx6sx clock tree while actually,
according to the Reference Manual, all of them should be named after the
audio_clk that controls the external MCLK output from MCLK pad of AUDMUX.
Thus fix it along with its gate clock missing in the current clock tree.
Meanwhile, this patch also configures a default clock rate for it -- 24MHz.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Add the spi_nor_match_id() to find the proper spi_device_id with the
NOR flash's name in the spi_nor_ids table.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer.
Before this patch, the layer is like:
MTD
------------------------
m25p80
------------------------
spi bus driver
------------------------
SPI NOR chip
After this patch, the layer is like:
MTD
------------------------
spi-nor
------------------------
m25p80
------------------------
spi bus driver
------------------------
SPI NOR chip
With the spi-nor controller driver(Freescale Quadspi), it looks like:
MTD
------------------------
spi-nor
------------------------
fsl-quadspi
------------------------
SPI NOR chip
New APIs:
spi_nor_scan: used to scan a spi-nor flash.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The spi_nor{} is cloned from the m25p{}.
The spi_nor{} can be used by both the m25p80 and spi-nor controller.
We also add the spi_nor_xfer_cfg{} which can be used by the two
fundamental primitives: read_xfer/write_xfer.
1) the hooks for spi_nor{}:
@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them
by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready.
@read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.
2) Add a new field sst_write_second for the SST NOR write.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.
This hearder can be used by the m25p80.c and other spi-nor controller,
such as Freescale's Quadspi.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Some platforms have read-only clock muxes that are preconfigured at
reset and cannot be changed at runtime. This patch extends mux clock
driver to allow handling such read-only muxes by adding new
CLK_MUX_READ_ONLY mux flag.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.
When b01 should be set as switching mux, it also needs to indicate
the change by setting hiword mask (b11 << 16).
The patch adds mux flag for this usage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.
When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).
The patch adds divider flag for this usage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't
set. This implements determine_rate for clk-mux to propagate to each
parent and to choose the best one (like clk-divider this chooses the
parent which provides the fastest rate <= the requested rate).
The determine_rate op is implemented as a core helper function so that
it can be easily used by more complex clocks which incorporate muxes.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.
To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Add core support to allow clock implementations to select the best
parent clock when rounding a rate, e.g. the one which can provide the
closest clock rate to that requested. This is by way of adding a new
clock op, determine_rate(), which is like round_rate() but has an extra
parameter to allow the clock implementation to optionally select a
different parent clock. The core then takes care of reparenting the
clock when setting the rate.
The parent change takes place with the help of some new private data
members. struct clk::new_parent specifies a clock's new parent (NULL
indicates no change), and struct clk::new_child specifies a clock's new
child (whose new_parent member points back to it). The purpose of these
are to allow correct walking of the future tree for notifications prior
to actually reparenting any clocks, specifically to skip child clocks
who are being reparented to another clock (they will be notified via the
new parent), and to include any new child clock. These pointers are set
by clk_calc_subtree(), and the new_child pointer gets cleared when a
child is actually reparented to avoid duplicate POST_RATE_CHANGE
notifications.
Each place where round_rate() is called, determine_rate() is checked
first and called in preference. This restructures a few of the call
sites to simplify the logic into if/else blocks.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Abstract access to the clock parent cache by defining
clk_get_parent_by_index(clk, index). This allows access to parent
clocks from clock drivers.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch adds the parsing code for the JEDEC compliant NAND.
Since we need the 0x40 as the column address, this patch also
makes the NAND_CMD_PARAM to use the 8-bit address only.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Add a helper to get the supported features for JEDEC compliant NAND.
Also add a macro JEDEC_FEATURE_16_BIT_BUS.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Add the jedec_version field, and add an anonymous union which
contains the nand_onfi_params and nand_jedec_params.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Create the nand_jedec_params{} and jedec_ecc_info{} according to
the JESD230A (Revision of JESD230, October 2012).
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Allow DMA data to be set at probe time for devices that can do that,
avoiding the need to do it every time we start a stream and supporting
non-DT dmaengine users using the helpers.
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit ecfc0c04f236f1e2a95094792ec10cf27be39f7c)
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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For many drivers using the generic dmaengine PCM driver one of the few (or the
only) things left to do in the drivers remove function is to unregister the PCM
device. This patch adds a resource managed version of snd_dmaengine_pcm_register()
which makes it possible to simplify the remove function as well as the error
path in the probe function for those drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 21585ee848078b12d0d1a513e93936bf96b444a0)
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Simplify error handling and remove repetitive (and rarely executed) code
for unregistration by providing a devm_snd_soc_register() card.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
(cherry picked from commit 0e4ff5c806263bf40ee5409ac283b776f0c11e41)
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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