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Depending on sample rate the PDM must be clocked at either 24.576MHz or
22.5792MHz. CLK_DIV is later calculated as function of PDM root clock
frequency and FS. Setting PDM root clock = FS * 1024 is wrong because
for low sample rate such as 8000 the PDM root clock will be 8000 * 1024
= 8192000 Hz so PDM will be underclocked for this sample rate.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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The original patch updates REG_MICFIL_STAT in fsl_micfil_reset
method, but not in configure_hwvad_interrupts, fix this.
Fixes: e12b0060cdac ("MLK-22598: ASoC: fsl_micfil: Reset channel output
data Flag")
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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The reason is that we access the register when power is disabled
reproduce command:
echo 8 > /sys/devices/platform/soc@0/30c00000.bus/30c00000.spba-bus/30ca0000.micfil/hwvad/enable
[ 332.838518] SError Interrupt on CPU2, code 0xbf000002 -- SError
[ 332.838521] CPU: 2 PID: 1383 Comm: sh Tainted: G O 5.4.24-2.1.0+g2ad925d15481 #1
[ 332.838523] Hardware name: NXP i.MX8MPlus EVK board (DT)
[ 332.838525] pstate: 20000085 (nzCv daIf -PAN -UAO)
[ 332.838526] pc : regcache_sync_block+0x7c/0x258
[ 332.838528] lr : regcache_sync_block+0xf0/0x258
[ 332.838531] sp : ffff800012bf3be0
[ 332.838532] x29: ffff800012bf3be0 x28: 0000000000000000
[ 332.838535] x27: 0000000000000000 x26: 0000000000000001
[ 332.838541] x25: ffff00017753ed00 x24: 0000000000000000
[ 332.838546] x23: ffff00017706d400 x22: 000000000000002b
[ 332.838550] x21: ffff00017753f100 x20: ffff000177538c00
[ 332.838554] x19: 0000000000000001 x18: 0000000000000000
[ 332.838559] x17: 0000000000000000 x16: 0000000000000000
[ 332.838564] x15: 0000000000000000 x14: 0000000000000000
[ 332.838567] x13: 0000000000000000 x12: 0000000000000000
[ 332.838572] x11: ffff800012bf3d50 x10: ffff000173c0e900
[ 332.838577] x9 : ffff00017706d870 x8 : 0000000000000000
[ 332.838582] x7 : 00000000000000a8 x6 : 0000000000000000
[ 332.838587] x5 : 0000000000000000 x4 : ffff800010769d88
[ 332.838592] x3 : ffff80001076d278 x2 : 0000000008000000
[ 332.838597] x1 : ffff800023c10000 x0 : 0000000000000000
[ 332.838603] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 332.838605] CPU: 2 PID: 1383 Comm: sh Tainted: G O 5.4.24-2.1.0+g2ad925d15481 #1
[ 332.838606] Hardware name: NXP i.MX8MPlus EVK board (DT)
[ 332.838608] Call trace:
[ 332.838609] dump_backtrace+0x0/0x140
[ 332.838612] show_stack+0x14/0x20
[ 332.838613] dump_stack+0xb4/0xf8
[ 332.838617] panic+0x158/0x324
[ 332.838618] nmi_panic+0x84/0x88
[ 332.838621] arm64_serror_panic+0x74/0x80
[ 332.838622] do_serror+0x80/0x138
[ 332.838623] el1_error+0x84/0xf8
[ 332.838627] regcache_sync_block+0x7c/0x258
[ 332.838628] regcache_rbtree_sync+0x60/0xb0
[ 332.838629] regcache_sync+0xac/0x140
[ 332.838633] disable_hwvad+0x3c/0x1f0
[ 332.838634] micfil_hwvad_handler+0x78/0x170
[ 332.838635] kobj_attr_store+0x14/0x28
[ 332.838637] sysfs_kf_write+0x40/0x50
[ 332.838640] kernfs_fop_write+0xf8/0x210
[ 332.838641] __vfs_write+0x18/0x40
[ 332.838642] vfs_write+0xdc/0x1c8
[ 332.838646] ksys_write+0x68/0xf0
[ 332.838647] __arm64_sys_write+0x18/0x20
[ 332.838648] el0_svc_common.constprop.0+0x68/0x160
[ 332.838651] el0_svc_handler+0x20/0x80
[ 332.838653] el0_svc+0x8/0xc
[ 332.838972] SMP: stopping secondary CPUs
[ 332.838974] Kernel Offset: disabled
[ 332.838975] CPU features: 0x0002,2000200c
[ 332.838976] Memory Limit: none
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
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The call flow:
devm_regmap_init_mmio_clk
- clk_prepare()
- clk_pm_runtime_get()
Cause the power domain of ipg clock always be enabled.
which impact the power consumption.
so we can't bind clock with regmap, but explicitly enable
clock when using.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
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The new features are:
1. The output is 24 more significative bits in 32bit slot
2. The fifo depth is 32 entries.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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With the case below, there is issue that after recording with
8 channels, the recording of 1 channel will fail.
arecord -Dhw:2,0 -r 32000 -f S16_LE -c 8 -d 5 -t raw /tmp/test1.pcm
arecord -Dhw:2,0 -r 32000 -f S16_LE -c 1 -d 5 -t raw /tmp/test2.pcm
arecord: pcm_read:2143: read error: Input/output error
The reason is that we need to reset channel output data Flag before
we start the recording
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 45ea3acd0c0c67a7b33faee9818401c6fbcc8c96)
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Merge the changes from imx_4.19.y
The top commit is:
b5472e3f3dd1 ("MLK-21775-4: ASoC: fsl_micfil: synchronize HWVAD enable/disable")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Fixes gcc '-Wunused-but-set-variable' warning:
sound/soc/fsl/fsl_micfil.c: In function 'get_clk_div':
sound/soc/fsl/fsl_micfil.c:154:6: warning: variable 'osr' set but not used [-Wunused-but-set-variable]
It is never used since introduction in
commit 47a70e6fc9a8 ("ASoC: Add MICFIL SoC Digital Audio Interface driver.")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add Digital Audio Interface driver that convers PDM bitstream to PCM
format.
Features:
- Fixed filtering characteristics for audio application.
- Full or partial set of channels operation with individual enable control.
- Programmable PDM clock generator.
- Programmable decimation rate.
- 16-bit signed output result.
- Overall stopband attenuation more than 80dB.
- Overall passband ripple less than 0.2dB.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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