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2021-04-21fsl_sai: work around missing MCLK on i.mx 8m plusMax Krummenacher
Some audio codecs need the MCLK during setup of the codec, however for the i.MX 8M Plus it is gated with the bce bit. So enable the bit already in fsl_sai_hw_params() which is an early state when initalizing sai and codec. Notably the WM8904 codec on the Dahlia carrier board is affected. Fixes a timeout on audio start: root@verdin-imx8mp:~# aplay sound/Gong.wav [ 1356.402716] wm8904 3-001a: DC servo timed out [ 1362.410401] wm8904 3-001a: DC servo timed out Playing WAVE 'sound/Gong.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo Related-to: ELB-3554 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-01-11Merge tag 'v5.4.73' into 5.4-2.3.x-imxAndrey Zhizhikin
This is the 5.4.73 stable release Conflicts: - arch/arm/boot/dts/imx6sl.dtsi: Commit [a1767c90194e2] in NXP tree is now covered with commit [5c4c2f437cead] from upstream. - drivers/gpu/drm/mxsfb/mxsfb_drv.c: Resolve merge hunk for patch [ed8b90d303cf0] from upstream - drivers/media/i2c/ov5640.c: Patch [aa4bb8b8838ff] in NXP tree is now covered by patches [79ec0578c7e0a] and [b2f8546056b35] from upstream. Changes from NXP patch [99aa4c8c18984] are covered in upstream version as well. - drivers/net/ethernet/freescale/fec_main.c: Fix merge fuzz for patch [9e70485b40c83] from upstream. - drivers/usb/cdns3/gadget.c: Keep NXP version of the file, upstream version is not compatible. - drivers/usb/dwc3/core.c: - drivers/usb/dwc3/core.h: Fix merge fuzz of patch [08045050c6bd2] together wth NXP patch [b30e41dc1e494] - sound/soc/fsl/fsl_sai.c: - sound/soc/fsl/fsl_sai.h: Commit [2ea70e51eb72a] in NXP tree is now covered with commit [1ad7f52fe6683] from upstream. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2020-10-29ASoC: fsl_sai: Instantiate snd_soc_dai_driverShengjiu Wang
[ Upstream commit 22a16145af824f91014d07f8664114859900b9e6 ] Instantiate snd_soc_dai_driver for independent symmetric control. Otherwise the symmetric setting may be overwritten by other instance. Fixes: 08fdf65e37d5 ("ASoC: fsl_sai: Add asynchronous mode support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1600424760-32071-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASKShengjiu Wang
[ Upstream commit 5aef1ff2397d021f93d874b57dff032fdfac73de ] The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on i.MX7ULP. Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for these platform, the FIFO watermark mask should be updated according to the fifo_depth. Fixes: a860fac42097 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-05-27MLK-24175: ASoC: fsl_sai: instantiate snd_soc_dai_driverShengjiu Wang
instantiate snd_soc_dai_driver for independent symmetric control. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2020-05-01MLK-23618-17: fsl_sai: fix hang in probe at boot timeViorel Suman
A power domain associated with a device may be disabled in a separate thread by "genpd_power_off_work_fn" function in case the device has no PM runtime enabled at that moment. This will stop the parent clock of "bus" clk and hang the probe in regmap read/write operation. In order to avoid this PM runtime must be enabled before any regmap read/write ops. Aside of this replace clk bus clocks with pm_runtime_get/put_sync calls. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Fixes: c2641e1974f7 ("MLK-23618-9: ASoC: fsl_sai: Don't bind clock with regmap") Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2020-04-17MLK-23792-1: ASoC: fsl_sai: Monitor spdif rx clock in imx8mmShengjiu Wang
As we use one spare sai instance to monitor the spdif rx clock, there isn't belong to a sound card, we can't access the registers by amixer controls. So remove the amixer controls, replace them with the device attribute. And add an additional device attribute for enablement of monitorring spdif. This feature only be supported on imx8mm. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2020-03-18MLK-23618-9: ASoC: fsl_sai: Don't bind clock with regmapShengjiu Wang
The call flow: devm_regmap_init_mmio_clk - clk_prepare() - clk_pm_runtime_get() Cause the power domain of lpcg clock always be enabled. which impact the power consumption. So we can't bind clock with regmap, then explicitly enable clock when using. As we already enable all clock in pm_runtime_resume, so only need to enable clock in probe. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2020-03-18MLK-23618-1: Revert "ASoC: fsl_sai: support multi power domain"Shengjiu Wang
This reverts commit 53915e7ea973851a5d9b60681a2718bbdeb5439e. The power domain of clock should be controlled by clock driver, We don't need to control it in audio driver, so we don't need to support multi power domain in audio driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2020-02-28ASoC: fsl_sai: Fix exiting path on probing failureOleksandr Suvorov
commit d1520889782dff58610c0b6b54d4cf3211ceb690 upstream. If the imx-sdma driver is built as a module, the fsl-sai device doesn't disable on probing failure, which causes the warning in the next probing: ================================================================== fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! ================================================================== Disabling the device properly fixes the issue. Fixes: 812ad463e089 ("ASoC: fsl_sai: Add support for runtime pm") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Link: https://lore.kernel.org/r/20200205160436.3813642-1-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-20MLK-23242-4: ASoC: fsl_sai: Add support for imx8mpShengjiu Wang
In imx8mp there is audiomix power domains, and only one power domain, that we don't need to call dev_pm_domain_attach_by_id, which should return the EEXIST. And we need to enable the MCLK output even it is in slave mode. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-12-10MLK-21957-3: ASoC: fsl_sai: add bitcount and timestamp controlsViorel Suman
Bitcount and timestamp support added in SAI IP recently. Add the related controls in SAI driver. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-12-10MLK-22522: ASoC: fsl_sai: fix stack-out-of-bounds KASAN complainViorel Suman
Fix the following KASAN reported issue: ================================================================== [ 11.580278] BUG: KASAN: stack-out-of-bounds in find_next_bit+0x3c/0xc0 [ 11.586815] Read of size 8 at addr ffffffc8c8d4f760 by task swapper/0/1 [ 11.593440] [ 11.594943] CPU: 4 PID: 1 Comm: swapper/0 Tainted: G W 4.19.35-05042-g. #157 [ 11.604259] Hardware name: Freescale i.MX8QM MEK (DT) [ 11.609323] Call trace: [ 11.611785] dump_backtrace+0x0/0x230 [ 11.615458] show_stack+0x14/0x20 [ 11.618787] dump_stack+0xbc/0xf4 [ 11.622118] print_address_description+0x60/0x270 [ 11.626830] kasan_report+0x230/0x360 [ 11.630505] __asan_load8+0x84/0xa8 [ 11.634005] find_next_bit+0x3c/0xc0 [ 11.637595] fsl_sai_calc_dl_off+0x1c/0x50 [ 11.641703] fsl_sai_read_dlcfg+0x184/0x368 [ 11.645898] fsl_sai_probe+0x3ec/0xb48 [ 11.649663] platform_drv_probe+0x70/0xd8 [ 11.653683] really_probe+0x24c/0x370 [ 11.657358] driver_probe_device+0x70/0x138 [ 11.661554] __driver_attach+0x124/0x128 [ 11.665489] bus_for_each_dev+0xe8/0x158 [ 11.669425] driver_attach+0x30/0x40 [ 11.673012] bus_add_driver+0x290/0x308 [ 11.676861] driver_register+0xbc/0x1d0 [ 11.680711] __platform_driver_register+0x7c/0x88 [ 11.685431] fsl_sai_driver_init+0x18/0x20 [ 11.689537] do_one_initcall+0xe8/0x5a8 [ 11.693387] kernel_init_freeable+0x6b0/0x760 [ 11.697759] kernel_init+0x10/0x120 [ 11.701255] ret_from_fork+0x10/0x18 .... ================================================================== [ 11.800186] Disabling lock debugging due to kernel taint Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-12-10MLK-21957-2: ASoC: fsl_sai: read SAI version and params in probeViorel Suman
Read SAI IP version and parameters in probe function. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-12-10MLK-21957-1: ASoC: fsl_sai: remove reset code from dai_probeViorel Suman
SAI software reset is done in runtime resume, there is no need to do it in fsl_sai_dai_probe. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-12-10MLK-21484-4: ASoC: fsl_sai: ensure clk not in use prior set_mclk_rateViorel Suman
On recent kernels clks which are marked with CLK_SET_RATE_GATE are "protected" against further changes at clk_prepare time, including clk set_parent and set_rate. See commit 9461f7b33d11 ("clk: fix CLK_SET_RATE_GATE with clock rate protection"). The current fsl_sai implementation ensures the clock is not in use prior set_parent, extend this for set_rate also by moving if (sai->mclk_streams == 0) outside fsl_sai_set_mclk_rate(). Aside of this avoid changing rate and parent for BUS clk. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25LF-106: ASoC: fsl_sai: request BUS_FREQ_AUDIOShengjiu Wang
request BUS_FREQ_AUDIO Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25ASoC: fsl_sai: Mark cache dirty at resumeDaniel Baluta
This is needed so that at resume will restore the correct SAI registers. Looks like the call to regcache_mark_dirty was missed when porting commit 760bd6187413e37c8 ("MLK-15960-2: ASoC: fsl_sai: refine the pm runtime function") Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-21876-4 ASoC: fsl: sai: fix build for next-20190524 upgradeDong Aisheng
In file included from ../sound/soc/fsl/fsl_sai.c:15:0: ../sound/soc/fsl/fsl_sai.c: In function ‘fsl_sai_startup’: ../sound/soc/fsl/fsl_sai.c:957:51: error: ‘offset’ undeclared (first use in this function) regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset), ^ ../include/linux/regmap.h:77:31: note: in definition of macro ‘regmap_update_bits’ regmap_update_bits_base(map, reg, mask, val, NULL, false, false) ^ ../sound/soc/fsl/fsl_sai.h:84:37: note: in expansion of macro ‘FSL_SAI_TCR3’ #define FSL_SAI_xCR3(tx, off) (tx ? FSL_SAI_TCR3(off) : FSL_SAI_RCR3(off)) ^ ../sound/soc/fsl/fsl_sai.c:957:34: note: in expansion of macro ‘FSL_SAI_xCR3’ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset), ^ ../sound/soc/fsl/fsl_sai.c:957:51: note: each undeclared identifier is reported only once for each function it appears in regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset), ^ ../include/linux/regmap.h:77:31: note: in definition of macro ‘regmap_update_bits’ regmap_update_bits_base(map, reg, mask, val, NULL, false, false) ^ ../sound/soc/fsl/fsl_sai.h:84:37: note: in expansion of macro ‘FSL_SAI_TCR3’ #define FSL_SAI_xCR3(tx, off) (tx ? FSL_SAI_TCR3(off) : FSL_SAI_RCR3(off)) ^ ../sound/soc/fsl/fsl_sai.c:957:34: note: in expansion of macro ‘FSL_SAI_xCR3’ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset), Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-11-25ASoC: fsl: sai: fix build failture due to 5.1 RC7 upgradeDong Aisheng
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-11-25ASoC: fsl_sai: support multi power domainShengjiu Wang
support multi power domain Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25ASoC: fsl_sai: Support -EPROBE_DEFERShengjiu Wang
Support -EPROBE_DEFER for the resource is not ready in time Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-20328-1: ASoC: fsl_sai: map number of pins to dataline masksViorel Suman
The patch enable mapping the number of pins required to play or record a specific number of channels to a specific dataline mask. Three consequent elements in "fsl,dataline" and "fsl,dataline,dsd" defines a particular mapping, for instance for: fsl,dataline = "0 0xff 0xff 2 0x11 0x11" there are two mappings defined: default (0 pins) "rx" and "tx" dataline masks: 0 0xff 0xff 2 pins "rx" and "tx" dataline masks: 2 0x11 0x11 In case if property is missing, then default value "0 0x1 0x1" is considered. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-20189-8: ASoC: fsl_sai: use signed offset variableViorel Suman
Both dataline_off and dataline_off_dsd fields are unsigned, thus checking negative values make no sense. Use a signed variable to calculate offset instead. This fixes Coverity issue: CID1899299 Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-15975-3: ASoC: fsl_sai: The offset of fifo_off is changedShengjiu Wang
Commit 786c8bd56324 ("MLK-19734-3: dmaengine: imx-sdma: change fifo offset of fifo_num") change the offset of fifo_off, so the sai driver need to be updated. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit c94ce8776e01f1f40a866d4da89603ab042dde0f)
2019-11-25MLK-18898-1: ASoC: fsl_sai: select pinctrl state as function of bitclock rateViorel Suman
Similar to DSD512 case we need a PCM pinctrl state option to map SAI BCLK to codec MCLK pin. Given that bitclock rate is function of slots number and slot width - pass bclk rate as parameter value from SAI driver. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> (cherry picked from commit 826caeae32713cff7ad50de8ebc9915de975edd9)
2019-11-25MLK-18947: ASoC: fsl_sai: fix volatile functionShengjiu Wang
The FSL_SAI_VERID and FSL_SAI_PARAM only available when reg_offset is 8 Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit 0a0695672dc7ecf07a7642ff6f99f0b9d3a26b32)
2019-11-25MLK-18682-2: ASoC: fsl: sai: allow dynamic pll switchingViorel Suman
Currently SAI master clock derives from an audio pll that cannot be changed at runtime. iMX8 SoC has 2 audio plls usually configured to support either 8000Hz (8k,16k,32k,48k,etc) or 11025Hz (11k,22k,44.1k,88.2k,etc) ranges of rates - thus at runtime a SAI interface is able to play only one range of rates. The patch allows dynamic SAI master clock reparenting to the appropriate audio pll as function of the audio stream rate to be played/recorded. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-18682-1: ASoC: fsl: sai: use set_bclk_ratio to calculate BCLK freq (part 1)Viorel Suman
ALSA API has a standard way to configure DAI BCLK by calling "snd_soc_dai_set_bclk_ratio" function. So use it to set BCLK ratio and calculate SAI BCLK frequency. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> [ Aisheng: split machine imx-pdm changes ] Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-11-25MLK-18534-1: ASoC: fsl: sai: introduce 1:1 bclk:mclk ratio supportViorel Suman
Since IP version 3.01 (845s) SAI has support for 1:1 bclk:mclk ratio. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-17531-1: ASoC: fsl: sai: add support for SAI v3.01Viorel Suman
a) Add support for new SAI (VERID, PARAM, MCTL, MDIV) registers available in i.MX 850d (SAI v3.00) and i.MX 845s (SAI v3.01). b) Handle SAI MCLK register as function of SAI IP version. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17580: ASoC: fsl: sai: check for pinctrl statusViorel Suman
For some cases (like AMIX) pinctrl may be null - this breaks SAI functionality. Enforce pinctrl null pointer checking prior calling any function which involves pins state changes. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-17580: ASoC: fsl: sai: Use DSD helperViorel Suman
Replace DSD related code with calls to DSD helper functions. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com
2019-11-25Sound: Soc: fsl: Set SAI Channel Mode to Output ModeCosmin-Gabriel Samoila
Transmit data pins will output zero when slots are masked or channels are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. When data pins are tri-stated, there is noise on some channels when FS clock value is high and data is read while fsclk is transitioning from high to low. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-17156-1: ASoC: fsl_sai: update register offset for ULP B0Shengjiu Wang
ULP B0 integrate the latest SAI IP, there is version id and parameter id register in the beginning, so update the offset for ULP B0 Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17528-3: ASoC: fsl_sai: Set clock rate in "set_sysclk" APIViorel Suman
Set the requested clock rate in "set_sysclk" for specified clock id. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17528-1: ASoC: fsl_sai: Introduce FSL_SAI_CLK_BIT clock idViorel Suman
Introduce FSL_SAI_CLK_BIT clock id in order to distinguish the bit clock and master clocks in "set_sysclk" API. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17566: ASoC: fsl_sai: fix register definitionShengjiu Wang
The register definition is not completed for SAI support 8 transmit data register and 8 receive data register. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17485: ASoC: fsl_sai: Specify supported rate_min and rate_maxDaniel Baluta
Because fsl_sai_dai rates doesn't have a specific set of rate values (.rates = SNDRV_PCM_RATE_KNOT) we need to provide rate_min and rate_max otherwise functions trying to get supported parameters will get confused and return an error. Fixes: 1b6f0496e013 ("MLK-17428-8: ASoC: fsl_sai: support 768KHz sample rate") Reviewed-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17428-8: ASoC: fsl_sai: support 768KHz sample rateShengjiu Wang
support 768Hz sample rate and 2.8MHz for DSD Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-16224-6: ASoC: fsl_sai: fix DSD suspend/resumeViorel Suman
With the existing implementation the SAI pinctrl state is restored to default after resume - this breaks DSD playback after resume. Restore DSD pinctrl state in snd_soc_dai_driver resume callback. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-17467: ASoC: fsl_sai: fix typo for fsl_saiShengjiu Wang
Fix build warning sound/soc/fsl/fsl_sai.c: In function ‘fsl_sai_trigger’: sound/soc/fsl/fsl_sai.c:736:3: warning: this ‘while’ clause does not guard... [-Wmisleading-indentation] while (tx && i < channels) ^~~~~ sound/soc/fsl/fsl_sai.c:742:4: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘while’ j++; ^ Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-16224-4: ASoC: fsl_sai: support multi fifo and DSDShengjiu Wang
The codec always mux the LRCLK pin to DSD data line, so when we want to support DSD, the pinmux is different. For two channel DSD, the DSDL is mapped to TX0, but the DSDR is mapped to TX4, there is address offset for the fifo address of TX0 and TX4, TX4's fifo is not adjacent to TX0's. Usually, if mapping is TX0 and TX1, that will be easy for SAI and SDMA to handle, that SAI can use the FIFO combine mode, SDMA can use the normal script. so for DSD: 1. The SDMA should use the multi-fifo script, and SAI can't use the FIFO combine mode. 2. driver should to check the dts configuration(fsl,dataline) for which dataline is used corrently 3. maxburst is the multiply of datalines 4. each channel of DSD occupy one data lane 5. according to data lane, set TRCE bits Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-17442: ASoC: fsl: fix wrong usage of filter_data (part 1)Shengjiu Wang
The filter_data should be used for dma_filter_fn function, but we used the filter_data wrongly for dma channel name. This patch is to fix the issue. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviwed-by: Daniel Baluta <daniel.baluta@nxp.com> [ Aisheng: split out esai and pcm changes ] Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-11-25MLK-16929-1: ASoC: fsl_sai: add bitclk_freqShengjiu Wang
Allow set SAI bit clock frequency trough snd_soc_dai_set_sysclk function call on machine sound drivers. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
2019-11-25MLK-13946-8: ASoC: fsl_sai: use min(channels,slots) for xMR settingViorel Suman
xMR setting must be set as min(channels,slots) since both "channels < slots" and "channels > slots" scenarios are possible. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-13946-3: ASoC: fsl_sai: fix the xMR settingShengjiu Wang
When there is multi data line enabled, the xMR setting is wrong if according to the channel number. which should according to the slot number Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-16130-1: ASoC: fsl_sai: enable TCE/RCE according to input channelsShengjiu Wang
If there is only two channels input and slots is 2, then enable one port is enough for data transfer. so enable the TCE/RCE according to the input channels and slots configuration. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2019-11-25MLK-13975: ASoC: fsl_sai: Refine master flag handlingViorel Suman
The patch introduces the master flag handling as function of direction and the option to provide the flag value from DTS. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-15960-2: ASoC: fsl_sai: refine the pm runtime functionShengjiu Wang
In imx8qm/imx8qxp, the power domain of IP is enabled when pm_runtime_get_sync() is called, and disabled when pm_runtime _put_sync() is called. when power domain is disabled, the value of registers will lost, so we need to use the regcache_sync() to restore the registers in fsl_sai_runtime_resume. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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