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path: root/sound/soc/fsl/fsl_sai.h
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2021-04-21fsl_sai: work around missing MCLK on i.mx 8m plusMax Krummenacher
Some audio codecs need the MCLK during setup of the codec, however for the i.MX 8M Plus it is gated with the bce bit. So enable the bit already in fsl_sai_hw_params() which is an early state when initalizing sai and codec. Notably the WM8904 codec on the Dahlia carrier board is affected. Fixes a timeout on audio start: root@verdin-imx8mp:~# aplay sound/Gong.wav [ 1356.402716] wm8904 3-001a: DC servo timed out [ 1362.410401] wm8904 3-001a: DC servo timed out Playing WAVE 'sound/Gong.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo Related-to: ELB-3554 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-01-11Merge tag 'v5.4.73' into 5.4-2.3.x-imxAndrey Zhizhikin
This is the 5.4.73 stable release Conflicts: - arch/arm/boot/dts/imx6sl.dtsi: Commit [a1767c90194e2] in NXP tree is now covered with commit [5c4c2f437cead] from upstream. - drivers/gpu/drm/mxsfb/mxsfb_drv.c: Resolve merge hunk for patch [ed8b90d303cf0] from upstream - drivers/media/i2c/ov5640.c: Patch [aa4bb8b8838ff] in NXP tree is now covered by patches [79ec0578c7e0a] and [b2f8546056b35] from upstream. Changes from NXP patch [99aa4c8c18984] are covered in upstream version as well. - drivers/net/ethernet/freescale/fec_main.c: Fix merge fuzz for patch [9e70485b40c83] from upstream. - drivers/usb/cdns3/gadget.c: Keep NXP version of the file, upstream version is not compatible. - drivers/usb/dwc3/core.c: - drivers/usb/dwc3/core.h: Fix merge fuzz of patch [08045050c6bd2] together wth NXP patch [b30e41dc1e494] - sound/soc/fsl/fsl_sai.c: - sound/soc/fsl/fsl_sai.h: Commit [2ea70e51eb72a] in NXP tree is now covered with commit [1ad7f52fe6683] from upstream. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2020-10-29ASoC: fsl_sai: Instantiate snd_soc_dai_driverShengjiu Wang
[ Upstream commit 22a16145af824f91014d07f8664114859900b9e6 ] Instantiate snd_soc_dai_driver for independent symmetric control. Otherwise the symmetric setting may be overwritten by other instance. Fixes: 08fdf65e37d5 ("ASoC: fsl_sai: Add asynchronous mode support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1600424760-32071-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-08Merge tag 'v5.4.70' into imx_5.4.yJason Liu
* tag 'v5.4.70': (3051 commits) Linux 5.4.70 netfilter: ctnetlink: add a range check for l3/l4 protonum ep_create_wakeup_source(): dentry name can change under you... ... Conflicts: arch/arm/mach-imx/pm-imx6.c arch/arm64/boot/dts/freescale/imx8mm-evk.dts arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts drivers/crypto/caam/caamalg.c drivers/gpu/drm/imx/dw_hdmi-imx.c drivers/gpu/drm/imx/imx-ldb.c drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c drivers/mmc/host/sdhci-esdhc-imx.c drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c drivers/net/ethernet/freescale/enetc/enetc.c drivers/net/ethernet/freescale/enetc/enetc_pf.c drivers/thermal/imx_thermal.c drivers/usb/cdns3/ep0.c drivers/xen/swiotlb-xen.c sound/soc/fsl/fsl_esai.c sound/soc/fsl/fsl_sai.c Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
2020-08-19ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASKShengjiu Wang
[ Upstream commit 5aef1ff2397d021f93d874b57dff032fdfac73de ] The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on i.MX7ULP. Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for these platform, the FIFO watermark mask should be updated according to the fifo_depth. Fixes: a860fac42097 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-05-27MLK-24175: ASoC: fsl_sai: instantiate snd_soc_dai_driverShengjiu Wang
instantiate snd_soc_dai_driver for independent symmetric control. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2020-04-17MLK-23792-1: ASoC: fsl_sai: Monitor spdif rx clock in imx8mmShengjiu Wang
As we use one spare sai instance to monitor the spdif rx clock, there isn't belong to a sound card, we can't access the registers by amixer controls. So remove the amixer controls, replace them with the device attribute. And add an additional device attribute for enablement of monitorring spdif. This feature only be supported on imx8mm. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-12-10MLK-21957-3: ASoC: fsl_sai: add bitcount and timestamp controlsViorel Suman
Bitcount and timestamp support added in SAI IP recently. Add the related controls in SAI driver. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-20328-1: ASoC: fsl_sai: map number of pins to dataline masksViorel Suman
The patch enable mapping the number of pins required to play or record a specific number of channels to a specific dataline mask. Three consequent elements in "fsl,dataline" and "fsl,dataline,dsd" defines a particular mapping, for instance for: fsl,dataline = "0 0xff 0xff 2 0x11 0x11" there are two mappings defined: default (0 pins) "rx" and "tx" dataline masks: 0 0xff 0xff 2 pins "rx" and "tx" dataline masks: 2 0x11 0x11 In case if property is missing, then default value "0 0x1 0x1" is considered. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-18682-2: ASoC: fsl: sai: allow dynamic pll switchingViorel Suman
Currently SAI master clock derives from an audio pll that cannot be changed at runtime. iMX8 SoC has 2 audio plls usually configured to support either 8000Hz (8k,16k,32k,48k,etc) or 11025Hz (11k,22k,44.1k,88.2k,etc) ranges of rates - thus at runtime a SAI interface is able to play only one range of rates. The patch allows dynamic SAI master clock reparenting to the appropriate audio pll as function of the audio stream rate to be played/recorded. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-18682-1: ASoC: fsl: sai: use set_bclk_ratio to calculate BCLK freq (part 1)Viorel Suman
ALSA API has a standard way to configure DAI BCLK by calling "snd_soc_dai_set_bclk_ratio" function. So use it to set BCLK ratio and calculate SAI BCLK frequency. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> [ Aisheng: split machine imx-pdm changes ] Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2019-11-25MLK-18534-1: ASoC: fsl: sai: introduce 1:1 bclk:mclk ratio supportViorel Suman
Since IP version 3.01 (845s) SAI has support for 1:1 bclk:mclk ratio. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-17531-1: ASoC: fsl: sai: add support for SAI v3.01Viorel Suman
a) Add support for new SAI (VERID, PARAM, MCTL, MDIV) registers available in i.MX 850d (SAI v3.00) and i.MX 845s (SAI v3.01). b) Handle SAI MCLK register as function of SAI IP version. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17580: ASoC: fsl: sai: Use DSD helperViorel Suman
Replace DSD related code with calls to DSD helper functions. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com
2019-11-25Sound: Soc: fsl: Set SAI Channel Mode to Output ModeCosmin-Gabriel Samoila
Transmit data pins will output zero when slots are masked or channels are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. When data pins are tri-stated, there is noise on some channels when FS clock value is high and data is read while fsclk is transitioning from high to low. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-17528-1: ASoC: fsl_sai: Introduce FSL_SAI_CLK_BIT clock idViorel Suman
Introduce FSL_SAI_CLK_BIT clock id in order to distinguish the bit clock and master clocks in "set_sysclk" API. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-17566: ASoC: fsl_sai: fix register definitionShengjiu Wang
The register definition is not completed for SAI support 8 transmit data register and 8 receive data register. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25MLK-16224-4: ASoC: fsl_sai: support multi fifo and DSDShengjiu Wang
The codec always mux the LRCLK pin to DSD data line, so when we want to support DSD, the pinmux is different. For two channel DSD, the DSDL is mapped to TX0, but the DSDR is mapped to TX4, there is address offset for the fifo address of TX0 and TX4, TX4's fifo is not adjacent to TX0's. Usually, if mapping is TX0 and TX1, that will be easy for SAI and SDMA to handle, that SAI can use the FIFO combine mode, SDMA can use the normal script. so for DSD: 1. The SDMA should use the multi-fifo script, and SAI can't use the FIFO combine mode. 2. driver should to check the dts configuration(fsl,dataline) for which dataline is used corrently 3. maxburst is the multiply of datalines 4. each channel of DSD occupy one data lane 5. according to data lane, set TRCE bits Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-16929-1: ASoC: fsl_sai: add bitclk_freqShengjiu Wang
Allow set SAI bit clock frequency trough snd_soc_dai_set_sysclk function call on machine sound drivers. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
2019-11-25MLK-13946-3: ASoC: fsl_sai: fix the xMR settingShengjiu Wang
When there is multi data line enabled, the xMR setting is wrong if according to the channel number. which should according to the slot number Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-13975: ASoC: fsl_sai: Refine master flag handlingViorel Suman
The patch introduces the master flag handling as function of direction and the option to provide the flag value from DTS. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-15927-1: ASoC: fsl_sai: Fix noise when using EDMAMihai Serban
EDMA requires the period size to be multiple of maxburst. Otherwise the remaining bytes are not transferred and thus noise is produced. We can handle this issue by adding a constraint on SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value. This is based on a similar patch we have for ESAI: commit bd3f3eb2a37c ("MLK-15109-2: ASoC: fsl_esai: add constrain_period_size") Signed-off-by: Mihai Serban <mihai.serban@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-15140-1: ASoC: fsl_sai: support latest sai moduleShengjiu Wang
The version of sai is upgrate in imx8mq, which add two register in beginning, there is VERID and PARAM. the driver need to be update Signed-off-by: Mihai Serban <mihai.serban@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2019-11-25MLK-14870: ASoC: fsl_sai: Remove support for S20_3LEDaniel Baluta
With current clock configuration we cannot derive bitclk for S20_3LE format in SAI master mode. There was an attempt to fix this in commit 65e6b5f1b4a7 ("MLK-14536: ASoC: wm8960: Fix playback in CPU DAI master mode") but this broke codec-master mode, thus the patch was partially reverted in 96f0d36e420 ("MLK-14798: arm: dts: imx6ul: Fix wm8960 codec master mode") So, remove S20_3LE support for SAI master mode. Clients using this feature should use codec master mode, which is the default one in the dts anyway. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-11-25ASoC: fsl_sai: set specific fmt for I2S XTORViorel Suman
Set specific fmt, for i2s xtor receiver is in slave mode and i2s xtor transmitter is in master mode. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25ASoC: fsl_sai: handle slave mode per TX/RX directionViorel Suman
The SAI interface can be a clock supplier or consummer as function of stream direction, ie when interacting with I2S XTOR. Removed FSL_SAI_RFR define as it is now referred as FSL_SAI_RFR0. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-25MLK-13574-2: ASoC: fsl_sai: refine driver for ip upgradeShengjiu Wang
In imx7ulp1, the sai can support two TX channel and two RX channels, So the usage need to be updated. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2019-11-25MLK-10611-1 ASoC: fsl-sai: Just one device can playback(captrue) when using ↵Zidan Wang
the same SAI Just one device can playback(captrue) when using the same SAI. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> (cherry picked from commit 7981a488c4da440db21f0544b519b44636a0cabb)
2019-11-25Revert "ASoC: fsl_sai: add of_match data"Dong Aisheng
This reverts commit 89c9679f699d88986ce552738dc7c5c500c8fc67.
2019-11-25Revert "ASoC: fsl_sai: derive TX FIFO watermark from FIFO depth"Dong Aisheng
This reverts commit bd517707d85f19a7339ea8b882fcbf0fd9976bd6.
2019-11-25Revert "ASoC: fsl_sai: Add registers definition for multiple datalines"Dong Aisheng
This reverts commit 5f0ac20ed6db1d6da2eea8b862cf3d54fdfb5830.
2019-11-25Revert "ASoC: fsl_sai: Update Tx/Rx channel enable mask"Dong Aisheng
This reverts commit b84f50b0fcb497a62068926fca793d2d213c7dbd.
2019-11-25Revert "ASoC: fsl_sai: Add support for SAI new version"Dong Aisheng
This reverts commit 4f7a0728b5305e2d865f543fbcffd617e03c7674.
2019-11-25Revert "ASoC: fsl_sai: Implement set_bclk_ratio"Leonard Crestez
This reverts commit 63d1a3488ff58e094a7f517cf93c0250f0a3f6be.
2019-11-25Revert "ASoC: fsl_sai: Fix noise when using EDMA"Leonard Crestez
This reverts commit e75f4940e8ad0dd76527302a10c06b58bf7eb590.
2019-09-17ASoC: fsl_sai: Fix noise when using EDMAMihai Serban
EDMA requires the period size to be multiple of maxburst. Otherwise the remaining bytes are not transferred and thus noise is produced. We can handle this issue by adding a constraint on SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value. Signed-off-by: Mihai Serban <mihai.serban@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190913192807.8423-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-13ASoC: fsl_sai: Implement set_bclk_ratioViorel Suman
This is to allow machine drivers to set a certain bitclk rate which might not be exactly rate * frame size. Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190830215910.31590-1-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add support for SAI new versionDaniel Baluta
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature. VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table: Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8. SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1]. In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf Signed-off-by: Mihai Serban <mihai.serban@nxp.com> [initial coding in the NXP internal tree] Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> [bugfixing and cleanups] Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> [adapted to linux-next] Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-4-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Update Tx/Rx channel enable maskDaniel Baluta
Tx channel enable (TCE) / Rx channel enable (RCE) bits enable corresponding data channel for Tx/Rx operation. Because SAI supports up the 8 channels TCE/RCE occupy up the 8 bits inside TCR3/RCR3 registers we need to extend the mask to reflect this. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-3-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add registers definition for multiple datalinesDaniel Baluta
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time. This patch adds definitions for all related data TX/RX registers: * TDR0..7, Transmit data register * TFR0..7, Transmit FIFO register * RDR0..7, Receive data register * RFR0..7, Receive FIFO register Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: derive TX FIFO watermark from FIFO depthLucas Stach
The DMA request schould be triggered as soon as the FIFO has space for another burst. As different versions of the SAI block have different FIFO sizes, the watrmark level needs to be derived from version specific data. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Link: https://lore.kernel.org/r/20190717105635.18514-3-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: add of_match dataLucas Stach
New revisions of the SAI IP block have even more differences that need be taken into account by the driver. To avoid sprinking compatible checks all over the driver move the current differences into of_match_data. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190717105635.18514-2-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-03ASoC: fsl_sai: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-25ASoC: fsl_sai: add tdm slots operation supportZidan Wang
Add tdm slots operation support. If tdm slots and slot width have been configured in machine driver, we should use these values. Otherwise, using relevant channels and word length to set slots and slot width. SAI will generate BCLK depends on sample rate, slots and slot width. And there may be unused BCLK cycles before each LRCLK transition. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-30Merge remote-tracking branches 'asoc/topic/fsi', 'asoc/topic/fsl', ↵Mark Brown
'asoc/topic/fsl-asrc', 'asoc/topic/fsl-card' and 'asoc/topic/fsl-sai' into asoc-next
2015-08-12ASoC: fsl: fix typos for sound/soc/fsl/*Xiubo Li
There are too much noise about the typos for fsl's drivers. So I fix all the typos here in this patch in almost every file I touched. Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-11ASoC: fsl-sai: add 32 bit word length supportZidan Wang
Add 32 bit word length support. There are no code changes required in the SAI driver since it has already wirten the word width to the corresponding register. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-05-12ASoC: fsl_sai: add sai master mode supportZidan Wang
When sai works on master mode, set its bit clock and frame clock. SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk will select proper MCLK source, then calculate and set the bit clock divider. After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add hw_free() to disable the mclk. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-01ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.Xiubo Li
The 'big-endian-data' property is originally used to indicate whether the LSB firstly or MSB firstly will be transmitted to the CODEC or received from the CODEC, and there has nothing relation to the memory data. Generally, if the audio data in big endian format, which will be using the bytes reversion, Here this can only be used to bits reversion. So using the 'lsb-first' instead of 'big-endian-data' can make the code to be readable easier and more easy to understand what this property is used to do. This property used for configuring whether the LSB or the MSB is transmitted first for the fifo data. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-01Merge branch 'topic/fsl' of ↵Mark Brown
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-fsl-sai
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