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path: root/sound/soc/fsl/fsl_spdif.h
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2020-05-08ASoC: fsl_spdif: add support for 88200 and 176400 ratesViorel Suman
Add support for 88200 Hz and 17600 Hz. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-11-25MLK-19115-2: ASoC: fsl_spdif: add support for enabling raw capture modeViorel Suman
Since i.MX8 MQ SPDIF interface is able to capture raw data. Add support in SPDIF driver for this functionality. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> (cherry picked from commit e13a302391f56a6bb547ff89e3fac73941cee429)
2019-02-18ASoC: fsl_spdif: fix TXCLK_DF maskViorel Suman
According to RM SPDIF TXCLK_DF mask is 7-bit wide. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-03ASoC: fsl_spdif: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-06-17ASoC: fsl_spdif: Add support for output sample rates 96kHz and 192kHzAnssi Hannula
Add support for the output sample rates 96kHz and 192kHz. Tested with a Cubox-i imx6 system and an Onkyo TX-SR607 receiver. Signed-off-by: Anssi Hannula <anssi.hannula@iki.fi> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-06-17ASoC: fsl_spdif: Improve coding styleNicolin Chen
1) Apply better indentations 2) Drop braces for single statement. 3) Use simpler ternary to reduce code. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-05ASoC: fsl_spdif: Rename all _div to _dfNicolin Chen
We should have used _df by following the reference manual at the beginning. So this patch just renames them. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-05Merge tag 'v3.15-rc4' into asoc-fsl-spdifMark Brown
Linux 3.15-rc4
2014-05-05ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock onlyNicolin Chen
The clock mux for the Freescale S/PDIF controller has eight clock sources while most of them are from other moudles and even system clocks that do not allow a rate-changing operation. So we here only allow the clk_set_rate() and clk_round_rate() happened to spdif root clock, the private clock for S/PDIF controller. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-04-18ASoC: fsl_spdif: Fix wrong OFFSET of STC_SYSCLK_DIVNicolin Chen
It should use STC_SYSCLK_DIV_OFFSET. Thus fix it. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-08-22ASoC: fsl: Add S/PDIF CPU DAI driverNicolin Chen
This patch implements a device-tree-only CPU DAI driver for Freescale S/PDIF controller that supports stereo playback and record feature. Signed-off-by: Nicolin Chen <b42378@freescale.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>