From 672a58fc7c477e59981653a11241566870fff852 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 24 Feb 2023 13:30:45 +0530 Subject: arm64: dts: qcom: sm8150: Fix the iommu mask used for PCIe controllers The iommu mask should be 0x3f as per Qualcomm internal documentation. Without the correct mask, the PCIe transactions from the endpoint will result in SMMU faults. Hence, fix it! Cc: stable@vger.kernel.org # 5.19 Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230224080045.6577-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index fd20096cfc6e..13e0ce828606 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1826,7 +1826,7 @@ "slave_q2a", "tbu"; - iommus = <&apps_smmu 0x1d80 0x7f>; + iommus = <&apps_smmu 0x1d80 0x3f>; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; @@ -1925,7 +1925,7 @@ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommus = <&apps_smmu 0x1e00 0x7f>; + iommus = <&apps_smmu 0x1e00 0x3f>; iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, <0x100 &apps_smmu 0x1e01 0x1>; -- cgit v1.2.3 From 8013295662f55696e5953ef14c31ba03721adf8f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 11 Feb 2023 10:54:15 +0530 Subject: arm64: dts: qcom: sc8280xp: Add label property to vadc channel nodes For uniquely identifying the vadc channels, label property has to be used. The initial commit adding vadc support assumed that the driver will use the unit address along with the node name to identify the channels. But this assumption is now broken by, commit 701c875aded8 ("iio: adc: qcom-spmi-adc5: Fix the channel name") that stripped unit address from channel names. This results in probe failure of the vadc driver: [ 8.380370] iio iio:device0: tried to double register : in_temp_pmic-die-temp_input [ 8.380383] qcom-spmi-adc5 c440000.spmi:pmic@0:adc@3100: Failed to register sysfs interfaces [ 8.380386] qcom-spmi-adc5: probe of c440000.spmi:pmic@0:adc@3100 failed with error -16 Hence, let's get rid of the assumption about drivers and rely on label property to uniquely identify the channels. The labels are derived from the schematics for each PMIC. For internal adc channels such as die and xo, the PMIC names are used as a prefix. Fixes: 7c0151347401 ("arm64: dts: qcom: sc8280xp-x13s: Add PM8280_{1/2} ADC_TM5 channels") Fixes: 9d41cd17394a ("arm64: dts: qcom: sc8280xp-x13s: Add PMR735A VADC channel") Fixes: 3375151a7185 ("arm64: dts: qcom: sc8280xp-x13s: Add PM8280_{1/2} VADC channels") Fixes: 9a6b3042c533 ("arm64: dts: qcom: sc8280xp-x13s: Add PMK8280 VADC channels") Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230211052415.14581-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 98e71b933437..96b36ce94ce0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -772,75 +772,88 @@ pmic-die-temp@3 { reg = ; qcom,pre-scaling = <1 1>; + label = "pmk8350_die_temp"; }; xo-therm@44 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "pmk8350_xo_therm"; }; pmic-die-temp@103 { reg = ; qcom,pre-scaling = <1 1>; + label = "pmc8280_1_die_temp"; }; sys-therm@144 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm1"; }; sys-therm@145 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm2"; }; sys-therm@146 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm3"; }; sys-therm@147 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm4"; }; pmic-die-temp@303 { reg = ; qcom,pre-scaling = <1 1>; + label = "pmc8280_2_die_temp"; }; sys-therm@344 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm5"; }; sys-therm@345 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm6"; }; sys-therm@346 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm7"; }; sys-therm@347 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "sys_therm8"; }; pmic-die-temp@403 { reg = ; qcom,pre-scaling = <1 1>; + label = "pmr735a_die_temp"; }; }; -- cgit v1.2.3 From 205c91fb6aca5f8bad5346181575a7ef78e43cea Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 13:49:21 +0100 Subject: arm64: dts: qcom: sm6115: Un-enable SPI5 by default The commit mentioned in the fixes tag erroneously enabled SPI5 unconditionally. Undo it. Fixes: 25aab0b852d6 ("arm64: dts: qcom: sm6115: Add geni debug uart node for qup0") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216124921.3985834-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 4d6ec815b78b..fbd67d2c8d78 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1078,6 +1078,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; -- cgit v1.2.3 From 11d5e41f5e129e39bddedc7244a0946a802d2e8e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 9 Jan 2023 14:56:47 +0100 Subject: arm64: dts: qcom: sm6375: Add missing power-domain-named to CDSP This was omitted when first introducing the node. Fix it. Fixes: fe6fd26aeddf ("arm64: dts: qcom: sm6375: Add ADSP&CDSP") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230109135647.339224-5-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 31b88c738510..068ee4f72485 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1209,6 +1209,7 @@ clock-names = "xo"; power-domains = <&rpmpd SM6375_VDDCX>; + power-domain-names = "cx"; memory-region = <&pil_cdsp_mem>; -- cgit v1.2.3 From 4059297ed0a5adf8e5fd0bd734d702a24202c02e Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 9 Feb 2023 09:45:10 +0200 Subject: arm64: dts: qcom: sm8550: Add bias pull up value to tlmm i2c data clk states The default bias pull up value for the tlmm i2c data clk states is 2.2kOhms. Add this value to make sure the driver factors in the i2c pull up bit when writing the config register. Signed-off-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209074510.4153294-2-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ff4d342c0725..aa84a36c394a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2691,7 +2691,7 @@ pins = "gpio28", "gpio29"; function = "qup1_se0"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c1_data_clk: qup-i2c1-data-clk-state { @@ -2699,7 +2699,7 @@ pins = "gpio32", "gpio33"; function = "qup1_se1"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c2_data_clk: qup-i2c2-data-clk-state { @@ -2707,7 +2707,7 @@ pins = "gpio36", "gpio37"; function = "qup1_se2"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c3_data_clk: qup-i2c3-data-clk-state { @@ -2715,7 +2715,7 @@ pins = "gpio40", "gpio41"; function = "qup1_se3"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c4_data_clk: qup-i2c4-data-clk-state { @@ -2723,7 +2723,7 @@ pins = "gpio44", "gpio45"; function = "qup1_se4"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c5_data_clk: qup-i2c5-data-clk-state { @@ -2731,7 +2731,7 @@ pins = "gpio52", "gpio53"; function = "qup1_se5"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c6_data_clk: qup-i2c6-data-clk-state { @@ -2739,7 +2739,7 @@ pins = "gpio48", "gpio49"; function = "qup1_se6"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c8_data_clk: qup-i2c8-data-clk-state { @@ -2747,14 +2747,14 @@ pins = "gpio57"; function = "qup2_se0_l1_mira"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; sda-pins { pins = "gpio56"; function = "qup2_se0_l0_mira"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; }; @@ -2763,7 +2763,7 @@ pins = "gpio60", "gpio61"; function = "qup2_se1"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c10_data_clk: qup-i2c10-data-clk-state { @@ -2771,7 +2771,7 @@ pins = "gpio64", "gpio65"; function = "qup2_se2"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c11_data_clk: qup-i2c11-data-clk-state { @@ -2779,7 +2779,7 @@ pins = "gpio68", "gpio69"; function = "qup2_se3"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c12_data_clk: qup-i2c12-data-clk-state { @@ -2787,7 +2787,7 @@ pins = "gpio2", "gpio3"; function = "qup2_se4"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c13_data_clk: qup-i2c13-data-clk-state { @@ -2795,7 +2795,7 @@ pins = "gpio80", "gpio81"; function = "qup2_se5"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_i2c15_data_clk: qup-i2c15-data-clk-state { @@ -2803,7 +2803,7 @@ pins = "gpio72", "gpio106"; function = "qup2_se7"; drive-strength = <2>; - bias-pull-up; + bias-pull-up = <2200>; }; qup_spi0_cs: qup-spi0-cs-state { -- cgit v1.2.3 From 27072f2ffb29283b9a44d878204c86c08d86b37f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 12:08:03 +0100 Subject: arm64: dts: qcom: sm8550: Use correct CPU compatibles Use the correct compatibles for the four kinds of CPU cores used on SM8550, based on the value of their MIDR_EL1 registers: CPU7: 0x411fd4e0 - CX3 r1p1 CPU5-6: 0x412fd470 - CA710 r?p? CPU3-4: 0x411fd4d0 - CA715 r?p? CPU0-2: 0x411fd461 - CA510 r?p? Signed-off-by: Konrad Dybcio Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216110803.3945747-2-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index aa84a36c394a..25f51245fe9b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -66,7 +66,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a510"; reg = <0 0>; enable-method = "psci"; next-level-cache = <&L2_0>; @@ -89,7 +89,7 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a510"; reg = <0 0x100>; enable-method = "psci"; next-level-cache = <&L2_100>; @@ -108,7 +108,7 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a510"; reg = <0 0x200>; enable-method = "psci"; next-level-cache = <&L2_200>; @@ -127,7 +127,7 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a715"; reg = <0 0x300>; enable-method = "psci"; next-level-cache = <&L2_300>; @@ -146,7 +146,7 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a715"; reg = <0 0x400>; enable-method = "psci"; next-level-cache = <&L2_400>; @@ -165,7 +165,7 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a710"; reg = <0 0x500>; enable-method = "psci"; next-level-cache = <&L2_500>; @@ -184,7 +184,7 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a710"; reg = <0 0x600>; enable-method = "psci"; next-level-cache = <&L2_600>; @@ -203,7 +203,7 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x3"; reg = <0 0x700>; enable-method = "psci"; next-level-cache = <&L2_700>; -- cgit v1.2.3 From 052750a4444577e6067bdf73dd5ff92876f59ef6 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Tue, 21 Feb 2023 20:36:33 +0800 Subject: arm64: dts: qcom: sm8250-xiaomi-elish: Correct venus firmware path Missing vendor name for venus firmware path. Add it. Fixes: a41b617530bf ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro") Signed-off-by: Jianhua Lu Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230221123633.25145-1-lujianhua000@gmail.com --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts index acaa99c5ff8b..a85d47f7a9e8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -625,6 +625,6 @@ }; &venus { - firmware-name = "qcom/sm8250/elish/venus.mbn"; + firmware-name = "qcom/sm8250/xiaomi/elish/venus.mbn"; status = "okay"; }; -- cgit v1.2.3 From eaba416688f4f074ea3bf2ef975c9e2dbb06712b Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Wed, 1 Mar 2023 16:53:50 +0800 Subject: arm64: dts: qcom: msm8916-ufi: Fix sim card selection pinctrl The previous commit mistakenly introduced sim_ctrl_default as pinctrl, this is incorrect, the interface for sim card selection varies between different devices and should not be placed in the dtsi. This commit selects external SIM card slot for ufi001c as default. uf896 selects the correct SIM card slot automatically, thus does not need this pinctrl node. Fixes: faf69431464b ("arm64: dts: qcom: msm8916-thwc: Add initial device trees") Signed-off-by: Yang Xiwen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_7036BCA256055D05F8C49D86DF7F0E2D1A05@qq.com --- arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts | 4 ---- arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts | 28 +++++++++++++++++++++-- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 10 -------- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts index c492db856190..82e260375174 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts @@ -33,7 +33,3 @@ &gpio_leds_default { pins = "gpio81", "gpio82", "gpio83"; }; - -&sim_ctrl_default { - pins = "gpio1", "gpio2"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts index 700cf81cbf8c..8433c9710b1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts @@ -25,6 +25,11 @@ gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; }; +&mpss { + pinctrl-0 = <&sim_ctrl_default>; + pinctrl-names = "default"; +}; + &button_default { pins = "gpio37"; bias-pull-down; @@ -34,6 +39,25 @@ pins = "gpio20", "gpio21", "gpio22"; }; -&sim_ctrl_default { - pins = "gpio1", "gpio2"; +/* This selects the external SIM card slot by default */ +&msmgpio { + sim_ctrl_default: sim-ctrl-default-state { + esim-sel-pins { + pins = "gpio0", "gpio3"; + bias-disable; + output-low; + }; + + sim-en-pins { + pins = "gpio1"; + bias-disable; + output-low; + }; + + sim-sel-pins { + pins = "gpio2"; + bias-disable; + output-high; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 790a9696da9d..cdf34b74fa8f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -92,9 +92,6 @@ }; &mpss { - pinctrl-0 = <&sim_ctrl_default>; - pinctrl-names = "default"; - status = "okay"; }; @@ -240,11 +237,4 @@ drive-strength = <2>; bias-disable; }; - - sim_ctrl_default: sim-ctrl-default-state { - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; }; -- cgit v1.2.3 From 8a63441e83724fee1ef3fd37b237d40d90780766 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Tue, 28 Feb 2023 17:19:12 +0530 Subject: arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent If the controller is not marked as cache coherent, then kernel will try to ensure coherency during dma-ops and that may cause data corruption. So, mark the PCIe node as dma-coherent as the devices on PCIe bus are cache coherent. Cc: stable@vger.kernel.org Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related node") Signed-off-by: Krishna chaitanya chundru Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1677584952-17496-1-git-send-email-quic_krichai@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bdcb74925313..8f4ab6bd2886 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2131,6 +2131,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; + dma-coherent; + iommus = <&apps_smmu 0x1c80 0x1>; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, -- cgit v1.2.3 From 6df6fab9320bc9ebdf50136a01e7bf0ee5984c62 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:31:29 +0100 Subject: arm64: dts: qcom: sm8450: correct WSA2 assigned clocks The WSA2 assigned-clocks were copied from WSA, but the WSA2 uses its own. Fixes: 14341e76dbc7 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308123129.232642-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..e77d188508fd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2143,8 +2143,8 @@ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; - assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; assigned-clock-rates = <19200000>, <19200000>; #clock-cells = <0>; -- cgit v1.2.3 From 670b7d6569bf439c90d7aac48ec36ee3e3013754 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Mar 2023 11:57:38 +0000 Subject: arm64: dts: qcom: sc8280xp: fix rx frame shapping info Some of the SoundWire frameshapping data seems incorrect, fix these values. Fixes: 1749a8ae49a3 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS") Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302115741.7726-2-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..906cbd81d268 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2504,12 +2504,12 @@ qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; - qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; - qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; #sound-dai-cells = <1>; #address-cells = <2>; @@ -2609,15 +2609,15 @@ qcom,din-ports = <4>; qcom,dout-ports = <0>; - qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; status = "disabled"; }; -- cgit v1.2.3 From e43bd22cb377bf4c4e5b12daacaf02f5c24fbb16 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Mar 2023 11:57:39 +0000 Subject: arm64: dts: qcom: sc8280xp: fix lpass tx macro clocks Tx macro soundwire clock is for some reason is incorrectly assigned to va macro, fix this and use tx macro clock instead. Fixes: 1749a8ae49a3 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS") Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302115741.7726-3-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 906cbd81d268..42bfa9fa5b96 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2600,7 +2600,7 @@ <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "core", "wake"; - clocks = <&vamacro>; + clocks = <&txmacro>; clock-names = "iface"; label = "TX"; #sound-dai-cells = <1>; -- cgit v1.2.3 From 4def7aa377ba1dbe66335ca3ebe3aa5a5bc3fe67 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Mar 2023 11:57:40 +0000 Subject: arm64: dts: qcom: sc8280xp-x13s: fix dmic sample rate The version of dmic that is on X13s panel supports clock frequency of range 1 Mhz to 4.8 MHz for normal operation. So correct the existing node to reflect this. Fixes: 8c1ea87e80b4 ("arm64: dts: qcom: sc8280xp-x13s: Add soundcard support") Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302115741.7726-4-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 96b36ce94ce0..7d076b9e85bf 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1075,7 +1075,7 @@ vdd-micb-supply = <&vreg_s10b>; - qcom,dmic-sample-rate = <600000>; + qcom,dmic-sample-rate = <4800000>; status = "okay"; }; -- cgit v1.2.3 From 2e498f35c385654396e94cf12e097522d3973d41 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Mar 2023 11:57:41 +0000 Subject: arm64: dts: qcom: sc8280xp-x13s: fix va dmic dai links and routing VA dmics 0, 1, 2 micbias on X13s are connected to WCD MICBIAS1, WCD MICBIAS1 and WCD MICBIAS3 respectively. Reflect this in dt to get dmics working. Also fix dmics to go via VA Macro instead of TX macro to fix device switching. Fixes: 8c1ea87e80b4 ("arm64: dts: qcom: sc8280xp-x13s: Add soundcard support") Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302115741.7726-5-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7d076b9e85bf..fa412bea8985 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -897,9 +897,9 @@ "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", - "TX DMIC0", "MIC BIAS1", - "TX DMIC1", "MIC BIAS2", - "TX DMIC2", "MIC BIAS3", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", "TX SWR_ADC1", "ADC2_OUTPUT"; wcd-playback-dai-link { @@ -950,7 +950,7 @@ va-dai-link { link-name = "VA Capture"; cpu { - sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; }; platform { -- cgit v1.2.3 From a5982b3971007161b423b39aa843bdb6713a9d44 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Mar 2023 16:47:24 +0100 Subject: arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address The second LPASS pin controller IO address is supposed to be the MCC range which contains the slew rate registers. The Linux driver then accesses slew rate register with hard-coded offset (0xa000). However the DTS contained the address of slew rate register as the second IO address, thus any reads were effectively pass the memory space and lead to "Internal error: synchronous external aborts" when applying pin configuration. Fixes: 6de7f9c34358 ("arm64: dts: qcom: sm8550: add GPR and LPASS pin controller") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302154724.856062-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 25f51245fe9b..24aa724c12ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1997,7 +1997,7 @@ lpass_tlmm: pinctrl@6e80000 { compatible = "qcom,sm8550-lpass-lpi-pinctrl"; reg = <0 0x06e80000 0 0x20000>, - <0 0x0725a000 0 0x10000>; + <0 0x07250000 0 0x10000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 23>; -- cgit v1.2.3 From e607b3c1fa0e1579951acd00f9559a77f97d0927 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 7 Mar 2023 21:02:00 +0530 Subject: arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent The UFS controller on SM8350 supports cache coherency, hence add the "dma-coherent" property to mark it as such. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307153201.180626-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 1c97e28da6ad..1a5a612d4234 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1664,6 +1664,7 @@ power-domains = <&gcc UFS_PHY_GDSC>; iommus = <&apps_smmu 0xe0 0x0>; + dma-coherent; clock-names = "core_clk", -- cgit v1.2.3 From 8ba961d4339c5db0e69ff6627606fe1f34c838e5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 7 Mar 2023 21:02:01 +0530 Subject: arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent The UFS controller on SM8450 supports cache coherency, hence add the "dma-coherent" property to mark it as such. Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307153201.180626-2-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e77d188508fd..b285b1530c10 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4003,6 +4003,7 @@ power-domains = <&gcc UFS_PHY_GDSC>; iommus = <&apps_smmu 0xe0 0x0>; + dma-coherent; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; -- cgit v1.2.3 From b891251b40d4dc4cfd28341f62f6784c02ad3a78 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 7 Mar 2023 18:23:40 -0500 Subject: arm64: dts: qcom: sa8540p-ride: correct name of remoteproc_nsp0 firmware The cdsp.mbn firmware that's referenced in sa8540p-ride.dts is actually named cdsp0.mbn in the deliverables from Qualcomm. Let's go ahead and correct the name to match what's in Qualcomm's deliverable. Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307232340.2370476-1-bmasney@redhat.com --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 3ccb5ffdb3ca..24fa449d48a6 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -241,7 +241,7 @@ }; &remoteproc_nsp0 { - firmware-name = "qcom/sa8540p/cdsp.mbn"; + firmware-name = "qcom/sa8540p/cdsp0.mbn"; status = "okay"; }; -- cgit v1.2.3 From ee1d5100c37e7a95af506c7addf018f652545ce6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 11:16:30 +0530 Subject: arm64: dts: qcom: sm8550: Mark UFS controller as cache coherent The UFS controller on SM8550 supports cache coherency, hence add the "dma-coherent" property to mark it as such. Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308054630.7202-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 24aa724c12ea..5d0888398b3c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1905,6 +1905,7 @@ required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x60 0x0>; + dma-coherent; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; -- cgit v1.2.3 From 10d900a834da29cf753f1e45f66982e322a177c1 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 15:35:50 +0100 Subject: arm64: dts: sm8150: add the QUPv3 high-speed UART node Add the high-speed UART node to the dtsi for sm8150. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309143551.200694-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index fd20096cfc6e..bfa19414c4be 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1334,6 +1334,20 @@ status = "disabled"; }; + uart9: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + reg-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; @@ -2425,6 +2439,13 @@ bias-disable; }; + qup_uart9_default: qup-uart9-default-state { + pins = "gpio41", "gpio42"; + function = "qup9"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c10_default: qup-i2c10-default-state { pins = "gpio9", "gpio10"; function = "qup10"; -- cgit v1.2.3 From d97ba0b040b1aee7c2a7a7155b7752413a965d1f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 15:35:51 +0100 Subject: arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART Enable the high-speed UART port that's connected to the GNSS controller on the board. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309143551.200694-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 459384ec8f23..339fea522509 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -17,6 +17,7 @@ aliases { serial0 = &uart2; + serial1 = &uart9; }; chosen { @@ -400,6 +401,10 @@ status = "okay"; }; +&uart9 { + status = "okay"; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3 From 96ce9227fdbcfe32265ffb2803bfbbfa692cb445 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 28 Jan 2023 11:12:56 +0530 Subject: arm64: dts: qcom: sm6115: Add remoteproc nodes Add the adsp, cdsp and modem remoteproc nodes to sm6115. Signed-off-by: Bhupesh Sharma [bjorn: Extended regs to match #address/size-cells to 2] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230128054256.2100501-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 184 +++++++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 4d6ec815b78b..e463dd3b0f11 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1322,6 +1322,39 @@ #power-domain-cells = <1>; }; + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,sm6115-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6115_VDDCX>; + + memory-region = <&pil_modem_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 12>; + }; + }; + stm@8002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x08002000 0x0 0x1000>, @@ -1934,6 +1967,157 @@ }; }; + remoteproc_adsp: remoteproc@ab00000 { + compatible = "qcom,sm6115-adsp-pas"; + reg = <0x0 0x0ab00000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6115_VDD_LPI_CX>, + <&rpmpd SM6115_VDD_LPI_MX>; + + memory-region = <&pil_adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x01c3 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x01c4 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x01c5 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x01c6 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x01c7 0x0>; + }; + }; + }; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible = "qcom,sm6115-cdsp-pas"; + reg = <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6115_VDDCX>; + + memory-region = <&pil_cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apcs_glb 28>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x0>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x0c600000 0x0 0x80000>; -- cgit v1.2.3 From 17289c0165bdb61a585e8e937b80defc376dbfde Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Jan 2023 20:00:20 -0500 Subject: arm64: dts: qcom: sdm670: add opps for peripherals The interconnects are now in place. Add Operating Performance Points for them to allow the kernel to properly manage them. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230201010020.84586-3-mailingradian@gmail.com --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 109 +++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 02f14692dd9d..c5f839dd1c6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -430,6 +431,10 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; clock-names = "iface", "core", "xo", "ice", "bus"; + interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; iommus = <&apps_smmu 0x140 0xf>; @@ -442,6 +447,38 @@ non-removable; status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_min_svs>; + opp-peak-kBps = <80000 80000>; + opp-avg-kBps = <52286 80000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <200000 100000>; + opp-avg-kBps = <130718 100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <200000 130000>; + opp-avg-kBps = <130718 130000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <4096000 4096000>; + opp-avg-kBps = <1338562 1338562>; + }; + }; }; gpi_dma0: dma-controller@800000 { @@ -477,6 +514,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -490,6 +529,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -507,6 +550,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -524,6 +571,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -541,6 +592,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -558,6 +613,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -575,6 +634,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -592,6 +655,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -609,6 +676,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -649,6 +720,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { @@ -662,6 +735,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -679,6 +756,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -696,6 +777,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -713,6 +798,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -730,6 +819,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -747,6 +840,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -764,6 +861,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -781,6 +882,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1028,6 +1133,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + status = "disabled"; usb_1_dwc3: usb@a600000 { -- cgit v1.2.3 From 009d936f15fd3597dbc762595ac8a864b5396611 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:45 +0100 Subject: arm64: dts: qcom: sc8280xp-pmics: add pmk8280 rtc The PMK8280 has an RTC which can also be used as a wakeup source. Note that the RTC can not be disabled and updating the time is not permitted either. Instead an offset can be stored in some other machine- specific non-volatile memory which a driver can take into account. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-20-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index df7d28f7ae60..d2518ffdf7f8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -95,6 +95,15 @@ #thermal-sensor-cells = <1>; status = "disabled"; }; + + pmk8280_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + wakeup-source; + status = "disabled"; + }; }; pmc8280_1: pmic@1 { -- cgit v1.2.3 From d6dbbda37ab5ab83dccf634fe082eb48d81b4899 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:46 +0100 Subject: arm64: dts: qcom: sc8280xp-pmics: add pmk8280 sdam nvram Add one of the PMK8280 SDAM blocks which can be used to store an RTC offset. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-21-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index d2518ffdf7f8..1411edd42b25 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -104,6 +104,15 @@ wakeup-source; status = "disabled"; }; + + pmk8280_sdam_6: nvram@8500 { + compatible = "qcom,spmi-sdam"; + reg = <0x8500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8500 0x100>; + status = "disabled"; + }; }; pmc8280_1: pmic@1 { -- cgit v1.2.3 From e67b45582c5e2ca829f4bb4c0042f75cdec62b80 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:47 +0100 Subject: arm64: dts: qcom: sc8280xp-crd: enable rtc The SC8280XP CRD firmware does not implement the UEFI time runtime services so the RTC in the PM8280K PMIC needs to be accessed directly. To complicate things further, the RTC control and time registers are read-only on this platform so an offset must be stored in some other machine-specific non-volatile memory which an RTC driver can take into account when reading or updating the time. The UEFI firmware (and Windows) use a UEFI variable for this: 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo but the offset can only be accessed via the Qualcomm UEFI Secure Application residing in the TEE as the firmware does not implement the variable runtime services either. While it is possible to access this UEFI variable from Linux on the CRD, this requires using a fairly complex and reverse-engineered firmware interface. As the only benefit of doing so is to make sure that the UEFI (Windows) and Linux time never gets out of sync, it seems preferable to use the PMIC scratch registers for storing an offset instead. This also avoids flash wear in case of RTC drift, etc. Also note that setting variables using this interface does not work on at least one CRD for reasons not yet known. So instead of using the UEFI RTC offset, reserve four bytes in one of the PMIC SDAM scratch-register blocks to hold the RTC offset. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-22-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 98a0f1f9f01e..d7b537284990 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -563,6 +563,21 @@ status = "okay"; }; +&pmk8280_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmk8280_sdam_6 { + status = "okay"; + + rtc_offset: rtc-offset@bc { + reg = <0xbc 0x4>; + }; +}; + &qup0 { status = "okay"; }; -- cgit v1.2.3 From 5fef1b434aa35e7e34f16bc5cb389d783f5a832f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:48 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: enable rtc The Lenovo X13s firmware does not implement the UEFI time runtime services so the RTC in the PM8280K PMIC needs to be accessed directly. To complicate things further, the RTC control and time registers are read-only on this platform so an offset must be stored in some other machine-specific non-volatile memory which an RTC driver can take into account when reading or updating the time. The UEFI firmware (and Windows) use a UEFI variable for this: 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo but the offset can only be accessed via the Qualcomm UEFI Secure Application residing in the TEE as the firmware does not implement the variable runtime services either. While it is possible to access this UEFI variable from Linux on the X13s, this requires using a fairly complex and reverse-engineered firmware interface. As the only benefit of doing so is to make sure that the UEFI (Windows) and Linux time never gets out of sync, it seems preferable to use the PMIC scratch registers for storing an offset instead. This also avoids flash wear in case of RTC drift, etc. So instead of using the UEFI RTC offset, reserve four bytes in one of the PMIC SDAM scratch-register blocks to hold the RTC offset. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-23-johan+linaro@kernel.org --- .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 98e71b933437..9b674686943d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -766,6 +766,21 @@ status = "okay"; }; +&pmk8280_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmk8280_sdam_6 { + status = "okay"; + + rtc_offset: rtc-offset@bc { + reg = <0xbc 0x4>; + }; +}; + &pmk8280_vadc { status = "okay"; -- cgit v1.2.3 From a5b9c5c548bd2c6997581e6a8991cea264cfd657 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Feb 2023 10:13:35 +0100 Subject: dt-bindings: clock: Add Qcom SM6125 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208091340.124641-6-konrad.dybcio@linaro.org --- .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif -- cgit v1.2.3 From 94329ce6e38fc420a7cc67b4174c7c8254e1493f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Feb 2023 10:13:37 +0100 Subject: dt-bindings: clock: Add Qcom SM6375 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208091340.124641-8-konrad.dybcio@linaro.org --- .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif -- cgit v1.2.3 From c413f34e7aafbabdab16fd8014ac4c87038dfd08 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Feb 2023 10:13:39 +0100 Subject: dt-bindings: clock: Add Qcom SM6115 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208091340.124641-10-konrad.dybcio@linaro.org --- .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..cf19f44af774 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif -- cgit v1.2.3 From 32734bbd1802efbd60ea4f0c3c1d5500bd0b20fe Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 20:00:20 +0200 Subject: arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes First, move the pinctrl related propeties out from SoC dtsi and into the board dts and add blank lines before status properties in the PHY nodes to be consistent with the rest of the nodes. Then drop the pipe clock from the controller nodes. Rename the aggre0 and aggre1 clocks to more generic noc_aggr, and then the cnoc_pcie_sf_axi to cnoc_sf_axi. Add the cpu-pcie interconnects to both controller nodes. Rename the pcie1 second reset to link_down and drop the unnecessary enable-gpios. Switch the aux clock to GCC_PCIE_1_PHY_AUX_CLK for the pcie1 PHY and drop the aux_phy from clock-names. Also rename the nocsr reset to phy_nocsr. With this changes we are now in line with the SC8280XP bindings. Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208180020.2761766-12-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 10 +++++++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 52 ++++++++++++--------------------- 2 files changed, 28 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5db6e789e6b8..44eab9308ff2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -414,18 +414,27 @@ &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + status = "okay"; }; &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; }; &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + status = "okay"; }; @@ -433,6 +442,7 @@ vdda-phy-supply = <&vreg_l3c_0p91>; vdda-pll-supply = <&vreg_l3e_1p2>; vdda-qref-supply = <&vreg_l1e_0p88>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ff4d342c0725..8992d6580bf3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1672,25 +1672,24 @@ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; - clock-names = "pipe", - "aux", + clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", - "aggre0"; + "noc_aggr"; - interconnect-names = "pcie-mem"; - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; iommus = <&apps_smmu 0x1400 0x7f>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, @@ -1704,12 +1703,6 @@ phys = <&pcie0_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - status = "disabled"; }; @@ -1771,8 +1764,7 @@ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, @@ -1780,21 +1772,21 @@ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; - clock-names = "pipe", - "aux", + clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", - "aggre1", - "cnoc_pcie_sf_axi"; + "noc_aggr", + "cnoc_sf_axi"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - interconnect-names = "pcie-mem"; - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; iommus = <&apps_smmu 0x1480 0x7f>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, @@ -1802,20 +1794,13 @@ resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names = "pci", - "pcie_1_link_down_reset"; + reset-names = "pci", "link_down"; power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - status = "disabled"; }; @@ -1823,18 +1808,17 @@ compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_1_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe", "aux_phy"; + "pipe"; resets = <&gcc GCC_PCIE_1_PHY_BCR>, <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; - reset-names = "phy", "nocsr"; + reset-names = "phy", "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; -- cgit v1.2.3 From fdaa922585f4474c88fbfaa129f8114f38200660 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Feb 2023 21:01:59 +0200 Subject: arm64: dts: qcom: pm8550b: Add eUSB2 repeater node Add nodes for the eUSB2 repeater found on the pm8550b SPMI PMIC. Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208190200.2966723-7-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/pm8550b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi index 16bcfb64d735..72609f31c890 100644 --- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -55,5 +55,11 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm8550b_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; }; }; -- cgit v1.2.3 From 749078e38e1ee28357e8fdcd4eac382a465bd1e7 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 21:02:00 +0200 Subject: arm64: dts: qcom: sm8550-mtp: Add eUSB2 repeater node Add the PMIC eUSB2 repeater node and add the usb-repeater property to the eUSB2 PHY to allow it to be controlled by the PHY driver. Signed-off-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208190200.2966723-8-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 44eab9308ff2..9d4ddb883a70 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -457,6 +457,11 @@ }; }; +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -563,6 +568,8 @@ vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&pm8550b_eusb2_repeater>; + status = "okay"; }; -- cgit v1.2.3 From d228efe884692742e3a614c2386ee006aeb6551d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Feb 2023 17:38:44 +0100 Subject: arm64: dts: qcom: sm8550-qrd: add QRD8550 Add a minimal DTS for the new QRD8550 board - a mobile-like development board with SM8550. Serial, UFS and USB should be working. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210163844.765074-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 439 ++++++++++++++++++++++++++++++++ 2 files changed, 440 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 31aa54f0428c..e55da38ea498 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -200,3 +200,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts new file mode 100644 index 000000000000..d5a645ee2a61 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 QRD"; + compatible = "qcom,sm8550-qrd", "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_s1g_1p25: smps1 { + regulator-name = "vreg_s1g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name = "vreg_s3g_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&vreg_l3g_1p2>; + vccq2-max-microamp = <100>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; -- cgit v1.2.3 From 5a0c6d4349a7da252c9fa5fbc3d42b4e5ee1f334 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Feb 2023 18:59:28 +0100 Subject: arm64: dts: qcom: sm6375: Add RMTFS Add a node for RMTFS on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213175928.1979637-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 31b88c738510..87b4c83588df 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -424,6 +425,15 @@ no-map; }; + rmtfs_mem: rmtfs@f3900000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf3900000 0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + debug_mem: debug@ffb00000 { reg = <0 0xffb00000 0 0xc0000>; no-map; -- cgit v1.2.3 From b5d08f08377218b1d2ab4026e427a7788b271c8e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Feb 2023 22:03:31 +0100 Subject: arm64: dts: qcom: msm8998: Fix stm-stimulus-base reg name The name stm-data-base comes from ancient (msm-3.10 or older) downstream kernels. Upstream uses stm-stimulus-base instead. Fix it. Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213210331.2106877-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 8bc1c59127e5..adf7258b3269 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1524,7 +1524,7 @@ compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x06002000 0x1000>, <0x16280000 0x180000>; - reg-names = "stm-base", "stm-data-base"; + reg-names = "stm-base", "stm-stimulus-base"; status = "disabled"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; -- cgit v1.2.3 From 0d589dc92fca4679186a949194fc7c452d37c575 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 14 Feb 2023 10:08:49 +0100 Subject: arm64: dts: qcom: pm8998: Add a specific compatible for coincell chg Add a PM8998-specific compatible to the coincell charger and keep the PM8941 one as fallback. Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214090849.2186370-3-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index adbba9f4089a..340033ac3186 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -72,7 +72,7 @@ }; pm8998_coincell: charger@2800 { - compatible = "qcom,pm8941-coincell"; + compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell"; reg = <0x2800>; status = "disabled"; -- cgit v1.2.3 From 603f96d4c9d0cb42f934fb0b99440bb9e8ba4385 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 14 Feb 2023 10:27:13 +0100 Subject: arm64: dts: qcom: add initial support for qcom sa8775p-ride This adds basic support for the Qualcomm sa8775p platform and the reference board: sa8775p-ride. The dt files describe the basics of the SoC and enable booting to shell. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++++++++++ 3 files changed, 853 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e55da38ea498..89e23a74bc7f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts new file mode 100644 index 000000000000..3adf7349f4e5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p.dtsi" + +/ { + model = "Qualcomm SA8775P Ride"; + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; + + aliases { + serial0 = &uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi new file mode 100644 index 000000000000..565c1376073e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10000>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + L3_1: l3-cache { + compatible = "cache"; + }; + + }; + }; + + CPU5: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10100>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + CPU6: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10200>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + CPU7: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10300>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sa8775p", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sa8775p-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible = "qcom,sa8775p-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sa8775p-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible = "qcom,sa8775p-config-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible = "qcom,sa8775p-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible = "qcom,sa8775p-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect-gpdsp-anoc { + compatible = "qcom,sa8775p-gpdsp-anoc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect-lpass-ag-noc { + compatible = "qcom,sa8775p-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sa8775p-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible = "qcom,sa8775p-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible = "qcom,sa8775p-nspa-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible = "qcom,sa8775p-nspb-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect-pcie-anoc { + compatible = "qcom,sa8775p-pcie-anoc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible = "qcom,sa8775p-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + /* Will be updated by the bootloader. */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg = <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg = <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90600000 { + reg = <0x0 0x90600000 0x0 0x200000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg = <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg = <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg = <0x0 0x908f0000 0x0 0xf000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908ff000 { + reg = <0x0 0x908ff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible = "qcom,smem"; + reg = <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: cpucp-fw@90b00000 { + reg = <0x0 0x90b00000 0x0 0x100000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg = <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg = <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg = <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg = <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg = <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg = <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg = <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg = <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg = <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg = <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg = <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + tz_stat_mem: tz-stat@d0000000 { + reg = <0x0 0xd0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg = <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg = <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1800000 { + reg = <0x0 0xd1800000 0x0 0x3900000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sa8775p-gcc"; + reg = <0x0 0x100000 0x0 0xc7018>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SA8775P_CX>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x408000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; + + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa8c000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = ; + }; + }; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8775p-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 149>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3 From 2af2ef08c0ba052aefca20609572d67e0633b1ef Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:49 +0530 Subject: arm64: dts: qcom: sdm845: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-2-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..1d5e6ade8ae7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -92,6 +92,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -118,6 +119,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -140,6 +142,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -162,6 +165,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -184,6 +188,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -206,6 +211,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -228,6 +234,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -250,6 +257,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -5232,6 +5240,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; wifi: wifi@18800000 { -- cgit v1.2.3 From 667d8a2039608c4c848179cb45282204eadeb157 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:50 +0530 Subject: arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-3-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bdcb74925313..d9b6e028cdac 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -168,6 +168,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -193,6 +194,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -214,6 +216,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -235,6 +238,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -256,6 +260,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -277,6 +282,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -298,6 +304,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -319,6 +326,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -5337,6 +5345,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; -- cgit v1.2.3 From afa34380d973491e87ab01d13c387528e2e1c476 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:51 +0530 Subject: arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1e1d366c92c1..c46bb6dab6a1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -46,6 +46,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -71,6 +72,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -92,6 +94,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -113,6 +116,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -134,6 +138,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -155,6 +160,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -177,6 +183,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; @@ -198,6 +205,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; @@ -2002,6 +2010,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; -- cgit v1.2.3 From 1b0911fe3edb0895c43db4c19729b3c300028189 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:52 +0530 Subject: arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 8992d6580bf3..71051fb4172b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -68,6 +68,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; @@ -91,6 +92,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; @@ -110,6 +112,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; @@ -129,6 +132,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x300>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; @@ -148,6 +152,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; @@ -167,6 +172,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; @@ -186,6 +192,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; @@ -205,6 +212,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; @@ -3323,6 +3331,7 @@ ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; pmu@24091000 { -- cgit v1.2.3 From d78cb07dbc1d384a8665b08918d188ee670ec45b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:53 +0530 Subject: arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2f0e460acccd..44c8851178eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -97,6 +97,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -127,6 +128,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -151,6 +153,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -175,6 +178,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -199,6 +203,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; @@ -223,6 +228,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; @@ -248,6 +254,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; @@ -272,6 +279,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <444>; @@ -5481,6 +5489,7 @@ ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; -- cgit v1.2.3 From fcca74d893f3511a1e95869b1b3db3abb69bfb3b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:54 +0530 Subject: arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f234159d2060..98a859ad5229 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -27,6 +27,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -45,6 +46,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -60,6 +62,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -75,6 +78,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -1312,6 +1316,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; gem_noc: interconnect@19100000 { -- cgit v1.2.3 From 7b39c98ff7e80f7e2bdf3c73829480e6ac123fb5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:55 +0530 Subject: arm64: dts: qcom: sc7180: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ebfa21e9ed8a..53f0076f20f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -76,6 +76,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -103,6 +104,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -126,6 +128,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -149,6 +152,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -172,6 +176,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -195,6 +200,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -218,6 +224,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -241,6 +248,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -3578,6 +3586,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; wifi: wifi@18800000 { -- cgit v1.2.3 From fc7258948c4a9e5dd2670adfcc80b13c621fbcd1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:56 +0530 Subject: arm64: dts: qcom: sm8150: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-9-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index bfa19414c4be..c7e0cc18c21f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -48,6 +48,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -74,6 +75,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -97,6 +99,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -119,6 +122,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -141,6 +145,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; @@ -163,6 +168,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; @@ -185,6 +191,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; @@ -207,6 +214,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <421>; @@ -4294,6 +4302,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; lmh_cluster1: lmh@18350800 { -- cgit v1.2.3 From c2a18730f0aaa2088a259f123e5fedf05f8a7041 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:57 +0530 Subject: arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-10-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 1c97e28da6ad..e52deb2ccfb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -49,6 +49,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -70,6 +71,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -87,6 +89,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -104,6 +107,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -121,6 +125,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -138,6 +143,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -156,6 +162,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -173,6 +180,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; @@ -3240,6 +3248,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; cdsp: remoteproc@98900000 { -- cgit v1.2.3 From 2051f735b37d8e49f84914df11eb7b4a3a16349f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:58 +0530 Subject: arm64: dts: qcom: sc8280xp: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..213767a377ff 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -45,6 +45,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_0>; @@ -69,6 +70,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_100>; @@ -89,6 +91,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_200>; @@ -109,6 +112,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_300>; @@ -129,6 +133,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_400>; @@ -149,6 +154,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_500>; @@ -169,6 +175,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_600>; @@ -189,6 +196,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_700>; @@ -4040,6 +4048,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; remoteproc_nsp0: remoteproc@1b300000 { -- cgit v1.2.3 From d9ab57eec39db8bf72951e00cde5ab117bcad6d8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:59 +0530 Subject: arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-12-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 87b4c83588df..6252a547d916 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -40,6 +40,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -59,6 +60,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -75,6 +77,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -91,6 +94,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -107,6 +111,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -123,6 +128,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -140,6 +146,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -156,6 +163,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -1393,6 +1401,7 @@ ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; -- cgit v1.2.3 From 0e6538e2d973bdfdf4d65a7d4b8baf1b7cdf75f0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:34:00 +0530 Subject: arm64: dts: qcom: sm6115: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-13-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index e463dd3b0f11..a9d2ff40935f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -39,6 +39,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -54,6 +55,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x1>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -65,6 +67,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x2>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -76,6 +79,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x3>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -87,6 +91,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; @@ -102,6 +107,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x101>; + clocks = <&cpufreq_hw 1>; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; enable-method = "psci"; @@ -113,6 +119,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x102>; + clocks = <&cpufreq_hw 1>; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; enable-method = "psci"; @@ -124,6 +131,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x103>; + clocks = <&cpufreq_hw 1>; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; enable-method = "psci"; @@ -2307,6 +2315,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; -- cgit v1.2.3 From c564b69984a78ce7811f22437794c9bb2afc11fd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:43 +0100 Subject: arm64: dts: qcom: sc7280: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-2-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d9b6e028cdac..46723418385b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2685,7 +2685,8 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; -- cgit v1.2.3 From 3e5c00256881f35b8664e1cf0b9fbf42cd9f24a1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:44 +0100 Subject: arm64: dts: qcom: sm8150: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-3-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c7e0cc18c21f..55aea7c05ed8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2271,7 +2271,8 @@ }; adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; -- cgit v1.2.3 From 8347b12e905b99f445067d09326e4a1cc490f9cc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:45 +0100 Subject: arm64: dts: qcom: sm8250: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-4-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 44c8851178eb..0ee376b7ff86 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2664,7 +2664,8 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>; -- cgit v1.2.3 From 78c61b6b2c33041940f2b22b47b058e83684b3f5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:46 +0100 Subject: arm64: dts: qcom: sm8350: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-5-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e52deb2ccfb5..e31043dd48a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1915,7 +1915,8 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; -- cgit v1.2.3 From 5a1816cc2d8caa054aa8b254efea9739aa8a68c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 20 Feb 2023 10:43:38 +0100 Subject: arm64: dts: qcom: msm8996: move WCD9335 audio codec to boards The WCD9335 audio codec on Slimbus is a property of a board, not SoC, thus it should not be present in MSM8996 DTSI. Keep it in specific boards, so it won't appear incomplete in the boards not having it. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230220094339.47370-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 56 +++++++++++++++----- .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 56 +++++++++++++++----- .../arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 60 +++++++++++++++++----- arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +---------- 4 files changed, 135 insertions(+), 67 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index fe6c415e8229..ce189dea2760 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -974,6 +974,50 @@ }; }; +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + &sound { compatible = "qcom,apq8096-sndcard"; model = "DB820c"; @@ -1101,15 +1145,3 @@ &venus { status = "okay"; }; - -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 2994337c6046..104deaee74e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -504,6 +504,50 @@ }; }; +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + &slpi_pil { status = "okay"; }; @@ -772,15 +816,3 @@ &venus { status = "okay"; }; - -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 2acfed28e3cb..446b1d23dec0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -337,6 +337,52 @@ }; }; +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&divclk1_cdc>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-vbat-supply = <&vph_pwr>; + vdd-micbias-supply = <&vph_pwr_bbyp>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + &slpi_pil { status = "okay"; @@ -395,20 +441,6 @@ status = "okay"; }; -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&divclk1_cdc>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-vbat-supply = <&vph_pwr>; - vdd-micbias-supply = <&vph_pwr_bbyp>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; - &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 905678e7175d..293ed2e60691 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3383,36 +3383,8 @@ dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - tasha_ifd: tas-ifd@0,0 { - compatible = "slim217,1a0"; - reg = <0 0>; - }; - - wcd9335: codec@1,0 { - pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; - pinctrl-names = "default"; - - compatible = "slim217,1a0"; - reg = <1 0>; - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; - interrupt-controller; - #interrupt-cells = <1>; - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - - slim-ifc-dev = <&tasha_ifd>; - - #sound-dai-cells = <1>; - }; - }; + status = "disabled"; }; adsp_pil: remoteproc@9300000 { -- cgit v1.2.3 From aec576821e6fd233ae895f4aa57ff1b511a71e8e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 20 Feb 2023 10:43:39 +0100 Subject: arm64: dts: qcom: apq8096-db820c: fix indentation Correct indentation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230220094339.47370-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index ce189dea2760..eb18811b2676 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -1070,7 +1070,7 @@ platform { sound-dai = <&q6routing>; - }; + }; codec { sound-dai = <&wcd9335 AIF4_PB>; -- cgit v1.2.3 From 5d793ff40692c9b3f88df1820a79ac8ae7d9c80b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 21 Feb 2023 16:05:43 +0100 Subject: arm64: dts: qcom: sa8775p: add cpufreq node Add a node for the cpufreq engine and specify the frequency domains for all CPUs. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230221150543.283487-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 565c1376073e..dc21e8450058 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -37,6 +37,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -52,6 +53,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -64,6 +66,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "cache"; @@ -76,6 +79,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "cache"; @@ -88,6 +92,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10000>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "cache"; @@ -104,6 +109,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "cache"; @@ -116,6 +122,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "cache"; @@ -128,6 +135,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "cache"; @@ -645,6 +653,19 @@ #hwlock-cells = <1>; }; + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0xf000000 0x0 0x1000000>; -- cgit v1.2.3 From d39469f5ce81b2cabf07b1cad3deddeafb7b8a8d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 22 Feb 2023 21:00:45 +0530 Subject: arm64: dts: qcom: sm8450: Add IMEM and PIL info region Add a simple-mfd representing IMEM on SM8450 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1677079845-17650-1-git-send-email-quic_mojha@quicinc.com --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..7671f15d639b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3689,6 +3689,20 @@ }; }; + sram@146aa000 { + compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; + reg = <0 0x146aa000 0 0x1000>; + ranges = <0 0 0x146aa000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; -- cgit v1.2.3 From d0af0537e28f6eace02deed63b585396de939213 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 2 Mar 2023 02:18:49 +0100 Subject: arm64: dts: qcom: msm8996: Add missing DWC3 quirks Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302011849.1873056-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 293ed2e60691..a1e14e3540e6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3006,8 +3006,11 @@ interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; phys = <&hsusb_phy1>, <&ssusb_phy_0>; phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,is-utmi-l1-suspend; + tx-fifo-resize; }; }; -- cgit v1.2.3 From bfe088bde391824040c39cbf277d7fe782042936 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:32 +0530 Subject: arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1d5e6ade8ae7..79da7eb954f3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2200,8 +2200,11 @@ llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From 116a932bbc7bc740b068fbfe320a465811ca62f8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:33 +0530 Subject: arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 53f0076f20f6..fb84aa480d91 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2768,7 +2768,7 @@ system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From 62e5ee9db98ed67eb50205072135544055cba9c4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:34 +0530 Subject: arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 46723418385b..5b0b10ee0a5c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3591,8 +3591,9 @@ system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From 0fe0955a79b994b8dcabe79f3a7192251fb256ea Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:35 +0530 Subject: arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 213767a377ff..667595381ab8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2991,8 +2991,14 @@ system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From c5ccf8d33f11f57ef46d12db1dda4afcc4d5150b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:36 +0530 Subject: arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 55aea7c05ed8..d3e7df92998c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1794,8 +1794,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From 42c9b1578233eeb3044656a446486bd2efc87312 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:37 +0530 Subject: arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-9-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 0ee376b7ff86..73c5504c1d44 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3568,8 +3568,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { -- cgit v1.2.3 From 7ae317cba6be783cfd6155bceec91d0918f78fb8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:38 +0530 Subject: arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e31043dd48a6..2a9248baa204 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2213,8 +2213,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; compute_noc: interconnect@a0c0000 { -- cgit v1.2.3 From 413c8ecd48f1df8034c7b13881ded33b3d10171f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:39 +0530 Subject: arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7671f15d639b..f6514c012926 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3995,8 +3995,11 @@ system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From 65d9975e5dae4601e8902765d08f55c246fd2022 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:40 +0530 Subject: arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c46bb6dab6a1..318fefc8f4fa 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1356,7 +1356,7 @@ system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { -- cgit v1.2.3 From 9ebaa4a8cdf11831090a7a7e8d5e82e12b4ff7a8 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 15 Mar 2023 21:27:51 +0100 Subject: arm64: dts: qcom: sm8150: fix the uart9 label There's a typo in the @
part of the uart9 label. Fix it. Fixes: 10d900a834da ("arm64: dts: sm8150: add the QUPv3 high-speed UART node") Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315202751.1518543-1-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d3e7df92998c..3e2b3597281e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1342,7 +1342,7 @@ status = "disabled"; }; - uart9: serial@a8c000 { + uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a84000 0x0 0x4000>; reg-names = "se"; -- cgit v1.2.3 From d882778eb430d430d5f72b92d49cb3f4f50be01c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:56 +0100 Subject: arm64: dts: qcom: drop incorrect cell-index from SPMI The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index' property: sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8976.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6125.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 - 8 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 62d05d740646..f769e63c955c 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -397,7 +397,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sdhc_1: mmc@7824900 { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 2d360d05aa5e..712f80fc865c 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -809,7 +809,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sdhc_1: mmc@7824000 { diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index adf7258b3269..d450fe69fe33 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1993,7 +1993,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; usb3: usb@a8f8800 { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index fb84aa480d91..604c2aa0c276 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3288,7 +3288,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sram@146aa000 { diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 5827cda270a0..72d9a12b5e9c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1189,7 +1189,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; usb3: usb@a8f8800 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 79da7eb954f3..99edd2ba85e2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4935,7 +4935,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sram@146bf000 { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 65033227718a..fd577eb705f8 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1134,7 +1134,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; apps_smmu: iommu@c600000 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 3e2b3597281e..46072ba37390 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3968,7 +3968,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; apps_smmu: iommu@15000000 { -- cgit v1.2.3 From d24539a6a98c19c81deb4004ec5023b3ee6e7bb8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:57 +0100 Subject: arm64: dts: qcom: sm8250: drop incorrect Coresight funnel properties There is only one output port, thus out-ports should not have 'address/size-cells' and unit addresses. 'reg-names' are also not allowed by bindings. qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+' qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 73c5504c1d44..9c8a48c28a88 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2808,11 +2808,7 @@ clock-names = "apb_pclk"; out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + port { funnel_in1_out_funnel_merg: endpoint { remote-endpoint = <&funnel_merg_in_funnel_in1>; }; @@ -2913,7 +2909,6 @@ arm,primecell-periphid = <0x000bb908>; reg = <0 0x06b04000 0 0x1000>; - reg-names = "funnel-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3229,9 +3224,6 @@ clock-names = "apb_pclk"; out-ports { - #address-cells = <1>; - #size-cells = <0>; - port { funnel_apss_merg_out_funnel_in1: endpoint { remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; -- cgit v1.2.3 From 9b8bfc443349c0c220438c6ac8839774210c9ba2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:58 +0100 Subject: arm64: dts: qcom: qdu1000: drop incorrect serial properties The serial node does not use/allow address/size cells: qdu1000-idp.dtb: geniqup@9c0000: serial@99c000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) Fixes: 6bd20c54b589 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 98a859ad5229..99d784085fb3 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -416,8 +416,6 @@ pinctrl-0 = <&qup_uart0_default>; pinctrl-names = "default"; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -585,8 +583,6 @@ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; -- cgit v1.2.3 From 9135ab4a53f7e967456b792ec6fc21ecaf06032b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:59 +0100 Subject: arm64: dts: qcom: sdm845-db845c: drop SPI label The SPI controller nodes do not use/allow label property: sdm845-db845c.dtb: spi@888000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index d4866feef2c4..acd4f9ca6c09 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -819,7 +819,6 @@ &spi2 { /* On Low speed expansion */ - label = "LS-SPI0"; status = "okay"; }; -- cgit v1.2.3 From 9b0ff841f0724fb4bf0218e33afba46a097b258c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:00 +0100 Subject: arm64: dts: qcom: apq8096-db820c: drop SPI label The SPI controller nodes do not use/allow label property: apq8096-db820c.dtb: spi@7575000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index eb18811b2676..842836ed680a 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -146,7 +146,6 @@ &blsp1_spi1 { /* On Low speed expansion */ - label = "LS-SPI0"; status = "okay"; }; @@ -183,7 +182,6 @@ &blsp2_spi6 { /* On High speed expansion */ - label = "HS-SPI1"; status = "okay"; }; -- cgit v1.2.3 From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:01 +0100 Subject: arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select The SPI controller nodes do not use/allow cs-select property: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 2aee8594b280..f5f4827c0e17 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -35,7 +35,6 @@ }; &blsp1_spi1 { - cs-select = <0>; pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; -- cgit v1.2.3 From 35343312a4399074e7a20ab086d29273bb5f1ad2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:02 +0100 Subject: arm64: dts: qcom: msm8953: correct RPMCC node name The bindings expect RPM clock controller subnode to be named 'clock-controller': msm8953-motorola-potter.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 610f3e3fc0c2..4e362b9012bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -269,7 +269,7 @@ compatible = "qcom,rpm-msm8953"; qcom,smd-channels = "rpm_requests"; - rpmcc: rpmcc { + rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; clocks = <&xo_board>; clock-names = "xo"; -- cgit v1.2.3 From 9bc3dc3c9dc1b9e594a6d56210b857f9ffca5853 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:03 +0100 Subject: arm64: dts: qcom: msm8953: drop clocks from RPMPD The RPM power domain controller does not take XO clock as input (according to bindings and Linux driver): msm8953-xiaomi-vince.dtb: rpm-requests: power-controller: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 4e362b9012bd..da00c2f04cda 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -281,9 +281,6 @@ #power-domain-cells = <1>; operating-points-v2 = <&rpmpd_opp_table>; - clocks = <&xo_board>; - clock-names = "ref"; - rpmpd_opp_table: opp-table { compatible = "operating-points-v2"; -- cgit v1.2.3 From e96d20585c84aca49771609b6bca3a7c30f7d397 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:04 +0100 Subject: arm64: dts: qcom: msm8994: correct RPMCC node name The bindings expect RPM clock controller subnode to be named 'clock-controller': apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 9ff9d35496d2..768fe2326933 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -242,7 +242,7 @@ compatible = "qcom,rpm-msm8994"; qcom,smd-channels = "rpm_requests"; - rpmcc: rpmcc { + rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; #clock-cells = <1>; }; -- cgit v1.2.3 From a369c74243ca4ad60b9de0ac5c2207fb4c4117b8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:05 +0100 Subject: arm64: dts: qcom: sc7280: fix EUD port properties Nodes with unit addresses must have also 'reg' property: sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property Fixes: 0b059979090d ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Souradeep Chowdhury Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b0b10ee0a5c..9e20243cce44 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3603,12 +3603,17 @@ <0 0x088e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; eud_ep: endpoint { remote-endpoint = <&usb2_role_switch>; }; }; port@1 { + reg = <1>; eud_con: endpoint { remote-endpoint = <&con_eud>; }; @@ -3619,7 +3624,11 @@ eud_typec: connector { compatible = "usb-c-connector"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; con_eud: endpoint { remote-endpoint = <&eud_con>; }; -- cgit v1.2.3 From 5ff9e238a17733669d6dd1992cae19e1684fe5ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:06 +0100 Subject: arm64: dts: qcom: msm8996-oneplus: do not enable incomplete nodes status=okay should appear in final place where all required properties are provided, because that makes the code the easiest to read. Move the status from common OnePlus DTSI to board DTS. No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-11-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 17 ----------------- arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts | 6 ++++++ arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts | 6 ++++++ 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 104deaee74e5..2adadc1e5b7c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -85,10 +85,6 @@ }; }; -&adsp_pil { - status = "okay"; -}; - &blsp1_i2c3 { status = "okay"; @@ -183,10 +179,6 @@ status = "okay"; }; -&gpu { - status = "okay"; -}; - &hsusb_phy1 { vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; @@ -215,7 +207,6 @@ &mss_pil { pll-supply = <&vreg_l12a_1p8>; - status = "okay"; }; &pcie0 { @@ -548,10 +539,6 @@ }; }; -&slpi_pil { - status = "okay"; -}; - &sound { compatible = "qcom,apq8096-sndcard"; model = "OnePlus3"; @@ -812,7 +799,3 @@ maximum-speed = "high-speed"; }; - -&venus { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts index 1bdc1b134305..dfe75119b8d2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts @@ -17,6 +17,7 @@ &adsp_pil { firmware-name = "qcom/msm8996/oneplus3/adsp.mbn"; + status = "okay"; }; &battery { @@ -25,6 +26,8 @@ }; &gpu { + status = "okay"; + zap-shader { firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; }; @@ -33,12 +36,15 @@ &mss_pil { firmware-name = "qcom/msm8996/oneplus3/mba.mbn", "qcom/msm8996/oneplus3/modem.mbn"; + status = "okay"; }; &slpi_pil { firmware-name = "qcom/msm8996/oneplus3/slpi.mbn"; + status = "okay"; }; &venus { firmware-name = "qcom/msm8996/oneplus3/venus.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts index 34f837dd0c12..51fce65e89f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts @@ -18,6 +18,7 @@ &adsp_pil { firmware-name = "qcom/msm8996/oneplus3t/adsp.mbn"; + status = "okay"; }; &battery { @@ -26,6 +27,8 @@ }; &gpu { + status = "okay"; + zap-shader { firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; }; @@ -34,12 +37,15 @@ &mss_pil { firmware-name = "qcom/msm8996/oneplus3t/mba.mbn", "qcom/msm8996/oneplus3t/modem.mbn"; + status = "okay"; }; &slpi_pil { firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn"; + status = "okay"; }; &venus { firmware-name = "qcom/msm8996/oneplus3t/venus.mbn"; + status = "okay"; }; -- cgit v1.2.3 From f99cdbd858df8457bcffc3e90fa6939d517193c5 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:26 +0530 Subject: dt-bindings: clock: Add Qualcomm IPQ5332 GCC Add binding for the Qualcomm IPQ5332 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-4-quic_kathirav@quicinc.com --- .../bindings/clock/qcom,ipq5332-gcc.yaml | 53 +++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 +++++++++++++++++++++ 2 files changed, 409 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml new file mode 100644 index 000000000000..718fe0625424 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5332 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5332. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-gcc + + clocks: + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: USB PCIE wrapper pipe clock source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_2lane_phy_pipe_clk>, + <&pcie_2lane_phy_pipe_clk_x1>, + <&usb_pcie_wrapper_pipe_clk>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h new file mode 100644 index 000000000000..8a405a0a96d0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define GCC_ADSS_PWM_CLK 6 +#define GCC_ADSS_PWM_CLK_SRC 7 +#define GCC_AHB_CLK 8 +#define GCC_APSS_AXI_CLK_SRC 9 +#define GCC_BLSP1_AHB_CLK 10 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_CE_AHB_CLK 27 +#define GCC_CE_AXI_CLK 28 +#define GCC_CE_PCNOC_AHB_CLK 29 +#define GCC_CMN_12GPLL_AHB_CLK 30 +#define GCC_CMN_12GPLL_APU_CLK 31 +#define GCC_CMN_12GPLL_SYS_CLK 32 +#define GCC_GP1_CLK 33 +#define GCC_GP1_CLK_SRC 34 +#define GCC_GP2_CLK 35 +#define GCC_GP2_CLK_SRC 36 +#define GCC_LPASS_CORE_AXIM_CLK 37 +#define GCC_LPASS_SWAY_CLK 38 +#define GCC_LPASS_SWAY_CLK_SRC 39 +#define GCC_MDIO_AHB_CLK 40 +#define GCC_MDIO_SLAVE_AHB_CLK 41 +#define GCC_MEM_NOC_Q6_AXI_CLK 42 +#define GCC_MEM_NOC_TS_CLK 43 +#define GCC_NSS_TS_CLK 44 +#define GCC_NSS_TS_CLK_SRC 45 +#define GCC_NSSCC_CLK 46 +#define GCC_NSSCFG_CLK 47 +#define GCC_NSSNOC_ATB_CLK 48 +#define GCC_NSSNOC_NSSCC_CLK 49 +#define GCC_NSSNOC_QOSGEN_REF_CLK 50 +#define GCC_NSSNOC_SNOC_1_CLK 51 +#define GCC_NSSNOC_SNOC_CLK 52 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 53 +#define GCC_NSSNOC_XO_DCD_CLK 54 +#define GCC_PCIE3X1_0_AHB_CLK 55 +#define GCC_PCIE3X1_0_AUX_CLK 56 +#define GCC_PCIE3X1_0_AXI_CLK_SRC 57 +#define GCC_PCIE3X1_0_AXI_M_CLK 58 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE3X1_0_AXI_S_CLK 60 +#define GCC_PCIE3X1_0_PIPE_CLK 61 +#define GCC_PCIE3X1_0_RCHG_CLK 62 +#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63 +#define GCC_PCIE3X1_1_AHB_CLK 64 +#define GCC_PCIE3X1_1_AUX_CLK 65 +#define GCC_PCIE3X1_1_AXI_CLK_SRC 66 +#define GCC_PCIE3X1_1_AXI_M_CLK 67 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68 +#define GCC_PCIE3X1_1_AXI_S_CLK 69 +#define GCC_PCIE3X1_1_PIPE_CLK 70 +#define GCC_PCIE3X1_1_RCHG_CLK 71 +#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72 +#define GCC_PCIE3X1_PHY_AHB_CLK 73 +#define GCC_PCIE3X2_AHB_CLK 74 +#define GCC_PCIE3X2_AUX_CLK 75 +#define GCC_PCIE3X2_AXI_M_CLK 76 +#define GCC_PCIE3X2_AXI_M_CLK_SRC 77 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78 +#define GCC_PCIE3X2_AXI_S_CLK 79 +#define GCC_PCIE3X2_AXI_S_CLK_SRC 80 +#define GCC_PCIE3X2_PHY_AHB_CLK 81 +#define GCC_PCIE3X2_PIPE_CLK 82 +#define GCC_PCIE3X2_RCHG_CLK 83 +#define GCC_PCIE3X2_RCHG_CLK_SRC 84 +#define GCC_PCIE_AUX_CLK_SRC 85 +#define GCC_PCNOC_AT_CLK 86 +#define GCC_PCNOC_BFDCD_CLK_SRC 87 +#define GCC_PCNOC_LPASS_CLK 88 +#define GCC_PRNG_AHB_CLK 89 +#define GCC_Q6_AHB_CLK 90 +#define GCC_Q6_AHB_S_CLK 91 +#define GCC_Q6_AXIM_CLK 92 +#define GCC_Q6_AXIM_CLK_SRC 93 +#define GCC_Q6_AXIS_CLK 94 +#define GCC_Q6_TSCTR_1TO2_CLK 95 +#define GCC_Q6SS_ATBM_CLK 96 +#define GCC_Q6SS_PCLKDBG_CLK 97 +#define GCC_Q6SS_TRIG_CLK 98 +#define GCC_QDSS_AT_CLK 99 +#define GCC_QDSS_AT_CLK_SRC 100 +#define GCC_QDSS_CFG_AHB_CLK 101 +#define GCC_QDSS_DAP_AHB_CLK 102 +#define GCC_QDSS_DAP_CLK 103 +#define GCC_QDSS_DAP_DIV_CLK_SRC 104 +#define GCC_QDSS_ETR_USB_CLK 105 +#define GCC_QDSS_EUD_AT_CLK 106 +#define GCC_QDSS_TSCTR_CLK_SRC 107 +#define GCC_QPIC_AHB_CLK 108 +#define GCC_QPIC_CLK 109 +#define GCC_QPIC_IO_MACRO_CLK 110 +#define GCC_QPIC_IO_MACRO_CLK_SRC 111 +#define GCC_QPIC_SLEEP_CLK 112 +#define GCC_SDCC1_AHB_CLK 113 +#define GCC_SDCC1_APPS_CLK 114 +#define GCC_SDCC1_APPS_CLK_SRC 115 +#define GCC_SLEEP_CLK_SRC 116 +#define GCC_SNOC_LPASS_CFG_CLK 117 +#define GCC_SNOC_NSSNOC_1_CLK 118 +#define GCC_SNOC_NSSNOC_CLK 119 +#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120 +#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121 +#define GCC_SNOC_PCIE3_1LANE_M_CLK 122 +#define GCC_SNOC_PCIE3_1LANE_S_CLK 123 +#define GCC_SNOC_PCIE3_2LANE_M_CLK 124 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 125 +#define GCC_SNOC_USB_CLK 126 +#define GCC_SYS_NOC_AT_CLK 127 +#define GCC_SYS_NOC_WCSS_AHB_CLK 128 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 +#define GCC_UNIPHY0_AHB_CLK 130 +#define GCC_UNIPHY0_SYS_CLK 131 +#define GCC_UNIPHY1_AHB_CLK 132 +#define GCC_UNIPHY1_SYS_CLK 133 +#define GCC_UNIPHY_SYS_CLK_SRC 134 +#define GCC_USB0_AUX_CLK 135 +#define GCC_USB0_AUX_CLK_SRC 136 +#define GCC_USB0_EUD_AT_CLK 137 +#define GCC_USB0_LFPS_CLK 138 +#define GCC_USB0_LFPS_CLK_SRC 139 +#define GCC_USB0_MASTER_CLK 140 +#define GCC_USB0_MASTER_CLK_SRC 141 +#define GCC_USB0_MOCK_UTMI_CLK 142 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 143 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144 +#define GCC_USB0_PHY_CFG_AHB_CLK 145 +#define GCC_USB0_PIPE_CLK 146 +#define GCC_USB0_SLEEP_CLK 147 +#define GCC_WCSS_AHB_CLK_SRC 148 +#define GCC_WCSS_AXIM_CLK 149 +#define GCC_WCSS_AXIS_CLK 150 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151 +#define GCC_WCSS_DBG_IFC_APB_CLK 152 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153 +#define GCC_WCSS_DBG_IFC_ATB_CLK 154 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155 +#define GCC_WCSS_DBG_IFC_NTS_CLK 156 +#define GCC_WCSS_ECAHB_CLK 157 +#define GCC_WCSS_MST_ASYNC_BDG_CLK 158 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159 +#define GCC_XO_CLK 160 +#define GCC_XO_CLK_SRC 161 +#define GCC_XO_DIV4_CLK 162 +#define GCC_IM_SLEEP_CLK 163 +#define GCC_NSSNOC_PCNOC_1_CLK 164 +#define GCC_MEM_NOC_AHB_CLK 165 +#define GCC_MEM_NOC_APSS_AXI_CLK 166 +#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167 +#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168 +#define GCC_PCIE3X2_PIPE_CLK_SRC 169 +#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 +#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 +#define GCC_USB0_PIPE_CLK_SRC 172 + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_AHB_CLK_ARES 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4 +#define GCC_APSS_AHB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_BLSP1_AHB_CLK_ARES 7 +#define GCC_BLSP1_BCR 8 +#define GCC_BLSP1_QUP1_BCR 9 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11 +#define GCC_BLSP1_QUP2_BCR 12 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14 +#define GCC_BLSP1_QUP3_BCR 15 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17 +#define GCC_BLSP1_SLEEP_CLK_ARES 18 +#define GCC_BLSP1_UART1_APPS_CLK_ARES 19 +#define GCC_BLSP1_UART1_BCR 20 +#define GCC_BLSP1_UART2_APPS_CLK_ARES 21 +#define GCC_BLSP1_UART2_BCR 22 +#define GCC_BLSP1_UART3_APPS_CLK_ARES 23 +#define GCC_BLSP1_UART3_BCR 24 +#define GCC_CE_BCR 25 +#define GCC_CMN_BLK_BCR 26 +#define GCC_CMN_LDO0_BCR 27 +#define GCC_CMN_LDO1_BCR 28 +#define GCC_DCC_BCR 29 +#define GCC_GP1_CLK_ARES 30 +#define GCC_GP2_CLK_ARES 31 +#define GCC_LPASS_BCR 32 +#define GCC_LPASS_CORE_AXIM_CLK_ARES 33 +#define GCC_LPASS_SWAY_CLK_ARES 34 +#define GCC_MDIOM_BCR 35 +#define GCC_MDIOS_BCR 36 +#define GCC_NSS_BCR 37 +#define GCC_NSS_TS_CLK_ARES 38 +#define GCC_NSSCC_CLK_ARES 39 +#define GCC_NSSCFG_CLK_ARES 40 +#define GCC_NSSNOC_ATB_CLK_ARES 41 +#define GCC_NSSNOC_NSSCC_CLK_ARES 42 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 44 +#define GCC_NSSNOC_SNOC_CLK_ARES 45 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 47 +#define GCC_PCIE3X1_0_AHB_CLK_ARES 48 +#define GCC_PCIE3X1_0_AUX_CLK_ARES 49 +#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51 +#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52 +#define GCC_PCIE3X1_0_BCR 53 +#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54 +#define GCC_PCIE3X1_0_PHY_BCR 55 +#define GCC_PCIE3X1_0_PHY_PHY_BCR 56 +#define GCC_PCIE3X1_1_AHB_CLK_ARES 57 +#define GCC_PCIE3X1_1_AUX_CLK_ARES 58 +#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60 +#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61 +#define GCC_PCIE3X1_1_BCR 62 +#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63 +#define GCC_PCIE3X1_1_PHY_BCR 64 +#define GCC_PCIE3X1_1_PHY_PHY_BCR 65 +#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66 +#define GCC_PCIE3X2_AHB_CLK_ARES 67 +#define GCC_PCIE3X2_AUX_CLK_ARES 68 +#define GCC_PCIE3X2_AXI_M_CLK_ARES 69 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70 +#define GCC_PCIE3X2_AXI_S_CLK_ARES 71 +#define GCC_PCIE3X2_BCR 72 +#define GCC_PCIE3X2_LINK_DOWN_BCR 73 +#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74 +#define GCC_PCIE3X2_PHY_BCR 75 +#define GCC_PCIE3X2PHY_PHY_BCR 76 +#define GCC_PCNOC_BCR 77 +#define GCC_PCNOC_LPASS_CLK_ARES 78 +#define GCC_PRNG_AHB_CLK_ARES 79 +#define GCC_PRNG_BCR 80 +#define GCC_Q6_AHB_CLK_ARES 81 +#define GCC_Q6_AHB_S_CLK_ARES 82 +#define GCC_Q6_AXIM_CLK_ARES 83 +#define GCC_Q6_AXIS_CLK_ARES 84 +#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85 +#define GCC_Q6SS_ATBM_CLK_ARES 86 +#define GCC_Q6SS_PCLKDBG_CLK_ARES 87 +#define GCC_Q6SS_TRIG_CLK_ARES 88 +#define GCC_QDSS_APB2JTAG_CLK_ARES 89 +#define GCC_QDSS_AT_CLK_ARES 90 +#define GCC_QDSS_BCR 91 +#define GCC_QDSS_CFG_AHB_CLK_ARES 92 +#define GCC_QDSS_DAP_AHB_CLK_ARES 93 +#define GCC_QDSS_DAP_CLK_ARES 94 +#define GCC_QDSS_ETR_USB_CLK_ARES 95 +#define GCC_QDSS_EUD_AT_CLK_ARES 96 +#define GCC_QDSS_STM_CLK_ARES 97 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 98 +#define GCC_QDSS_TS_CLK_ARES 99 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104 +#define GCC_QPIC_AHB_CLK_ARES 105 +#define GCC_QPIC_CLK_ARES 106 +#define GCC_QPIC_BCR 107 +#define GCC_QPIC_IO_MACRO_CLK_ARES 108 +#define GCC_QPIC_SLEEP_CLK_ARES 109 +#define GCC_QUSB2_0_PHY_BCR 110 +#define GCC_SDCC1_AHB_CLK_ARES 111 +#define GCC_SDCC1_APPS_CLK_ARES 112 +#define GCC_SDCC_BCR 113 +#define GCC_SNOC_BCR 114 +#define GCC_SNOC_LPASS_CFG_CLK_ARES 115 +#define GCC_SNOC_NSSNOC_1_CLK_ARES 116 +#define GCC_SNOC_NSSNOC_CLK_ARES 117 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118 +#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119 +#define GCC_UNIPHY0_AHB_CLK_ARES 120 +#define GCC_UNIPHY0_BCR 121 +#define GCC_UNIPHY0_SYS_CLK_ARES 122 +#define GCC_UNIPHY1_AHB_CLK_ARES 123 +#define GCC_UNIPHY1_BCR 124 +#define GCC_UNIPHY1_SYS_CLK_ARES 125 +#define GCC_USB0_AUX_CLK_ARES 126 +#define GCC_USB0_EUD_AT_CLK_ARES 127 +#define GCC_USB0_LFPS_CLK_ARES 128 +#define GCC_USB0_MASTER_CLK_ARES 129 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 130 +#define GCC_USB0_PHY_BCR 131 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132 +#define GCC_USB0_SLEEP_CLK_ARES 133 +#define GCC_USB3PHY_0_PHY_BCR 134 +#define GCC_USB_BCR 135 +#define GCC_WCSS_AXIM_CLK_ARES 136 +#define GCC_WCSS_AXIS_CLK_ARES 137 +#define GCC_WCSS_BCR 138 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139 +#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141 +#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143 +#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144 +#define GCC_WCSS_ECAHB_CLK_ARES 145 +#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146 +#define GCC_WCSS_Q6_BCR 147 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148 +#define GCC_XO_CLK_ARES 149 +#define GCC_XO_DIV4_CLK_ARES 150 +#define GCC_Q6SS_DBG_ARES 151 +#define GCC_WCSS_DBG_BDG_ARES 152 +#define GCC_WCSS_DBG_ARES 153 +#define GCC_WCSS_AXI_S_ARES 154 +#define GCC_WCSS_AXI_M_ARES 155 +#define GCC_WCSSAON_ARES 156 +#define GCC_PCIE3X2_PIPE_ARES 157 +#define GCC_PCIE3X2_CORE_STICKY_ARES 158 +#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159 +#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160 +#define GCC_PCIE3X1_0_PIPE_ARES 161 +#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162 +#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163 +#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164 +#define GCC_PCIE3X1_1_PIPE_ARES 165 +#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166 +#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167 +#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168 +#define GCC_IM_SLEEP_CLK_ARES 169 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170 +#define GCC_UNIPHY0_XPCS_ARES 171 +#define GCC_UNIPHY1_XPCS_ARES 172 +#endif -- cgit v1.2.3 From 0360f0ea8c0f67ec8a25c5ec89f044dbc66b5c5f Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:31 +0530 Subject: arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Add initial device tree support for the Qualcomm IPQ5332 SoC and MI01.2 board. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-9-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 ++++++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 263 ++++++++++++++++++++++++++++ 3 files changed, 339 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 89e23a74bc7f..3ba8a11bb81d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts new file mode 100644 index 000000000000..702013b867d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; + compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi new file mode 100644 index 000000000000..a2ed54264d5c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5332", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_mem: tz@4a600000 { + reg = <0x0 0x4a600000 0x0 0x200000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupt-controller; + #interrupt-cells = <2>; + + serial_0_pins: serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x1000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x1000>; /* GICV */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3 From ed32155302fc3e5b8d30c51b95666e844f1449e1 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 10 Feb 2023 11:34:00 +0530 Subject: arm64: dts: qcom: ipq5332: enable the download mode support Enable the support for download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210060401.24383-2-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index a2ed54264d5c..46ce6985e580 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -70,6 +70,7 @@ firmware { scm { compatible = "qcom,scm-ipq5332", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; }; }; @@ -137,6 +138,11 @@ <0>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq5332", "syscon"; + reg = <0x01937000 0x21000>; + }; + sdhc: mmc@7804000 { compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x07805000 0x1000>; -- cgit v1.2.3 From d56dd7f935e125244bc15f5a0a9e68cdb0ec87ca Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 10 Feb 2023 11:34:01 +0530 Subject: arm64: dts: qcom: ipq5332: add SMEM support Add SMEM support by adding required nodes. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210060401.24383-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 46ce6985e580..76d739b216dd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -99,6 +99,14 @@ reg = <0x0 0x4a600000 0x0 0x200000>; no-map; }; + + smem@4a800000 { + compatible = "qcom,smem"; + reg = <0x0 0x4a800000 0x0 0x00100000>; + no-map; + + hwlocks = <&tcsr_mutex 0>; + }; }; soc@0 { @@ -138,6 +146,12 @@ <0>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + tcsr: syscon@1937000 { compatible = "qcom,tcsr-ipq5332", "syscon"; reg = <0x01937000 0x21000>; -- cgit v1.2.3 From 44750f153699b6e4f851a399287e5c8df208d696 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 6 Jan 2023 17:46:18 +0100 Subject: arm64: dts: qcom: sdm845: correct dynamic power coefficients While stressing EAS on my dragonboard RB3, I have noticed that LITTLE cores where never selected as the most energy efficient CPU whatever the utilization level of waking task. energy model framework uses its cost field to estimate the energy with the formula: nrg = cost of the selected OPP * utilization / CPU's max capacity which ends up selecting the CPU with lowest cost / max capacity ration as long as the utilization fits in the OPP's capacity. If we compare the cost of a little OPP with similar capacity of a big OPP like : OPP(kHz) OPP capacity cost max capacity cost/max capacity LITTLE 1766400 407 351114 407 863 big 1056000 408 520267 1024 508 This can be interpreted as the LITTLE core consumes 70% more than big core for the same compute capacity. According to [1], LITTLE consumes 10% less than big core for Coremark benchmark at those OPPs. If we consider that everything else stays unchanged, the dynamic-power-coefficient of LITTLE core should be only 53% of the current value: 290 * 53% = 154 Set the dynamic-power-coefficient of CPU0-3 to 154 to fix the energy model. [1] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main Fixes: 0e0a8e35d725 ("arm64: dts: qcom: sdm845: correct dynamic power coefficients") Signed-off-by: Vincent Guittot Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230106164618.1845281-1-vincent.guittot@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 99edd2ba85e2..6c7acaab6e13 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -95,7 +95,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -122,7 +122,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -145,7 +145,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -168,7 +168,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, -- cgit v1.2.3 From fb1fe1542a12e4694e05fe14d4003f828515700c Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Tue, 17 Jan 2023 06:57:08 -0800 Subject: arm64: dts: qcom: sm8250: Add tpdm mm/prng Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Acked-by: Suzuki K Poulose Signed-off-by: Mao Jinlong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230117145708.16739-10-quic_jinlmao@quicinc.com --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 164 +++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 9c8a48c28a88..9916186c633d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2772,6 +2772,73 @@ }; }; + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0 0x06004000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@9 { + reg = <9>; + tpda_9_in_tpdm_mm: endpoint { + remote-endpoint = <&tpdm_mm_out_tpda9>; + }; + }; + + port@17 { + reg = <23>; + tpda_23_in_tpdm_prng: endpoint { + remote-endpoint = <&tpdm_prng_out_tpda_23>; + }; + }; + }; + }; + + funnel@6005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06005000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint = <&tpda_out_funnel_qatb>; + }; + }; + }; + }; + funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; @@ -2791,6 +2858,13 @@ #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint = <&funnel_qatb_out_funnel_in0>; + }; + }; + port@7 { reg = <7>; funnel0_in7: endpoint { @@ -2904,6 +2978,22 @@ }; }; + tpdm@684c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0 0x0684c000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_23: endpoint { + remote-endpoint = <&tpda_23_in_tpdm_prng>; + }; + }; + }; + }; + funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; arm,primecell-periphid = <0x000bb908>; @@ -2987,6 +3077,80 @@ }; }; + tpdm@6c08000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0 0x06c08000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_mm_out_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; + }; + }; + }; + }; + + funnel@6c0b000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06c0b000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_dl_mm_out_funnel_dl_center: endpoint { + remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + funnel_dl_mm_in_tpdm_mm: endpoint { + remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; + }; + }; + }; + }; + + funnel@6c2d000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06c2d000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port { + tpdm_mm_out_tpda9: endpoint { + remote-endpoint = <&tpda_9_in_tpdm_mm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_dl_center_in_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; + }; + }; + }; + }; + etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; -- cgit v1.2.3 From c2819cab9d2edddcb8395bb74367ba61e581a2c5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 24 Feb 2023 14:07:58 +0100 Subject: arm64: dts: qcom: sc8280xp: Use correct CPU compatibles Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct compatibles instead of the placeholder qcom,kryo. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230224130759.45579-2-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 667595381ab8..ae06ed488b8a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -43,7 +43,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -68,7 +68,7 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -89,7 +89,7 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -110,7 +110,7 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -131,7 +131,7 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -152,7 +152,7 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -173,7 +173,7 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -194,7 +194,7 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; -- cgit v1.2.3 From 67aa109eee654c76dcc100554e637fa64d5aa099 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:37 +0530 Subject: arm64: dts: qcom: sdm845: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller") Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-2-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6c7acaab6e13..0fdd59a9feed 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2303,8 +2303,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; interrupts = ; interrupt-names = "msi"; @@ -2408,7 +2408,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; -- cgit v1.2.3 From c30a27dcfe4545edbda1578b3a63ed6147519cdd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:38 +0530 Subject: arm64: dts: qcom: msm8998: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x1b200000) specified in the ranges property for I/O region. Fixes: b84dfd175c09 ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-3-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d450fe69fe33..09b222f363c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -922,7 +922,7 @@ phy-names = "pciephy"; status = "disabled"; - ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; #interrupt-cells = <1>; -- cgit v1.2.3 From 1d4743d6312582978966d38908b69085621b7693 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:39 +0530 Subject: arm64: dts: qcom: sc7280: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9e20243cce44..e35f1d5325da 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2085,7 +2085,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; -- cgit v1.2.3 From 565c633940312b4eea7785a0a58e1944258c47e9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:40 +0530 Subject: arm64: dts: qcom: sm8550: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 71051fb4172b..a07bbb8e9fb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1661,8 +1661,8 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; bus-range = <0x00 0xff>; dma-coherent; @@ -1753,8 +1753,8 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; bus-range = <0x00 0xff>; dma-coherent; -- cgit v1.2.3 From e49eafefe5ab325e38dd074f2005076ffc271e54 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:41 +0530 Subject: arm64: dts: qcom: ipq8074: Fix the PCI I/O port range For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x10200000, 0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses and align them in a single line. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index f769e63c955c..fe37dcdc52c8 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -779,10 +779,8 @@ phys = <&pcie_phy1>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x10220000 0x10220000 - 0 0xfde0000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ interrupts = ; interrupt-names = "msi"; @@ -843,10 +841,8 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x20220000 0x20220000 - 0 0xfde0000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ interrupts = ; interrupt-names = "msi"; -- cgit v1.2.3 From 75a6e1fdb351189f55097741e8460ca3f9b2883f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:42 +0530 Subject: arm64: dts: qcom: ipq6018: Fix the PCI I/O port range For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address (0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 095bbdd9a5c3 ("arm64: dts: qcom: ipq6018: Add pcie support") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index bbd94025ff5d..9ff4e9d45065 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -738,8 +738,8 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>, - <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>; + ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, + <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; interrupts = ; interrupt-names = "msi"; -- cgit v1.2.3 From cf0ac10feb17661987d0018eb9475dc03e2a2253 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:43 +0530 Subject: arm64: dts: qcom: msm8996: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x0c200000, 0x0d200000, 0x0e200000) specified in the ranges property for I/O region. While at it, let's also align the entries. Fixes: ed965ef89227 ("arm64: dts: qcom: msm8996: add support to pcie") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a1e14e3540e6..55104630a7f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1851,8 +1851,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, - <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, + <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; device_type = "pci"; @@ -1905,8 +1905,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, - <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, + <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; device_type = "pci"; @@ -1956,8 +1956,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, - <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, + <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; device_type = "pci"; -- cgit v1.2.3 From e115a4495db687898b8d91d4f16c2cf55bbf167c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:44 +0530 Subject: arm64: dts: qcom: sm8250: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000, 0x64200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-9-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 9916186c633d..7ccec48255f0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1842,8 +1842,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = , , @@ -1951,7 +1951,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; @@ -2059,7 +2059,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; interrupts = ; -- cgit v1.2.3 From cb3d6ab7fb72f89c92884a6236911da28ddf9b47 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:45 +0530 Subject: arm64: dts: qcom: qcs404: Use 0x prefix for the PCI I/O and MEM ranges To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-10-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index bc2ed73afb74..42fc33ab8b2e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1469,8 +1469,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ - <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ + <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ interrupts = ; interrupt-names = "msi"; -- cgit v1.2.3 From 89fe81c01715f81c3a7d371e9e5f7d7ae5bc557c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:46 +0530 Subject: arm64: dts: qcom: sc8280xp: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x30200000, 0x32200000, 0x34200000, 0x38200000, 0x3c200000) specified in the ranges property for I/O region. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ae06ed488b8a..64d351aa3b0f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1665,7 +1665,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -1764,7 +1764,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -1861,7 +1861,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -1961,7 +1961,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -2058,7 +2058,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; -- cgit v1.2.3 From 422b110b9b0af0afd4a4b19e8fc3ceab9e71d842 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:47 +0530 Subject: arm64: dts: qcom: sm8150: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-12-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 46072ba37390..95e573890983 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1824,8 +1824,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = ; interrupt-names = "msi"; @@ -1920,7 +1920,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; -- cgit v1.2.3 From f57903c8f4c77938eb71fc67e4652264a9fa14f9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:48 +0530 Subject: arm64: dts: qcom: sm8450: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: bc6588bc25fb ("arm64: dts: qcom: sm8450: add PCIe1 root device") Fixes: 7b09b1b47335 ("arm64: dts: qcom: sm8450: add PCIe0 RC device") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-13-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f6514c012926..f1f2ce33a1e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1746,8 +1746,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; /* * MSIs for BDF (1:0.0) only works with Device ID 0x5980. @@ -1862,8 +1862,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; /* * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. -- cgit v1.2.3 From cf4e716e9a38b32a922a88ac3c5b701137a663dd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:49 +0530 Subject: arm64: dts: qcom: sm8350: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-14-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 2a9248baa204..2f27b9da96af 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1495,8 +1495,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = , , @@ -1589,8 +1589,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; interrupt-names = "msi"; -- cgit v1.2.3 From 4a2c9b9e1215c557c17a48e3fabe9b1674c1d608 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Thu, 2 Mar 2023 13:30:49 +0100 Subject: arm64: dts: qcom: msm8976: Add and provide xo clk to rpmcc In order for consumers of RPMCC XO clock to probe successfully their parent needs to be feed with reference clock to obtain proper rate, add fixed xo-board clock and supply it to rpmcc to make consumers happy. Frequency setting is left per board basis just like on other recent trees. Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Fixes: ff7f6d34ca07 ("arm64: dts: qcom: Add support for SONY Xperia X/X Compact") Signed-off-by: Adam Skladowski Reviewed-by: Dmitry Baryshkov [bjorn: Squashed the two patches] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302123051.12440-1-a39.skl@gmail.com Link: https://lore.kernel.org/r/20230302123051.12440-2-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/msm8976.dtsi | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi index 67baced639c9..085d79542e1b 100644 --- a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi @@ -280,3 +280,7 @@ vdda3p3-supply = <&pm8950_l13>; status = "okay"; }; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 712f80fc865c..05929d7a1d23 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -20,6 +20,13 @@ chosen { }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -351,6 +358,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; #clock-cells = <1>; }; -- cgit v1.2.3 From 62d882e62fe91ebdf4acbb8444bb3cf78a958aef Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:04 -0800 Subject: arm64: dts: qcom: sc7180: Delete wormdingler-rev0 The earliest wormdingler I could find in my pile of hardware is -rev1. I believe that -rev0 boards were just distributed as a pile of components with no case. At this point I can't imagine anyone needing to make wormdingler-rev0 work, so let's delete support for it. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.1.Id0cd5120469eb200118c0c7b8ee8209f877767b4@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 -- .../qcom/sc7180-trogdor-wormdingler-rev0-boe.dts | 22 ------------- .../qcom/sc7180-trogdor-wormdingler-rev0-inx.dts | 22 ------------- .../dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi | 36 ---------------------- 4 files changed, 82 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3ba8a11bb81d..ea16e19de4dc 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -120,8 +120,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts deleted file mode 100644 index d6ed7d0afe4a..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Wormdingler board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x10 => 16 - * - bits 7..4: Panel ID: 0x1 (BOE) - */ - -/dts-v1/; - -#include "sc7180-trogdor-wormdingler-rev0.dtsi" - -/ { - model = "Google Wormdingler rev0 BOE panel board"; - compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180"; -}; - -&panel { - compatible = "boe,tv110c9m-ll3"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts deleted file mode 100644 index c03525ea64ca..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Wormdingler board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x0 => 0 - * - bits 7..4: Panel ID: 0x0 (INX) - */ - -/dts-v1/; - -#include "sc7180-trogdor-wormdingler-rev0.dtsi" - -/ { - model = "Google Wormdingler rev0 INX panel board"; - compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180"; -}; - -&panel { - compatible = "innolux,hj110iz-01a"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi deleted file mode 100644 index 7f272c6e95f6..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Wormdingler board device tree source - * - * Copyright 2021 Google LLC. - * - */ - -/dts-v1/; - -#include "sc7180-trogdor-wormdingler.dtsi" - -&avdd_lcd { - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; -}; - -&panel { - enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; -}; - -&v1p8_mipi { - gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; -}; - -/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ -&avdd_lcd_en { - pins = "gpio80"; -}; - -&mipi_1800_en { - pins = "gpio81"; -}; - -&vdd_reset_1800 { - pins = "gpio76"; -}; -- cgit v1.2.3 From 5fe8b1c88d7b3a227d96f277cd0d36a76aff0273 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:05 -0800 Subject: arm64: dts: qcom: sc7180: Delete kingoftown-rev0 The earliest kingoftown that I could find in my pile of boards was -rev2 and even that revision looks pretty rough (plastics on the case are very unfinished). Though I don't actually have details about how many -rev0 devices were produced, I can't imagine anyone still using one. Let's delete support. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.2.I68cbe5d5d45074428469da8c52f1d6a78bdc62fc@changeid --- arch/arm64/boot/dts/qcom/Makefile | 3 +- .../boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts | 38 ---- .../boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts | 17 -- .../boot/dts/qcom/sc7180-trogdor-kingoftown.dts | 228 +++++++++++++++++++++ .../boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi | 220 -------------------- 5 files changed, 229 insertions(+), 277 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ea16e19de4dc..f3e7c8c04c58 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -85,8 +85,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts deleted file mode 100644 index 3abd6222fe46..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Kingoftown board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" -#include "sc7180-trogdor-kingoftown.dtsi" - -/ { - model = "Google Kingoftown (rev0)"; - compatible = "google,kingoftown-rev0", "qcom,sc7180"; -}; - -/* - * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a - * power rail instead, since kingoftown does not have FP. - */ -&pp3300_fp_tp { - gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; -}; - -&tlmm { - en_fp_rails: en-fp-rails-state { - pins = "gpio74"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts deleted file mode 100644 index e0752ba7df11..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Kingoftown board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-parade-ps8640.dtsi" -#include "sc7180-trogdor-kingoftown.dtsi" - -/ { - model = "Google Kingoftown (rev1+)"; - compatible = "google,kingoftown", "qcom,sc7180"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts new file mode 100644 index 000000000000..36326ef972dc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Kingoftown"; + compatible = "google,kingoftown", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + /delete-property/ VBAT-supply; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&ap_tp_i2c { + status = "okay"; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&en_pp3300_dx_edp { + pins = "gpio67"; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_L", /* 0 */ + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", /* 10 */ + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", /* 20 */ + "", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "", + "", /* 30 */ + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", /* 40 */ + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", /* 50 */ + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", /* 60 */ + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", /* 70 */ + "", + "", + "", + "EN_FP_RAILS", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", /* 80 */ + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", /* 90 */ + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", /* 100 */ + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", /* 110 */ + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi deleted file mode 100644 index 315ac5eb5f78..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Kingoftown board device tree source - * - * Copyright 2021 Google LLC. - */ - -/* This file must be included after sc7180-trogdor.dtsi */ -#include -#include "sc7180-trogdor-lte-sku.dtsi" - -&alc5682 { - compatible = "realtek,rt5682s"; - /delete-property/ VBAT-supply; - realtek,dmic1-clk-pin = <2>; - realtek,dmic-clk-rate-hz = <2048000>; -}; - -&ap_tp_i2c { - status = "okay"; -}; - -ap_ts_pen_1v8: &i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply = <&pp3300_ts>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - }; -}; - -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_ZOOM) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; -}; - -&panel { - compatible = "edp-panel"; -}; - -&pp3300_dx_edp { - gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; -}; - -&sound { - compatible = "google,sc7180-trogdor"; - model = "sc7180-rt5682s-max98357a-1mic"; -}; - -&wifi { - qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; -}; - -/* PINCTRL - modifications to sc7180-trogdor.dtsi */ - -&en_pp3300_dx_edp { - pins = "gpio67"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "TP_INT_L", /* 0 */ - "AP_RAM_ID0", - "AP_SKU_ID2", - "AP_RAM_ID1", - "", - "AP_RAM_ID2", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "TS_RESET_L", - "TS_INT_L", - "", /* 10 */ - "EDP_BRIJ_IRQ", - "AP_EDP_BKLTEN", - "", - "", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "HUB_RST_L", - "", - "", - "", /* 20 */ - "", - "", - "AMP_EN", - "", - "", - "", - "", - "HP_IRQ", - "", - "", /* 30 */ - "AP_BRD_ID2", - "BRIJ_SUSPEND", - "AP_BRD_ID0", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "BT_UART_CTS", - "BT_UART_RTS", - "BT_UART_TXD", /* 40 */ - "BT_UART_RXD", - "H1_AP_INT_ODL", - "", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "HP_I2C_SDA", - "HP_I2C_SCL", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", /* 50 */ - "AMP_DIN", - "", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "HP_MCLK", - "AP_SKU_ID0", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", /* 60 */ - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_SPI_CLK", - "AP_SPI_MOSI", - "AP_SPI_MISO", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "EN_PP3300_DX_EDP", - "AP_SPI_CS0_L", - "", - "", /* 70 */ - "", - "", - "", - "EN_FP_RAILS", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT_L", - "UIM1_DATA", - "UIM1_CLK", /* 80 */ - "UIM1_RST", - "", - "CODEC_PWR_EN", - "HUB_EN", - "", - "", - "", - "", - "", - "AP_SKU_ID1", /* 90 */ - "AP_RST_REQ", - "", - "AP_BRD_ID1", - "AP_EC_INT_L", - "", - "", - "", - "", - "", - "", /* 100 */ - "", - "", - "", - "EDP_BRIJ_EN", - "", - "", - "", - "", - "", - "", /* 110 */ - "", - "", - "", - "", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "DP_HOT_PLUG_DET", - "EC_IN_RW_ODL"; -}; -- cgit v1.2.3 From c0d1296512102a216f9ce10238a9f79c0ac22ccf Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:06 -0800 Subject: arm64: dts: qcom: sc7180: Delete lazor-rev0 lazor-rev0 was a pile of parts. While I kept the pile of parts for lazor running on my desk for longer than I usually do, those days are still long past. Let's finally delete support for lazor-rev0. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.3.I30128a6f4b60b096770186430036afb40ede6f70@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 - .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 34 ---------------------- 2 files changed, 35 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f3e7c8c04c58..477783764bf8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -86,7 +86,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts deleted file mode 100644 index d49de65aa960..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" -#include "sc7180-trogdor-lazor.dtsi" - -/ { - model = "Google Lazor (rev0)"; - compatible = "google,lazor-rev0", "qcom,sc7180"; -}; - -&sn65dsi86_out { - /* - * Lane 0 was incorrectly mapped on the cable, but we've now decided - * that the cable is canon and in -rev1+ we'll make a board change - * that means we no longer need the swizzle. - */ - lane-polarities = <1 0>; -}; - -&usb_hub_2_x { - vdd-supply = <&pp3300_l7c>; -}; - -&usb_hub_3_x { - vdd-supply = <&pp3300_l7c>; -}; -- cgit v1.2.3 From b82c362b4d27f439f9ba753e74e0e7a364263f3a Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:07 -0800 Subject: arm64: dts: qcom: sc7180: Delete mrbland The mrbland board was never actually produced and there has been no activity around the board for quite some time. It seems highly unlikely to magically get revived. There should be nobody in need of these device trees, so let's delete them. If somehow the project resurrects itself then we can re-add support, perhaps just for -rev1+. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.4.I79eee3b8e9eb3086ae02760e97a2e12ffa8eb4f0@changeid --- arch/arm64/boot/dts/qcom/Makefile | 4 - .../dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts | 22 -- .../dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts | 22 -- .../boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 36 --- .../dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts | 22 -- .../dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts | 24 -- .../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 320 --------------------- 7 files changed, 450 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 477783764bf8..1a29403400b7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -100,10 +100,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts deleted file mode 100644 index 2767817fb053..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x0 => 0 - * - bits 7..4: Panel ID: 0x0 (AUO) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland-rev0.dtsi" - -/ { - model = "Google Mrbland rev0 AUO panel board"; - compatible = "google,mrbland-rev0-sku0", "qcom,sc7180"; -}; - -&panel { - compatible = "auo,b101uan08.3"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts deleted file mode 100644 index 711485574a03..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x10 => 16 - * - bits 7..4: Panel ID: 0x1 (BOE) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland-rev0.dtsi" - -/ { - model = "Google Mrbland rev0 BOE panel board"; - compatible = "google,mrbland-rev0-sku16", "qcom,sc7180"; -}; - -&panel { - compatible = "boe,tv101wum-n53"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi deleted file mode 100644 index f4c1f3813664..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland.dtsi" - -&avdd_lcd { - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; -}; - -&panel { - enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; -}; - -&v1p8_mipi { - gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; -}; - -/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ -&avdd_lcd_en { - pins = "gpio80"; -}; - -&mipi_1800_en { - pins = "gpio81"; -}; - -&vdd_reset_1800 { - pins = "gpio76"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts deleted file mode 100644 index 275313ef7554..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x600 => 1536 - * - bits 11..8: Panel ID: 0x6 (AUO) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland.dtsi" - -/ { - model = "Google Mrbland rev1+ AUO panel board"; - compatible = "google,mrbland-sku1536", "qcom,sc7180"; -}; - -&panel { - compatible = "auo,b101uan08.3"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts deleted file mode 100644 index 87c6b6c30b5e..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x300 => 768 - * - bits 11..8: Panel ID: 0x3 (BOE) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland.dtsi" - -/ { - model = "Google Mrbland (rev1 - 2) BOE panel board"; - /* Uses ID 768 on rev1 and 1024 on rev2+ */ - compatible = "google,mrbland-sku1024", "google,mrbland-sku768", - "qcom,sc7180"; -}; - -&panel { - compatible = "boe,tv101wum-n53"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi deleted file mode 100644 index ed12ee35f06b..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" - -/* This board only has 1 USB Type-C port. */ -/delete-node/ &usb_c1; - -/ { - avdd_lcd: avdd-lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd_lcd"; - - gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_lcd_en>; - - vin-supply = <&pp5000_a>; - }; - - avee_lcd: avee-lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "avee_lcd"; - - gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&avee_lcd_en>; - - vin-supply = <&pp5000_a>; - }; - - v1p8_mipi: v1p8-mipi-regulator { - compatible = "regulator-fixed"; - regulator-name = "v1p8_mipi"; - - gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_1800_en>; - - vin-supply = <&pp3300_a>; - }; -}; - -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - -&camcc { - status = "okay"; -}; - -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; -}; - -&dsi0 { - - panel: panel@0 { - /* Compatible will be filled in per-board */ - reg = <0>; - enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_reset_1800>; - avdd-supply = <&avdd_lcd>; - avee-supply = <&avee_lcd>; - pp1800-supply = <&v1p8_mipi>; - pp3300-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - rotation = <270>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&gpio_keys { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@5d { - compatible = "goodix,gt7375p"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -&pp1800_uf_cam { - status = "okay"; -}; - -&pp1800_wf_cam { - status = "okay"; -}; - -&pp2800_uf_cam { - status = "okay"; -}; - -&pp2800_wf_cam { - status = "okay"; -}; - -&wifi { - qcom,ath10k-calibration-variant = "GO_MRBLAND"; -}; - -/* - * No eDP on this board but it's logically the same signal so just give it - * a new name and assign the proper GPIO. - */ -pp3300_disp_on: &pp3300_dx_edp { - gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; -}; - -/* PINCTRL - modifications to sc7180-trogdor.dtsi */ - -/* - * No eDP on this board but it's logically the same signal so just give it - * a new name and assign the proper GPIO. - */ - -tp_en: &en_pp3300_dx_edp { - pins = "gpio85"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "HUB_RST_L", - "AP_RAM_ID0", - "AP_SKU_ID2", - "AP_RAM_ID1", - "", - "AP_RAM_ID2", - "UF_CAM_EN", - "WF_CAM_EN", - "TS_RESET_L", - "TS_INT_L", - "", - "", - "AP_EDP_BKLTEN", - "UF_CAM_MCLK", - "WF_CAM_CLK", - "", - "", - "UF_CAM_SDA", - "UF_CAM_SCL", - "WF_CAM_SDA", - "WF_CAM_SCL", - "AVEE_LCD_EN", - "", - "AMP_EN", - "", - "", - "", - "", - "HP_IRQ", - "WF_CAM_RST_L", - "UF_CAM_RST_L", - "AP_BRD_ID2", - "", - "AP_BRD_ID0", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "BT_UART_CTS", - "BT_UART_RTS", - "BT_UART_TXD", - "BT_UART_RXD", - "H1_AP_INT_ODL", - "", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "HP_I2C_SDA", - "HP_I2C_SCL", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DIN", - "PEN_DET_ODL", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "HP_MCLK", - "AP_SKU_ID0", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_SPI_CLK", - "AP_SPI_MOSI", - "AP_SPI_MISO", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "", - "AP_SPI_CS0_L", - "", - "", - "", - "", - "WLAN_SW_CTRL", - "", - "REPORT_E", - "", - "ID0", - "", - "ID1", - "", - "", - "", - "CODEC_PWR_EN", - "HUB_EN", - "TP_EN", - "MIPI_1.8V_EN", - "VDD_RESET_1.8V", - "AVDD_LCD_EN", - "", - "AP_SKU_ID1", - "AP_RST_REQ", - "", - "AP_BRD_ID1", - "AP_EC_INT_L", - "SDM_GRFC_3", - "", - "", - "BOOT_CONFIG_4", - "BOOT_CONFIG_2", - "", - "", - "", - "", - "", - "", - "", - "BOOT_CONFIG_3", - "WCI2_LTE_COEX_TXD", - "WCI2_LTE_COEX_RXD", - "", - "", - "", - "", - "FORCED_USB_BOOT_POL", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "DP_HOT_PLUG_DET", - "EC_IN_RW_ODL"; - - avdd_lcd_en: avdd-lcd-en-state { - pins = "gpio88"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - avee_lcd_en: avee-lcd-en-state { - pins = "gpio21"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - mipi_1800_en: mipi-1800-en-state { - pins = "gpio86"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - vdd_reset_1800: vdd-reset-1800-state { - pins = "gpio87"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; -- cgit v1.2.3 From b26d66228e9744f4ac278d4fa891fc973b00dc6b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:51 +0100 Subject: arm64: dts: qcom: sm8150-kumano: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm8150-sony-xperia-kumano-bahamut.dtb: gpio-keys: key-camera-focus: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index ff77cc3c879a..47e2430991ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -59,7 +59,7 @@ gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; key-camera-snapshot { @@ -68,7 +68,7 @@ gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; key-vol-down { @@ -77,7 +77,7 @@ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; -- cgit v1.2.3 From d7f1f0fd7944b89d45accde9017095feab2b4675 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:52 +0100 Subject: arm64: dts: qcom: msm8998-fxtec: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: msm8998-fxtec-pro1.dtb: gpio-hall-sensors: event-hall-sensor1: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 5aad9f05780a..8b71b1f8f300 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -44,7 +44,7 @@ label = "Keyboard Hall Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; debounce-interval = <15>; - gpio-key,wakeup; + wakeup-source; linux,input-type = ; linux,code = ; }; @@ -116,7 +116,7 @@ gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; }; -- cgit v1.2.3 From ff348b7d963a8b80502997bc266d47e31406db45 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:53 +0100 Subject: arm64: dts: qcom: msm8998-sony-xperia: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: msm8998-sony-xperia-yoshino-lilac.dtb: gpio-keys: button-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 820414758888..fa02e45f1c24 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -106,7 +106,7 @@ gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; }; @@ -138,7 +138,7 @@ gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <30>; }; }; -- cgit v1.2.3 From aa03d854ad656ae214f7ebb13e7d95e436e99da1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:54 +0100 Subject: arm64: dts: qcom: sc7280-idp: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sc7280-idp.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8b5293e7fd2a..388770be8f13 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -70,7 +70,7 @@ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; linux,can-disable; }; -- cgit v1.2.3 From f06c0f2779e4567e3a83986646bdd7f63edfee17 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:55 +0100 Subject: arm64: dts: qcom: sdm630-sony-xperia: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sdm630-sony-xperia-nile-voyager.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index e52580acd5c8..2ca713a3902a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -112,7 +112,7 @@ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; }; }; -- cgit v1.2.3 From d30f4d6de95ab05cec138929f54f5b92a394c68b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:56 +0100 Subject: arm64: dts: qcom: sm6115p-lenovo-j606f: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm6115p-lenovo-j606f.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 4ce2d905d70e..00b153aa1b7d 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -49,7 +49,7 @@ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; }; -- cgit v1.2.3 From 77a7e394287177b57ec14172a046819eec1a8e90 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:57 +0100 Subject: arm64: dts: qcom: sm8250-sony-xperia: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm8250-sony-xperia-edo-pdx206.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts | 2 +- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index 5ecf7dafb2ec..01fe3974ee72 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -26,7 +26,7 @@ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index b9c982a059df..c96cc9c90a5f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -63,7 +63,7 @@ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; -- cgit v1.2.3 From df03c41673308006fab6ba71a8458b15a79181f6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:58 +0100 Subject: arm64: dts: qcom: sm8250-xiaomi-elish: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm8250-xiaomi-elish.dtb: gpio-keys: key-vol-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts index acaa99c5ff8b..24fc29f0ee5e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -95,7 +95,7 @@ linux,code = ; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; -- cgit v1.2.3 From 7629c7a525d163f2a3a08e260a69ff25163ab357 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Mar 2023 09:32:53 +0100 Subject: arm64: dts: qcom: sm8550: fix qup_spi0_cs node The node is incomplete and doesn't need a subnode, add the missing properties and move everything to the root of qup-spi0-cs-state node. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-2-595b02067672@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a07bbb8e9fb5..d3a1e320306e 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2799,10 +2799,10 @@ }; qup_spi0_cs: qup-spi0-cs-state { - cs-pins { - pins = "gpio31"; - function = "qup1_se0"; - }; + pins = "gpio31"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; }; qup_spi0_data_clk: qup-spi0-data-clk-state { -- cgit v1.2.3 From f03908b23f84ecd49f12facf4acf34c3ad24f27a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Mar 2023 09:32:54 +0100 Subject: arm64: dts: qcom: sm8550: misc style fixes Miscellaneous DT fixes to remove spurious blank line and enhance readability. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-3-595b02067672@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d3a1e320306e..8789ea42d6eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -420,7 +420,6 @@ no-map; }; - hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { reg = <0 0x811d0000 0 0x30000>; no-map; @@ -2202,7 +2201,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -2294,8 +2294,10 @@ power-domains = <&rpmhpd SM8550_MMCX>; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -3163,7 +3165,7 @@ intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; - reg = <0 0x17100000 0 0x10000>, /* GICD */ + reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ ranges; #interrupt-cells = <3>; -- cgit v1.2.3 From 608465f798bb3eaf6773a49b893902860858e294 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 8 Mar 2023 13:36:17 +0100 Subject: arm64: dts: qcom: msm8916: Fix tsens_mode unit address The reg address of the tsens_mode nvmem cell is correct but the unit address does not match (0xec vs 0xef). Fix it. No functional change. Fixes: 24aafd041fb2 ("arm64: dts: qcom: msm8916: specify per-sensor calibration cells") Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308123617.101211-1-stephan.gerhold@kernkonzept.com --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0733c2f4f379..0d5283805f42 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -503,7 +503,7 @@ bits = <1 7>; }; - tsens_mode: mode@ec { + tsens_mode: mode@ef { reg = <0xef 0x1>; bits = <5 3>; }; -- cgit v1.2.3 From cf386126aef92256245adc8be686f2df4b837013 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 16 Mar 2023 15:12:52 +0100 Subject: arm64: dts: qcom: sc8280xp: fix external display power domain Fix the external display controller nodes which erroneously described the controllers as belonging to CX rather than MMCX. Fixes: 19d3bb90754f ("arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316141252.2436-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 64d351aa3b0f..c22ab532cdf3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3267,7 +3267,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&mdss0_dp0_opp_table>; - power-domains = <&rpmhpd SC8280XP_CX>; + power-domains = <&rpmhpd SC8280XP_MMCX>; status = "disabled"; @@ -3345,7 +3345,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&mdss0_dp1_opp_table>; - power-domains = <&rpmhpd SC8280XP_CX>; + power-domains = <&rpmhpd SC8280XP_MMCX>; status = "disabled"; -- cgit v1.2.3 From 0ea0edc04a04e3e36fa7d0b3c8463b0440764cf1 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 14 Mar 2023 14:06:32 +0530 Subject: arm64: dts: qcom: sm6115: Cleanup USB node's label There is only one USB controller present on SM6115 / SM4250 Qualcomm SoC, so drop the numbering used with USB node's label names in the dtsi and the related sm4250-oneplus-billie2.dts. Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314083633.1882214-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index a3f1c7c41fd7..fa57f4bf5825 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -225,11 +225,11 @@ status = "okay"; }; -&usb_1 { +&usb { status = "okay"; }; -&usb_1_hsphy { +&usb_hsphy { vdd-supply = <&vreg_l4a>; vdda-pll-supply = <&vreg_l12a>; vdda-phy-dpdm-supply = <&vreg_l15a>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index a9d2ff40935f..86d26a782654 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -650,7 +650,7 @@ #power-domain-cells = <1>; }; - usb_1_hsphy: phy@1613000 { + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; #phy-cells = <0>; @@ -1089,7 +1089,7 @@ }; }; - usb_1: usb@4ef8800 { + usb: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; reg = <0x0 0x04ef8800 0x0 0x400>; #address-cells = <2>; @@ -1117,11 +1117,11 @@ qcom,select-utmi-as-pipe-clk; status = "disabled"; - usb_1_dwc3: usb@4e00000 { + usb_dwc3: usb@4e00000 { compatible = "snps,dwc3"; reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = ; - phys = <&usb_1_hsphy>; + phys = <&usb_hsphy>; phy-names = "usb2-phy"; iommus = <&apps_smmu 0x120 0x0>; snps,dis_u2_susphy_quirk; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 00b153aa1b7d..20a51e164d2a 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -273,11 +273,11 @@ status = "okay"; }; -&usb_1 { +&usb { status = "okay"; }; -&usb_1_hsphy { +&usb_hsphy { vdd-supply = <&pm6125_l4>; vdda-pll-supply = <&pm6125_l12>; vdda-phy-dpdm-supply = <&pm6125_l15>; -- cgit v1.2.3 From 1f1e512288edf0ef99d9ceb9af29e2e004341ced Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 14 Mar 2023 14:06:33 +0530 Subject: arm64: dts: qcom: sm6115: Move USB node's 'maximum-speed' and 'dr_mode' properties to dts Normally the 'maximum-speed' and 'dr_mode' properties of a USB controller + port is dependent on the type of the ports, regulators and mode change interrupt routing available on the board(s). So, move the same from the sm6115 dtsi file to respective board file(s). Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314083633.1882214-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 5 +++++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 5 +++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index fa57f4bf5825..3f39f25e0721 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -229,6 +229,11 @@ status = "okay"; }; +&usb_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; +}; + &usb_hsphy { vdd-supply = <&vreg_l4a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 86d26a782654..fdad0f13e064 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1129,8 +1129,6 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - maximum-speed = "high-speed"; - dr_mode = "peripheral"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 20a51e164d2a..10c9d338446c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -277,6 +277,11 @@ status = "okay"; }; +&usb_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; +}; + &usb_hsphy { vdd-supply = <&pm6125_l4>; vdda-pll-supply = <&pm6125_l12>; -- cgit v1.2.3 From 27ad7815cb70cbfdcbee4368f41033e83731479f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 14 Mar 2023 13:10:01 +0530 Subject: arm64: dts: qcom: sm6115: Move SDHC node(s)'s 'pinctrl' properties to dts Normally the 'pinctrl' properties of a SDHC controller and the chip detect pin settings are dependent on the type of the slots (for e.g uSD card slot), regulators and GPIO(s) available on the board(s). So, move the same from the sm6115 dtsi file to the respective board file(s). Reviewed-by: Marijn Suijten Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314074001.1873781-1-bhupesh.sharma@linaro.org --- .../arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 10 ++++++++++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 22 ---------------------- 2 files changed, 10 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index 3f39f25e0721..a1f0622db5a0 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -202,12 +202,22 @@ vqmmc-supply = <&vreg_l5a>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_state_off &sdc2_card_det_n>; status = "okay"; }; &tlmm { gpio-reserved-ranges = <14 4>; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index fdad0f13e064..840a453f1f14 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -603,13 +603,6 @@ bias-pull-up; drive-strength = <10>; }; - - sd-cd-pins { - pins = "gpio88"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; }; sdc2_state_off: sdc2-off-state { @@ -630,13 +623,6 @@ bias-pull-up; drive-strength = <2>; }; - - sd-cd-pins { - pins = "gpio88"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; }; }; @@ -739,10 +725,6 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; - pinctrl-0 = <&sdc1_state_on>; - pinctrl-1 = <&sdc1_state_off>; - pinctrl-names = "default", "sleep"; - bus-width = <8>; status = "disabled"; }; @@ -761,10 +743,6 @@ <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; - pinctrl-0 = <&sdc2_state_on>; - pinctrl-1 = <&sdc2_state_off>; - pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6115_VDDCX>; operating-points-v2 = <&sdhc2_opp_table>; iommus = <&apps_smmu 0x00a0 0x0>; -- cgit v1.2.3 From 75b81e5a49f897ef1a2f95182216850a53664aa3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:46 +0100 Subject: arm64: dts: qcom: sm8350: add port subnodes in dwc3 node Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-6-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 2f27b9da96af..77c2fdeaab4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2272,6 +2272,25 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; -- cgit v1.2.3 From f28d912671c87ffa30e223fc32c9145a8b5135cd Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:47 +0100 Subject: arm64: dts: qcom: sm8450: add port subnodes in dwc3 node Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-7-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f1f2ce33a1e0..d67e72cdd897 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4172,6 +4172,25 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; -- cgit v1.2.3 From 34e7e432f17ce1df90a044c815ec753bc70f7c6c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:48 +0100 Subject: arm64: dts: qcom: sm8550: add port subnodes in dwc3 node Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-8-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 8789ea42d6eb..9c135417cd54 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2461,6 +2461,25 @@ phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; -- cgit v1.2.3 From a891ec9e4f3adf62068695a48b769b30b22591e2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:49 +0100 Subject: arm64: dts: qcom: sm8350-hdk: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-9-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 46 +++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 09baf6959c71..a10bf7c8764f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -31,6 +31,40 @@ }; }; + pmic-glink { + compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -674,8 +708,16 @@ }; &usb_1_dwc3 { - /* TODO: Define USB-C connector properly */ - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { -- cgit v1.2.3 From 2ca9703147ca7e347e300fb23f699f1065302b0b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:50 +0100 Subject: arm64: dts: qcom: sm8450-hdk: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-10-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 45 ++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index feef3837e4cd..1755ee3aa04c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -87,6 +87,40 @@ enable-active-high; }; + pmic-glink { + compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -724,7 +758,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { -- cgit v1.2.3 From 0dbb756c9120eb46aa1ec4fa47b6da0f6d21374f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:51 +0100 Subject: arm64: dts: qcom: sm8550-mtp: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-11-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 45 ++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9d4ddb883a70..e2b9bb6b1e27 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -27,6 +27,40 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -561,7 +595,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { -- cgit v1.2.3 From b767d1b40cbca49452d712ca0f4f053dacfc5c45 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 22 Mar 2023 00:31:14 +0530 Subject: arm64: dts: qcom: sdm845: Fix the BAM DMA engine compatible string As per documentation, Qualcomm SDM845 SoC supports BAM DMA engine v1.7.4, so use the correct compatible strings. Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230321190118.3327360-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0fdd59a9feed..e8e9aa4da914 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2628,7 +2628,7 @@ }; cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; clocks = <&rpmhcc RPMH_CE_CLK>; -- cgit v1.2.3 From 4f278f71c79f174c027d07f57837d1ca41b2df37 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Tue, 21 Mar 2023 21:23:19 +0300 Subject: arm64: dts: qcom: pm8150l: add spmi-flash-led node Add a node describing the flash block found on pm8150l. Signed-off-by: Danila Tikhonov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230321182319.24958-1-danila@jiaxyga.com --- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 135bfb8d629b..cca45fad75ac 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -116,6 +116,12 @@ #address-cells = <1>; #size-cells = <0>; + pm8150l_flash: led-controller@d300 { + compatible = "qcom,pm8150l-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + pm8150l_lpg: pwm { compatible = "qcom,pm8150l-lpg"; -- cgit v1.2.3 From dc3ad22112de7fe76352ef2aa2943b62eb1836a3 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:44 +0100 Subject: arm64: dts: qcom: sa8775p: add the QUPv3 #2 node Add the second instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index dc21e8450058..9fbddd980f60 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -499,6 +499,19 @@ }; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x5a3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ -- cgit v1.2.3 From 4926a8e93f321760fa265f91d78aa2a2163e222b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:45 +0100 Subject: arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2 Enable the second instance of the QUPv3 engine on the sa8775p-ride board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 3adf7349f4e5..a538bb79c04a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -24,6 +24,10 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; -- cgit v1.2.3 From a23d122572a4ad1292e60d4a87e6f0238aaa0505 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:46 +0100 Subject: arm64: dts: qcom: sa8775p: add the i2c18 node Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-4-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9fbddd980f60..3f935b37ccd1 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2023, Linaro Limited */ +#include #include #include #include @@ -510,6 +511,27 @@ #address-cells = <2>; #size-cells = <2>; status = "disabled"; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; intc: interrupt-controller@17a00000 { -- cgit v1.2.3 From 12f35f74ad6da53d94fcbc1bbb2adff60b31a71f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:47 +0100 Subject: arm64: dts: qcom: sa8775p-ride: enable i2c18 This enables the I2C interface on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index a538bb79c04a..5fdce8279537 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -13,6 +13,7 @@ aliases { serial0 = &uart10; + i2c18 = &i2c18; }; chosen { @@ -20,6 +21,13 @@ }; }; +&i2c18 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; @@ -37,6 +45,13 @@ pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + + qup_i2c18_default: qup-i2c18-state { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart10 { -- cgit v1.2.3 From cfd975f588400e0942d55dc4bb84c12c6f217fb4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:48 +0100 Subject: arm64: dts: qcom: sa8775p: add the spi16 node Add the SPI controller node for the interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-6-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3f935b37ccd1..0be5a469c8ea 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -512,6 +512,27 @@ #size-cells = <2>; status = "disabled"; + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x00890000 0x0 0x4000>; -- cgit v1.2.3 From a3b31b0e0f76326bfa4bc81577f52738ad8e072b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:49 +0100 Subject: arm64: dts: qcom: sa8775p-ride: enable the SPI node Enable the SPI interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-7-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 5fdce8279537..d01ca3a9ee37 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart10; i2c18 = &i2c18; + spi16 = &spi16; }; chosen { @@ -40,12 +41,25 @@ clock-frequency = <32764>; }; +&spi16 { + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &tlmm { qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4"; -- cgit v1.2.3 From 41ae5ca448c21a82a2f07e10954b043a0d45a811 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:50 +0100 Subject: arm64: dts: qcom: sa8775p: add high-speed UART nodes Add two UART nodes that are known to be used by existing development boards with this SoC. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-8-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 0be5a469c8ea..c5b73c591e0f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -498,6 +498,21 @@ operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_2: geniqup@8c0000 { @@ -533,6 +548,21 @@ status = "disabled"; }; + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x00890000 0x0 0x4000>; -- cgit v1.2.3 From 4b6c4249069694a593f3b4c3d81c75a5053b7693 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:51 +0100 Subject: arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-9-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index d01ca3a9ee37..cba7c8116141 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -13,6 +13,7 @@ aliases { serial0 = &uart10; + serial1 = &uart12; i2c18 = &i2c18; spi16 = &spi16; }; @@ -66,6 +67,32 @@ drive-strength = <2>; bias-pull-up; }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; + }; }; &uart10 { @@ -75,6 +102,12 @@ status = "okay"; }; +&uart12 { + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; -- cgit v1.2.3 From e1988af7a646aafe8075b179c00fd8053ced2add Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:52 +0100 Subject: arm64: dts: qcom: sa8775p-ride: enable the BT UART port Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-10-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index cba7c8116141..1020dfd21da2 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart10; serial1 = &uart12; + serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; }; @@ -93,6 +94,32 @@ bias-pull-down; }; }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins = "gpio91"; + function = "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins = "gpio92"; + function = "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins = "gpio93"; + function = "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins = "gpio94"; + function = "qup2_se3"; + bias-pull-down; + }; + }; }; &uart10 { @@ -108,6 +135,12 @@ status = "okay"; }; +&uart17 { + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; -- cgit v1.2.3 From 613f14a3a9d7e12a832ff822f85a33ad0ebee952 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 14:03:14 +0100 Subject: arm64: dts: qcom: sm8250-xiaomi-elish: fix USB maximum speed property Fix typo in USB DWC3 node maximum speed property. Fixes: a41b617530bf ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304130315.51595-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts index 24fc29f0ee5e..6bd0dda8b6e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -595,7 +595,7 @@ &usb_1_dwc3 { dr_mode = "peripheral"; - maximum-spped = "high-speed"; + maximum-speed = "high-speed"; /* Remove USB3 phy */ phys = <&usb_1_hsphy>; phy-names = "usb2-phy"; -- cgit v1.2.3 From 0beda02e530f8fc571877939645cb20ade113027 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 14:03:15 +0100 Subject: arm64: dts: qcom: sm8350-microsoft-surface: fix USB dual-role mode property The "dr_mode" is a property of USB DWC3 node, not the Qualcomm wrapper one: sm8350-microsoft-surface-duo2.dtb: usb@a6f8800: 'dr_mode' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+' Fixes: c16160cfa565 ("arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304130315.51595-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index b536ae36ae6d..3bd5e57cbcda 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -341,6 +341,9 @@ &usb_1 { status = "okay"; +}; + +&usb_1_dwc3 { dr_mode = "peripheral"; }; -- cgit v1.2.3 From 6b056f38f07d6fe48e9c0ea9bbcf68f11c1a388b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Mar 2023 16:43:08 +0100 Subject: arm64: dts: qcom: pm660: align thermal node names with bindings Bindings expect thermal node names to end with '-thermal', so fix pm660 and pm660l: sda660-inforce-ifc6560.dtb: thermal-zones: 'pm660', 'pm660l' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305154308.241651-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index fc0eccaccdf6..4bc717917f44 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -11,7 +11,7 @@ / { thermal-zones { - pm660 { + pm660-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index f9b3864bd3b9..87b71b7205b8 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -11,7 +11,7 @@ / { thermal-zones { - pm660l { + pm660l-thermal { polling-delay-passive = <250>; polling-delay = <1000>; -- cgit v1.2.3 From e225d56042e3a02aa3ee60c96da687ac3c690a37 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Mar 2023 09:14:29 +0100 Subject: arm64: dts: qcom: sdm845-db845c: drop empty node override Drop empty override of pm8998_gpios. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306081430.28491-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index acd4f9ca6c09..e14fe9bbb386 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1135,10 +1135,6 @@ bias-disable; }; -&pm8998_gpios { - -}; - /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi0_default { drive-strength = <6>; -- cgit v1.2.3 From e18b829549793f706c6c8a39f24ba93b3213fb33 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Mar 2023 09:14:30 +0100 Subject: arm64: dts: qcom: drop redundant line breaks Remove trailing, redundant line breaks. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 1 - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 -- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 1 - arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 1 - arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 2 -- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 1 - arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 --- 18 files changed, 29 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 842836ed680a..5ceaab5d4039 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -1137,7 +1137,6 @@ vdda-phy-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; - }; &venus { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0d5283805f42..639b158b4fbe 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -2180,7 +2180,6 @@ }; }; }; - }; timer { diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 55104630a7f0..4661a556772e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1882,7 +1882,6 @@ "cfg", "bus_master", "bus_slave"; - }; pcie1: pcie@608000 { @@ -3471,7 +3470,6 @@ }; }; }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 604c2aa0c276..7b0c25f31a41 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3027,7 +3027,6 @@ required-opps = <&rpmhpd_opp_nom>; }; }; - }; dsi0: dsi@ae94000 { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e35f1d5325da..e342dd073fd2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -943,7 +943,6 @@ opp-avg-kBps = <390000 0>; }; }; - }; gpi_dma0: dma-controller@900000 { @@ -3298,7 +3297,6 @@ opp-avg-kBps = <200000 0>; }; }; - }; usb_1_hsphy: phy@88e3000 { @@ -3767,7 +3765,6 @@ required-opps = <&rpmhpd_opp_turbo>; }; }; - }; videocc: clock-controller@aaf0000 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index c22ab532cdf3..87774d43d8b2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2781,7 +2781,6 @@ drive-strength = <2>; slew-rate = <1>; bias-bus-hold; - }; }; @@ -4413,7 +4412,6 @@ required-opps = <&rpmhpd_opp_nom>; }; }; - }; mdss1_dp1: displayport-controller@22098000 { diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index e3e61b9d1b9d..32a7bd59e1ec 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -395,7 +395,6 @@ regulator-enable-ramp-delay = <500>; }; }; - }; &gcc { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 086d14e2de92..d82c0d4407f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -45,7 +45,6 @@ "AMIC3", "MIC BIAS4", "AMIC4", "MIC BIAS1", "AMIC5", "MIC BIAS3"; - }; /* diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 4916d0db5b47..2a3ad478892b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -233,7 +233,6 @@ regulator-allow-set-load; regulator-allowed-modes = ; - }; pm6150l_l7: ldo7 { @@ -255,7 +254,6 @@ regulator-allow-set-load; regulator-allowed-modes = ; - }; pm6150l_l10: ldo10 { diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 318fefc8f4fa..578238910f23 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -176,7 +176,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { @@ -888,7 +887,6 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; - }; config_noc: interconnect@1500000 { diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 6252a547d916..a84a19027cad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -139,7 +139,6 @@ compatible = "cache"; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 95e573890983..8e2820aa0f6e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -92,7 +92,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU2: cpu@200 { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7ccec48255f0..7b78761f2041 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -247,7 +247,6 @@ cache-unified; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { @@ -2428,7 +2427,6 @@ drive-strength = <2>; slew-rate = <1>; bias-bus-hold; - }; }; @@ -2447,7 +2445,6 @@ drive-strength = <2>; input-enable; bias-pull-down; - }; }; @@ -3022,7 +3019,6 @@ }; }; }; - }; etf@6b05000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index a10bf7c8764f..2ee1b121686a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -678,7 +678,6 @@ bias-pull-up; }; }; - }; &uart2 { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 77c2fdeaab4e..86d887a1c3eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -155,7 +155,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 1755ee3aa04c..cc6bfe99d07d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -377,7 +377,6 @@ regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; - }; regulators-3 { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index f7592946c783..65a94dfaf5ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -282,7 +282,6 @@ regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; - }; regulators-3 { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d67e72cdd897..357ef1d275c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -154,7 +154,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { @@ -2762,7 +2761,6 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; - }; mdp_opp_table: opp-table { @@ -3569,7 +3567,6 @@ pins = "gpio76", "gpio77", "gpio78", "gpio79"; function = "qup20"; }; - }; lpass_tlmm: pinctrl@3440000 { -- cgit v1.2.3 From 80dc42d9facc9232072855340c2285682c0c3b19 Mon Sep 17 00:00:00 2001 From: Gergo Koteles Date: Mon, 6 Mar 2023 18:41:47 +0100 Subject: arm64: dts: qcom: sdm845-oneplus-common: add Hall sensor Enable the Hall effect sensor (flip cover) for OnePlus 6/6T. The GPIO is mapped to SW_LID events as in msm8916, msm8994, msm8998 devices. Signed-off-by: Gergo Koteles Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306174147.185239-1-soyer@irl.hu --- .../arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 64638ea94db7..b01542d79ae2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -29,6 +29,23 @@ stdout-path = "serial0:115200n8"; }; + gpio-hall-sensor { + compatible = "gpio-keys"; + label = "Hall effect sensor"; + + pinctrl-0 = <&hall_sensor_default>; + pinctrl-names = "default"; + + event-hall-sensor { + gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + label = "Hall Effect Sensor"; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + gpio-keys { compatible = "gpio-keys"; label = "Volume keys"; @@ -753,6 +770,14 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + hall_sensor_default: hall-sensor-default-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + tri_state_key_default: tri-state-key-default-state { pins = "gpio40", "gpio42", "gpio26"; function = "gpio"; -- cgit v1.2.3 From e4c17be956fbe133211c24b9fc9ba253ffc44db6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:01 +0100 Subject: arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-4-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 7b0c25f31a41..3c799b564b64 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3576,7 +3576,7 @@ }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; -- cgit v1.2.3 From 236e7dd568ed4b839fb8abdf3ce7c77444e610e2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:02 +0100 Subject: arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-5-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e8e9aa4da914..2f32179c7d1b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5232,7 +5232,7 @@ }; cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; -- cgit v1.2.3 From f33f95773e148cd0adbfc3135f2bfbf56a69f488 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:03 +0100 Subject: arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-6-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 840a453f1f14..30d53b812987 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -2282,7 +2282,7 @@ }; cpufreq_hw: cpufreq@f521000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0x0 0x0f521000 0x0 0x1000>, <0x0 0x0f523000 0x0 0x1000>; -- cgit v1.2.3 From 64917707914f95fa5827f2cc5bea2d5febe3a01b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:04 +0100 Subject: arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-7-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 578238910f23..18c4616848ce 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2001,7 +2001,7 @@ }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; -- cgit v1.2.3 From b2e1f87070ead06fb2918edeeed4329f58d1b2ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:05 +0100 Subject: arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-8-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8e2820aa0f6e..573f6bba6f39 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4294,7 +4294,7 @@ }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, <0 0x18327800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1", -- cgit v1.2.3 From 7c2c4c9decf6f4604fe15a1db2da7c1250b3e9e5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 15:27:12 +0100 Subject: arm64: dts: qcom: sm8450-hdk: use recommended drive strength for speaker SD_N Downstream DTS (and sc8280xp-lenovo-thinkpad-x13s with the same speakers) uses 16 mA drive strength for the WSA8835 speaker SD_N reset/shutdown pin. Use the same for HDK8450, as it is seem the recommended value. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308142712.277659-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index cc6bfe99d07d..a2ae37e4ac68 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -797,7 +797,7 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio1"; function = "gpio"; - drive-strength = <4>; + drive-strength = <16>; bias-disable; output-low; }; @@ -805,7 +805,7 @@ spkr_2_sd_n_active: spkr-2-sd-n-active-state { pins = "gpio89"; function = "gpio"; - drive-strength = <4>; + drive-strength = <16>; bias-disable; output-low; }; -- cgit v1.2.3 From f0d0966f87f9c38b74619bf7f0345f368af3a4c1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 19:33:16 +0100 Subject: arm64: dts: qcom: sm8450-hdk: use precise WCD9385 compatible The HDK8450 uses WCD9385 audio codec, so use precise compatible, even though WCD9380 and WCD9385 are both compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308183317.559253-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index a2ae37e4ac68..c97e775e00b3 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -25,7 +25,7 @@ }; wcd938x: audio-codec { - compatible = "qcom,wcd9380-codec"; + compatible = "qcom,wcd9385-codec"; pinctrl-names = "default"; pinctrl-0 = <&wcd_default>; -- cgit v1.2.3 From 6b2777fff8a9942cdcee82ae3f17d7f483a1e18c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 19:33:17 +0100 Subject: arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it is more like a shutdown pin, not a reset. Use the same settings here for HDK8450 and keep the WCD9385 by default in powered off (so pin as low). Align the name of pin configuration node with other pins in the DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308183317.559253-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index c97e775e00b3..e931545a2cac 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -810,9 +810,11 @@ output-low; }; - wcd_default: wcd-default-state { + wcd_default: wcd-reset-n-active-state { pins = "gpio43"; function = "gpio"; + drive-strength = <16>; bias-disable; + output-low; }; }; -- cgit v1.2.3 From b8838e653034425cd26983c7d96535e2742a6212 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:13 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: mark s11b regulator as always-on The s11b supply is used by the wlan module (as well as some of the pmics) which are not yet fully described in the devicetree. Mark the regulator as always-on for now. Fixes: 123b30a75623 ("arm64: dts: qcom: sc8280xp-x13s: enable WiFi controller") Cc: stable@vger.kernel.org # 6.2 Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-2-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index fa412bea8985..532859363a22 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -377,6 +377,7 @@ regulator-min-microvolt = <1272000>; regulator-max-microvolt = <1272000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_s12b: smps12 { -- cgit v1.2.3 From f4472fd33e4751c54efb13d2536261e9273770a9 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:14 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: mark s10b regulator as always-on The s10b supply is used by several components that are not (yet) described in devicetree (e.g. ram, charger, ec) and must not be disabled. Mark the regulator as always-on. Fixes: f29077d86652 ("arm64: dts: qcom: sc8280xp-x13s: Add soundcard support") Cc: Srinivas Kandagatla Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 532859363a22..d6f6feee635e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -370,6 +370,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_s11b: smps11 { -- cgit v1.2.3 From 291e6b6cd7145108d45aeffbac4bb1348fece6b6 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:15 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: mark s12b regulator as always-on The s12b supply is used by several pmic regulators as well as the wlan/bluetooth radio which are not yet fully described in the devicetree. Mark the regulator as always-on for now. Fixes: f29077d86652 ("arm64: dts: qcom: sc8280xp-x13s: Add soundcard support") Cc: Srinivas Kandagatla Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-4-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d6f6feee635e..f327bc72463f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -386,6 +386,7 @@ regulator-min-microvolt = <984000>; regulator-max-microvolt = <984000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l3b: ldo3 { -- cgit v1.2.3 From 07b0883e1f09416d07d25a2158f8cd35b732b686 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:16 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: mark bob regulator as always-on The bob supply is used by several pmic regulators and components which are not (yet fully) described in the devicetree. Mark the regulator as always-on for now. Fixes: f29077d86652 ("arm64: dts: qcom: sc8280xp-x13s: Add soundcard support") Cc: Srinivas Kandagatla Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-5-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index f327bc72463f..99c6d6574559 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -444,6 +444,7 @@ regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; regulator-initial-mode = ; + regulator-always-on; }; }; -- cgit v1.2.3 From ed066df385cb1a7286123a246337636f8debd18d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:17 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: add pmic regulator supplies The s11b, s12b, s1c and bob supplies are used by several pmic regulators. Add the missing description to the devicetree. Note that there are still some consumers that are not (fully) described in the devicetree so the supplies must remain marked as always-on for now. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-6-johan+linaro@kernel.org --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 9b674686943d..ad90f72e116a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -363,7 +363,11 @@ compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; + vdd-l1-l4-supply = <&vreg_s12b>; + vdd-l2-l7-supply = <&vreg_bob>; vdd-l3-l5-supply = <&vreg_s11b>; + vdd-l6-l9-l10-supply = <&vreg_s12b>; + vdd-l8-supply = <&vreg_s12b>; vreg_s10b: smps10 { regulator-name = "vreg_s10b"; @@ -413,7 +417,21 @@ regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; + vdd-bob-supply = <&vreg_vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1c>; + vdd-l2-l8-supply = <&vreg_s1c>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s11b>; + + vreg_s1c: smps1 { + regulator-name = "vreg_s1c"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + regulator-always-on; + }; vreg_l1c: ldo1 { regulator-name = "vreg_l1c"; @@ -449,6 +467,10 @@ qcom,pmic-id = "d"; vdd-l1-l4-supply = <&vreg_s11b>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_s11b>; + vdd-l6-l9-l10-supply = <&vreg_s12b>; + vdd-l8-supply = <&vreg_s12b>; vreg_l3d: ldo3 { regulator-name = "vreg_l3d"; -- cgit v1.2.3 From b01899cb18659c9911cc790cd66784623e5e5a0e Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:18 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: add hid 1.8V supplies All the input devices use s10b as 1.8V supply. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-7-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index ad90f72e116a..57180368d3e2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -592,6 +592,7 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&ts0_default>; @@ -613,6 +614,7 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&tpad_default>; @@ -629,6 +631,7 @@ hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&tpad_default>; @@ -643,6 +646,7 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&kybd_default>; -- cgit v1.2.3 From 2702f54f400ad3979632cdb76553772414f4c5e3 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 21 Mar 2023 10:40:11 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: add wifi calibration variant Describe the bus topology for PCIe domain 6 and add the ath11k calibration variant so that the board file (calibration data) can be loaded. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216246 Reviewed-by: Konrad Dybcio Tested-by: Steev Klimaszewski Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230321094011.9759-3-johan+linaro@kernel.org --- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 57180368d3e2..0d1e49ddd540 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -703,6 +703,23 @@ pinctrl-0 = <&pcie4_default>; status = "okay"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bus-range = <0x01 0xff>; + + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,ath11k-calibration-variant = "LE_X13S"; + }; + }; }; &pcie4_phy { -- cgit v1.2.3 From e16dd29a3dff57eb6c84374ad8d824f1ec1c48bd Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 17 Feb 2023 14:03:08 +0530 Subject: arm64: dts: qcom: ipq5332: enable the CPUFreq support Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency above 800MHz. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217083308.12017-6-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 76d739b216dd..04ef80f267bf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include @@ -35,6 +36,8 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@1 { @@ -43,6 +46,8 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@2 { @@ -51,6 +56,8 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@3 { @@ -59,6 +66,8 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { @@ -80,6 +89,16 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -214,6 +233,24 @@ }; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5332-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a53pll>, <&xo_board>; + clock-names = "pll", "xo"; + #mbox-cells = <1>; + }; + + a53pll: clock@b116000 { + compatible = "qcom,ipq5332-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; -- cgit v1.2.3 From 45875db5cc91958af0e0ada3d8d27ad57ab7c8bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:58:36 +0100 Subject: arm64: dts: qcom: sc7180-trogdor-pazquel360: drop incorrect RT5682S VBAT-supply It seems that the RT5682S codec does not use VBAT-supply: sc7180-trogdor-pazquel360-lte.dtb: codec@1a: Unevaluated properties are not allowed ('VBAT-supply' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217155838.848403-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi index bc4f3b6c6634..273e2249f018 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi @@ -12,6 +12,7 @@ compatible = "realtek,rt5682s"; realtek,dmic1-clk-pin = <2>; realtek,dmic-clk-rate-hz = <2048000>; + /delete-property/ VBAT-supply; }; ap_ts_pen_1v8: &i2c4 { -- cgit v1.2.3 From 11c0d37d4c03ac8002d378cb814aca89118e7d35 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:58:37 +0100 Subject: arm64: dts: qcom: sc7280-herobrine-audio-rt5682: add missing supplies Bindings expect DBVDD-supply and LDO1-IN-supply: sc7280-herobrine-evoker-lte.dtb: codec@1a: 'DBVDD-supply' is a required property sc7280-herobrine-evoker-lte.dtb: codec@1a: 'LDO1-IN-supply' is a required property In sc7180-trogdor.dtsi they come from the same regulator, so let's assume intention was the same here. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217155838.848403-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi index 1ca11a14104d..485f9942e128 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi @@ -94,6 +94,8 @@ hp_i2c: &i2c2 { interrupts = <101 IRQ_TYPE_EDGE_BOTH>; AVDD-supply = <&pp1800_alc5682>; + DBVDD-supply = <&pp1800_alc5682>; + LDO1-IN-supply = <&pp1800_alc5682>; MICVDD-supply = <&pp3300_codec>; realtek,dmic1-data-pin = <1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi index 69e7aa7b2f6c..8b855345e5c7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -76,6 +76,8 @@ hp_i2c: &i2c2 { interrupts = <101 IRQ_TYPE_EDGE_BOTH>; AVDD-supply = <&pp1800_alc5682>; + DBVDD-supply = <&pp1800_alc5682>; + LDO1-IN-supply = <&pp1800_alc5682>; MICVDD-supply = <&pp3300_codec>; realtek,dmic1-data-pin = <1>; -- cgit v1.2.3 From a93af4677e8c3db24eeeb0498bee83b6b7e341fe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:58:38 +0100 Subject: arm64: dts: qcom: sc7280: align RPMh regulator nodes with bindings Device node names should be generic and bindings expect certain pattern for RPMh regulator nodes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217155838.848403-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index 1185141f348e..afae7f46b050 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -27,7 +27,7 @@ }; &apps_rsc { - pmg1110-regulators { + regulators-2 { compatible = "qcom,pmg1110-rpmh-regulators"; qcom,pmic-id = "k"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index 4e0b013e25f4..df39a64da923 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -40,7 +40,7 @@ /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ &apps_rsc { - pmg1110-regulators { + regulators-2 { compatible = "qcom,pmg1110-rpmh-regulators"; qcom,pmic-id = "k"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index ba64316b4427..15222e92e3f5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -25,7 +25,7 @@ }; &apps_rsc { - pmr735a-regulators { + regulators-2 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 388770be8f13..5dc9bee28e7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -184,7 +184,7 @@ }; &apps_rsc { - pm7325-regulators { + regulators-0 { compatible = "qcom,pm7325-rpmh-regulators"; qcom,pmic-id = "b"; @@ -279,7 +279,7 @@ }; }; - pm8350c-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 88204f794ccb..cb0cc2ba2fa3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -87,7 +87,7 @@ * are left out of here since they are managed elsewhere. */ - pm7325-regulators { + regulators-0 { compatible = "qcom,pm7325-rpmh-regulators"; qcom,pmic-id = "b"; @@ -188,7 +188,7 @@ }; }; - pm8350c-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; -- cgit v1.2.3 From 2458a305e80ef736ae03e6ca0bcae4c3f6923163 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:33 +0100 Subject: arm64: dts: qcom: sm8350: switch to combo usb3/dp phy The first QMP PHY is an USB3/DP combo phy, switch to the newly documented bindings and register the clocks to the GCC and DISPCC controllers. Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov #SM8350-HDK Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-2-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 42 +++++++++++++----------------------- 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 86d887a1c3eb..4907aa68e584 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -660,7 +661,7 @@ <&ufs_mem_phy_lanes 0>, <&ufs_mem_phy_lanes 1>, <&ufs_mem_phy_lanes 2>, - <0>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>; }; @@ -2133,37 +2134,24 @@ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8350-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sm8350-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; }; usb_2_qmpphy: phy-wrapper@88eb000 { @@ -2269,7 +2257,7 @@ iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; ports { @@ -2653,8 +2641,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, - <0>; + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", -- cgit v1.2.3 From a2802008af93b70165a80624082c695d89f51eb2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:34 +0100 Subject: arm64: dts: qcom: sm8350: add dp controller Add the Display Port controller subnode to the MDSS node. Tested-by: Dmitry Baryshkov #SM8350-HDK Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-3-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 79 ++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 4907aa68e584..d9d7ee90d5d4 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2435,6 +2435,85 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; + }; + }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; }; -- cgit v1.2.3 From d3054cec1e9ea475e53280724db62b62e25669d7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:35 +0100 Subject: arm64: dts: qcom: sm8450: switch to usb3/dp combo phy The QMP PHY is a USB3/DP combo phy, switch to the newly documented bindings and register the clocks to the GCC and DISPCC controllers. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-4-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 +++++++++++++----------------------- 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 357ef1d275c9..c334200cd54b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -747,7 +748,7 @@ <&ufs_mem_phy_lanes 0>, <&ufs_mem_phy_lanes 1>, <&ufs_mem_phy_lanes 2>, - <0>; + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk", @@ -2033,37 +2034,24 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sm8450-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; }; remoteproc_slpi: remoteproc@2400000 { @@ -2970,8 +2958,8 @@ <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, /* dp0 */ - <0>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */ @@ -4167,7 +4155,7 @@ iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; ports { -- cgit v1.2.3 From bdd2f4ce5e762d5aede6c30ae161e377536dae1c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:36 +0100 Subject: arm64: dts: qcom: sm8450: add dp controller Add the Display Port controller subnode to the MDSS node. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-5-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index c334200cd54b..d8f18e07383d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2749,6 +2749,13 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2781,6 +2788,78 @@ }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; -- cgit v1.2.3 From 1681ce3735483ab6897e403a20a7faf5c34c1f09 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 20 Mar 2023 14:57:09 +0100 Subject: arm64: dts: qcom: sc8280xp-pmics: fix sdam 'reg' property The SPMI PMIC register region width is fixed and should not be encoded in the devicetree. Fixes: d6dbbda37ab5 ("arm64: dts: qcom: sc8280xp-pmics: add pmk8280 sdam nvram") Signed-off-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230320135710.1989-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 1411edd42b25..c35e7f6bd657 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -107,7 +107,7 @@ pmk8280_sdam_6: nvram@8500 { compatible = "qcom,spmi-sdam"; - reg = <0x8500 0x100>; + reg = <0x8500>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; -- cgit v1.2.3 From a246c20c45a0a2bf5e865a4c3a76822b79b38c80 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 20:30:48 +0100 Subject: arm64: dts: qcom: sdm850-lenovo-yoga-c630: Use proper WSA881x shutdown GPIO polarity The WSA881x shutdown GPIO is active low (SD_N), but Linux driver assumed DTS always comes with active high. Since Linux drivers were updated to handle proper flag, correct the DTS. The change is not backwards compatible with older Linux kernel. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322193051.826167-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 67d2a663ce75..5c688cb6a7ce 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -753,7 +753,7 @@ left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrLeft"; #sound-dai-cells = <0>; @@ -761,7 +761,7 @@ right_spkr: speaker@0,4 { compatible = "sdw10217211000"; - powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>; reg = <0 4>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrRight"; -- cgit v1.2.3 From 5b91fab8eae27d1436eacde60107bab9987bbd9d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 20:30:49 +0100 Subject: arm64: dts: qcom: sdm850-samsung-w737: Use proper WSA881x shutdown GPIO polarity The WSA881x shutdown GPIO is active low (SD_N), but Linux driver assumed DTS always comes with active high. Since Linux drivers were updated to handle proper flag, correct the DTS. The change is not backwards compatible with older Linux kernel. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322193051.826167-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 9850140514ba..41f59e32af64 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -662,7 +662,7 @@ left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrLeft"; #sound-dai-cells = <0>; @@ -670,7 +670,7 @@ right_spkr: speaker@0,4 { compatible = "sdw10217211000"; - powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>; reg = <0 4>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrRight"; -- cgit v1.2.3 From 4ded91530544afdbac350f609e6597076f569e52 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 20:30:50 +0100 Subject: arm64: dts: qcom: sm8250-mtp: Use proper WSA881x shutdown GPIO polarity The WSA881x shutdown GPIO is active low (SD_N), but Linux driver assumed DTS always comes with active high. Since Linux drivers were updated to handle proper flag, correct the DTS. The change is not backwards compatible with older Linux kernel. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322193051.826167-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index e54cdc8bc31f..4c9de236676d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -764,7 +764,7 @@ left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; - powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrLeft"; #sound-dai-cells = <0>; @@ -773,7 +773,7 @@ right_spkr: speaker@0,4 { compatible = "sdw10217211000"; reg = <0 4>; - powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_LOW>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrRight"; #sound-dai-cells = <0>; -- cgit v1.2.3 From 41841f120345be87a12a4096ebcc2d2959c484ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 20:30:51 +0100 Subject: arm64: dts: qcom: qrb5165-rb5: Use proper WSA881x shutdown GPIO polarity The WSA881x shutdown GPIO is active low (SD_N), but Linux driver assumed DTS always comes with active high. Since Linux drivers were updated to handle proper flag, correct the DTS. The change is not backwards compatible with older Linux kernel. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322193051.826167-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index aa0a7bd7307c..dd924331b0ee 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1012,7 +1012,7 @@ left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; - powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrLeft"; #sound-dai-cells = <0>; @@ -1021,7 +1021,7 @@ right_spkr: speaker@0,4 { compatible = "sdw10217211000"; reg = <0 4>; - powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; #thermal-sensor-cells = <0>; sound-name-prefix = "SpkrRight"; #sound-dai-cells = <0>; -- cgit v1.2.3 From 4367d763698c5c7c2c0e540f0508e48b337c7d8a Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 24 Mar 2023 10:47:44 +0100 Subject: arm64: dts: qcom: sc8280xp-x13s: enable alternate touchpad Enable both touchpad nodes in the devictree and let the HID driver determine which one is actually populated (by attempting to read from each i2c address). Ideally this would not be needed and the boot firmware should instead enable only the node for the populated touchpad, but this is unlikely to ever be realised for the X13s. Note that the pin configuration must currently be moved to the parent i2c-bus node even though only one of these nodes will ever be successfully probed on a specific device (e.g. to allow them to be probed in parallel). Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324094744.20448-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 0d1e49ddd540..19d5ac6591fa 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -603,7 +603,7 @@ clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&i2c21_default>; + pinctrl-0 = <&i2c21_default>, <&tpad_default>; status = "okay"; @@ -616,12 +616,7 @@ vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_s10b>; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; - wakeup-source; - - status = "disabled"; }; touchpad@2c { @@ -633,9 +628,6 @@ vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_s10b>; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; - wakeup-source; }; -- cgit v1.2.3 From 72630ba422b70ea0874fc90d526353cf71c72488 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 24 Mar 2023 05:16:50 +0300 Subject: arm64: dts: qcom: ipq8074-hk01: enable QMP device, not the PHY node Correct PCIe PHY enablement to refer the QMP device nodes rather than PHY device nodes. QMP nodes have 'status = "disabled"' property in the ipq8074.dtsi, while PHY nodes do not correspond to the actual device and do not have the status property. Fixes: e8a7fdc505bb ("arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on address") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324021651.1799969-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index ca3f96646b90..5cf07caf4103 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -62,11 +62,11 @@ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; -&pcie_phy0 { +&pcie_qmp0 { status = "okay"; }; -&pcie_phy1 { +&pcie_qmp1 { status = "okay"; }; -- cgit v1.2.3 From 1dc40551f206d20b7e46ea7dd538dcdd928451c6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 24 Mar 2023 05:16:51 +0300 Subject: arm64: dts: qcom: ipq8074-hk10: enable QMP device, not the PHY node Correct PCIe PHY enablement to refer the QMP device nodes rather than PHY device nodes. QMP nodes have 'status = "disabled"' property in the ipq8074.dtsi, while PHY nodes do not correspond to the actual device and do not have the status property. Fixes: 1ed34da63a37 ("arm64: dts: qcom: Add board support for HK10") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324021651.1799969-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 651a231554e0..1b8379ba87f9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -48,11 +48,11 @@ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; -&pcie_phy0 { +&pcie_qmp0 { status = "okay"; }; -&pcie_phy1 { +&pcie_qmp1 { status = "okay"; }; -- cgit v1.2.3 From c98a56395e7854f7975dd8539d0563e0ac7d060e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:28:48 +0100 Subject: arm64: dts: qcom: sm8450: remove invalid power-domain-names in pcie nodes Fixes the following DT bindings check error: pci@1c00000: Unevaluated properties are not allowed ('power-domain-names' were unexpected) Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-3-0ca1bea1a843@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d8f18e07383d..16a1fbb2b9da 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1798,7 +1798,6 @@ reset-names = "pci"; power-domains = <&gcc PCIE_0_GDSC>; - power-domain-names = "gdsc"; phys = <&pcie0_lane>; phy-names = "pciephy"; @@ -1912,7 +1911,6 @@ reset-names = "pci"; power-domains = <&gcc PCIE_1_GDSC>; - power-domain-names = "gdsc"; phys = <&pcie1_lane>; phy-names = "pciephy"; -- cgit v1.2.3 From e57430d2483506f046e39bf8c61159dde88aede2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:28:49 +0100 Subject: arm64: dts: qcom: sm8450: fix pcie1 gpios properties name Add the final "s" to the pgio properties and fix the invalid "enable" name to the correct "wake", checked against the HDK8450 schematics. Fixes: bc6588bc25fb ("arm64: dts: qcom: sm8450: add PCIe1 root device") Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-4-0ca1bea1a843@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 16a1fbb2b9da..08381fd3729d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1915,8 +1915,8 @@ phys = <&pcie1_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; -- cgit v1.2.3 From 704e26678c8d50d8988e30a47edddbb361e9e973 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:41 +0100 Subject: arm64: dts: qcom: apq8096-db820c: drop simple-bus from clocks 'clocks' node is not a bus, but just a placeholder for clocks: apq8096-db820c.dtb: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: dtschema/schemas/simple-bus.yaml apq8096-db820c.dtb: clocks: xo-board: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], ... From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 5ceaab5d4039..c965a8c81d9b 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -63,7 +63,6 @@ }; clocks { - compatible = "simple-bus"; divclk4: divclk4 { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit v1.2.3 From 5574a5022df4cf67fdcf8c94bfbafb2cc296beee Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:42 +0100 Subject: arm64: dts: qcom: msm8994-msft-lumia: drop simple-bus from clocks 'clocks' node is not a bus, but just a placeholder for clocks: msm8992-msft-lumia-octagon-talkman.dtb: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: dtschema/schemas/simple-bus.yaml msm8992-msft-lumia-octagon-talkman.dtb: clocks: xo-board: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], ... From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 4520a7e86d5b..e9480c4208f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -46,8 +46,6 @@ }; clocks { - compatible = "simple-bus"; - divclk4: divclk4 { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit v1.2.3 From 338958e30c6897b7978019b5ea3fa1897cd511ba Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:43 +0100 Subject: arm64: dts: qcom: msm8996-xiaomi: drop simple-bus from clocks 'clocks' node is not a bus, but just a placeholder for clocks: msm8996-xiaomi-gemini.dtb: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: dtschema/schemas/simple-bus.yaml msm8996-xiaomi-gemini.dtb: clocks: xo-board: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], ... From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 446b1d23dec0..1ce5df0a3405 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -12,8 +12,6 @@ / { clocks { - compatible = "simple-bus"; - divclk1_cdc: divclk1 { compatible = "gpio-gate-clock"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>; -- cgit v1.2.3 From a2e5260d07555834d14431399cefdd3220b917d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:44 +0100 Subject: arm64: dts: qcom: sdm630: move DSI opp-table into DSI node The soc node is supposed to have only device nodes with MMIO addresses, so move the DSI OPP into the DSI controller node to fix: sda660-inforce-ifc6560.dtb: soc: opp-table-dsi: {'compatible': ['operating-points-v2'], ... should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 38 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 72d9a12b5e9c..8bdb36a63474 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1450,25 +1450,6 @@ <0>; }; - dsi_opp_table: opp-table-dsi { - compatible = "operating-points-v2"; - - opp-131250000 { - opp-hz = /bits/ 64 <131250000>; - required-opps = <&rpmpd_opp_svs>; - }; - - opp-210000000 { - opp-hz = /bits/ 64 <210000000>; - required-opps = <&rpmpd_opp_svs_plus>; - }; - - opp-262500000 { - opp-hz = /bits/ 64 <262500000>; - required-opps = <&rpmpd_opp_nom>; - }; - }; - mdss: display-subsystem@c900000 { compatible = "qcom,mdss"; reg = <0x0c900000 0x1000>, @@ -1610,6 +1591,25 @@ status = "disabled"; + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-262500000 { + opp-hz = /bits/ 64 <262500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From d97e712be401a67e0db8e79612b30d65e9619f41 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Mar 2023 14:32:43 +0200 Subject: arm64: dts: qcom: sc8280xp-x13s: drop bogus 'input-enable' The sc8280xp pin controller does not have a way to enable or disable the input buffer so drop the unnecessary 'input-enable' property which is about to be deprecated. Link: https://lore.kernel.org/lkml/20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327123243.4527-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 19d5ac6591fa..7c7273e8ce9b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1182,7 +1182,6 @@ hall_int_n_default: hall-int-n-state { pins = "gpio107"; function = "gpio"; - input-enable; bias-disable; }; -- cgit v1.2.3 From 280e05a3942a010cdd3bfd8b32ae00efb6761dea Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Mar 2023 14:29:48 +0200 Subject: arm64: dts: qcom: sc8280xp-pmics: fix pon compatible and registers The pmk8280 PMIC PON peripheral is gen3 and uses two sets of registers; hlos and pbs. This specifically fixes the following error message during boot when the pbs registers are not defined: PON_PBS address missing, can't read HW debounce time Note that this also enables the spurious interrupt workaround introduced by commit 0b65118e6ba3 ("Input: pm8941-pwrkey - add software key press debouncing support") (which may or may not be needed). Fixes: ccd3517faf18 ("arm64: dts: qcom: sc8280xp: Add reference device") Signed-off-by: Johan Hovold Tested-by: Steev Klimaszewski #Thinkpad X13s Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327122948.4323-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index c35e7f6bd657..a0ba535bb6c9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -59,8 +59,9 @@ #size-cells = <0>; pmk8280_pon: pon@1300 { - compatible = "qcom,pm8998-pon"; - reg = <0x1300>; + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; pmk8280_pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; -- cgit v1.2.3 From c747968cf945d7d57d117e4414465fdacb26ab4b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:43 +0200 Subject: arm64: dts: qcom: sdm845-cheza: use just "port" in Innolux panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sdm845-cheza-r2.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index f2b48241d15c..59ad6a8403d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -135,11 +135,9 @@ backlight = <&backlight>; no-hpd; - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; }; }; }; -- cgit v1.2.3 From e3cc58599167db818fbcba3b0c3debb3d6776f4a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:44 +0200 Subject: arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc8280xp-lenovo-thinkpad-x13s.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7c7273e8ce9b..3bd36a4ac205 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -549,11 +549,9 @@ backlight = <&backlight>; power-supply = <&vreg_edp_3p3>; - ports { - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss0_dp3_out>; - }; + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; }; }; }; -- cgit v1.2.3 From 78f7be3c4c2abcd5845f6acb30754173c4aed4b3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:45 +0200 Subject: arm64: dts: qcom: sc8280xp-crd: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc8280xp-crd.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index d7b537284990..6b4e1541ee39 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -413,11 +413,9 @@ backlight = <&backlight>; - ports { - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss0_dp3_out>; - }; + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; }; }; }; -- cgit v1.2.3 From 746bda7d9dd9518793034d7008a19e4cf5c3004d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:46 +0200 Subject: arm64: dts: qcom: sc7180-idp: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7180-idp.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' sc7180-idp.dtb: panel@0: 'port' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index c3bdd3295c02..fcabbc6a897f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -312,14 +312,9 @@ reset-gpios = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; -- cgit v1.2.3 From 88904a12fbcbd97e56d341080845ce0807164fb5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:47 +0200 Subject: arm64: dts: qcom: sc7180-trogdor-quackingstick: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7180-trogdor-quackingstick-r0.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index cb41ccdaccfd..8e7b42f843d4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -65,14 +65,9 @@ backlight = <&backlight>; rotation = <270>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; -- cgit v1.2.3 From c28d9029f3b68a42794a0527696c91f7b31e81f3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:48 +0200 Subject: arm64: dts: qcom: sc7180-trogdor-wormdingler: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7180-trogdor-wormdingler-rev1-boe.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 9832e752da35..262d6691abd9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -124,14 +124,9 @@ backlight = <&backlight>; rotation = <270>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; -- cgit v1.2.3 From ff5508b93b9c5dd723ac68c315be1cf727845063 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:49 +0200 Subject: arm64: dts: qcom: sc7180-qcard: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7280-herobrine-zombie-nvme-lte.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index cb0cc2ba2fa3..88b3586e389f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -354,14 +354,9 @@ backlight = <&pm8350c_pwm_backlight>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - edp_panel_in: endpoint { - remote-endpoint = <&mdss_edp_out>; - }; + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_edp_out>; }; }; }; -- cgit v1.2.3 From 9ec6040a48300a7527e46505e121f71a3e0f924f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:50 +0200 Subject: arm64: dts: qcom: sc7180-trogdor-lazor: correct panel compatible innolux,n116bca-ea1 is not exactly compatible witg innolux,n116bge, as they have their own driver data. Bindings do not allow fallback: sc7180-trogdor-lazor-limozeen-nots-r4.dtb: panel: compatible: ['innolux,n116bca-ea1', 'innolux,n116bge'] is too long Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts index 235cda2bba5e..7f01573b5543 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts @@ -23,7 +23,7 @@ /delete-node/&ap_ts; &panel { - compatible = "innolux,n116bca-ea1", "innolux,n116bge"; + compatible = "innolux,n116bca-ea1"; }; &sdhc_2 { -- cgit v1.2.3 From 9f3c858ecde007b147491d5f9d19484090fbe3b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:51 +0200 Subject: arm64: dts: qcom: sdm845-oneplus: drop invalid panel properties Panel does not have children with unit-addresses thus address/size-cells are not valid: panel@0: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index b01542d79ae2..0c268c560d37 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -347,8 +347,6 @@ display_panel: panel@0 { status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; vddio-supply = <&vreg_l14a_1p88>; -- cgit v1.2.3 From e12482e688303d93507ae7c1346a27dbaa1811fb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:52 +0200 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: drop invalid panel properties Panel does not have children with unit-addresses thus address/size-cells are not valid: sdm845-xiaomi-beryllium-tianma.dtb: panel@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index e0fda4d754fe..e444ef1cd742 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -232,9 +232,6 @@ vddpos-supply = <&lab>; vddneg-supply = <&ibb>; - #address-cells = <1>; - #size-cells = <0>; - backlight = <&pmi8998_wled>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From 0514b376da09f9e4a6a4581112bcac063ee3ad9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:53 +0200 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: correct compatible Tianma FHD panel is supposed to be used with fallback compatible: sdm845-xiaomi-beryllium-tianma.dtb: panel@0: compatible: ['tianma,fhd-video'] is too short Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-11-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts index 8e176111e599..e9427851ebaa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts @@ -10,6 +10,6 @@ }; &display_panel { - compatible = "tianma,fhd-video"; + compatible = "tianma,fhd-video", "novatek,nt36672a"; status = "okay"; }; -- cgit v1.2.3 From 3244442406ff49e8f75a1f2def211c497710570f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 9 Mar 2023 10:14:52 +0100 Subject: arm64: dts: qcom: msm8916: Move WCN compatible to boards On MSM8916 the wireless connectivity functionality (WiFi/Bluetooth) is split into the digital part inside the SoC and the analog RF part inside a supplementary WCN36xx chip. For MSM8916, three different options exist: - WCN3620 (WLAN 802.11 b/g/n 2.4 GHz + Bluetooth) - WCN3660B (WLAN 802.11 a/b/g/n 2.4/5 GHz + Bluetooth) - WCN3680B (WLAN 802.11ac 2.4/5 GHz + Bluetooth) Choosing one of these is up to the board vendor. This means that the compatible belongs into the board-specific DT part so people porting new boards pay attention to set the correct compatible. Right now msm8916.dtsi sets "qcom,wcn3620" as default compatible, which does not work at all for boards that have WCN3660B or WCN3680B. Remove the default compatible from msm8196.dtsi and move it to the board DT as follows: - Boards with only &pronto { status = "okay"; } used the default "qcom,wcn3620" so far. They now set this explicitly for &wcnss_iris. - Boards with &pronto { ... iris { compatible = "qcom,wcn3660b"; }}; already had an override that just moves to &wcnss_iris now. - For msm8916-samsung-a2015-common.dtsi the WCN compatible differs for boards making use of it (a3u: wcn3620, a5u: wcn3660b, e2015: wcn3620) so the definitions move to the board-specific DT part. Since this requires touching all the board DTs, use this as a chance to name the WCNSS-related labels consistently, so everything is grouped properly when sorted alphabetically. No functional change, just clean-up for more clarity & easier porting. Aside from ordering the generated DTBs are identical. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309091452.1011776-1-stephan.gerhold@kernkonzept.com --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 15 +++++++++------ arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 12 ++++++++---- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 12 ++++++++---- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 12 ++++++++---- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 22 +++++++++++----------- .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 4 ---- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 8 ++++++++ .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 14 ++++++++------ .../dts/qcom/msm8916-samsung-e2015-common.dtsi | 8 ++++++++ .../boot/dts/qcom/msm8916-samsung-gt5-common.dtsi | 16 ++++++++-------- .../boot/dts/qcom/msm8916-samsung-j5-common.dtsi | 12 ++++++++---- .../boot/dts/qcom/msm8916-samsung-serranove.dts | 16 ++++++++-------- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 12 ++++++++---- .../boot/dts/qcom/msm8916-wingtech-wt88047.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/msm8916.dtsi | 13 ++++++------- 19 files changed, 146 insertions(+), 90 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index c52d79a55d80..27ceaa94c8bd 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -325,12 +325,6 @@ linux,code = ; }; -&pronto { - status = "okay"; - - firmware-name = "qcom/apq8016/wcnss.mbn"; -}; - &sdhc_1 { status = "okay"; @@ -411,10 +405,19 @@ qcom,mbhc-vthreshold-high = <75 150 237 450 500>; }; +&wcnss { + status = "okay"; + firmware-name = "qcom/apq8016/wcnss.mbn"; +}; + &wcnss_ctrl { firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; }; +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + /* Enable CoreSight */ &cti0 { status = "okay"; }; &cti1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index ed3fa7b3575b..13cd9ad167df 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -118,10 +118,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; @@ -149,6 +145,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 701a5585d77e..fecb69944cfa 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -160,10 +160,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -191,6 +187,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 3618704a5330..91284a1d0966 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -128,10 +128,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -159,6 +155,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index a0e520edde02..525ec76efeeb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -118,10 +118,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -149,6 +145,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 8c07eca900d3..5b1bac8f5122 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -227,10 +227,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -312,6 +308,14 @@ qcom,hphl-jack-type-normally-open; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index d1e8cf2f50c0..f1dd625e1822 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -231,10 +231,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -263,6 +259,14 @@ extcon = <&pm8916_usbin>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 3899e11b9843..b79e80913af9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -99,10 +99,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -130,6 +126,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 8cac23b5240c..6eb5e0a39510 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -20,17 +20,6 @@ pll-supply = <&pm8916_l7>; }; -&pronto { - vddpx-supply = <&pm8916_l7>; - - iris { - vddxo-supply = <&pm8916_l7>; - vddrfa-supply = <&pm8916_s3>; - vddpa-supply = <&pm8916_l9>; - vdddig-supply = <&pm8916_l5>; - }; -}; - &sdhc_1 { vmmc-supply = <&pm8916_l8>; vqmmc-supply = <&pm8916_l5>; @@ -46,6 +35,17 @@ v3p3-supply = <&pm8916_l13>; }; +&wcnss { + vddpx-supply = <&pm8916_l7>; +}; + +&wcnss_iris { + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; +}; + &rpm_requests { smd_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index a2ed7bdbf528..16d67749960e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -252,10 +252,6 @@ linux,code = ; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index c691cca2eb45..a1ca4d883420 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -112,6 +112,14 @@ status = "okay"; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &msmgpio { panel_vdd3_default: panel-vdd3-default-state { pins = "gpio9"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 3dd819458785..4e10b8a5e9f9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -54,12 +54,6 @@ status = "okay"; }; -&pronto { - iris { - compatible = "qcom,wcn3660b"; - }; -}; - &touchkey { vcc-supply = <®_touch_key>; vdd-supply = <®_touch_key>; @@ -69,6 +63,14 @@ status = "okay"; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + &msmgpio { tkey_en_default: tkey-en-default-state { pins = "gpio97"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index c95f0b4bc61f..f6c4a011fdfd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -58,6 +58,14 @@ vdd-supply = <®_touch_key>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &msmgpio { tkey_en_default: tkey-en-default-state { pins = "gpio97"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index d920b7247d82..74ffd04db8d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -125,14 +125,6 @@ status = "okay"; }; -&pronto { - status = "okay"; - - iris { - compatible = "qcom,wcn3660b"; - }; -}; - &sdhc_1 { pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -162,6 +154,14 @@ extcon = <&pm8916_usbin>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index f3b81b6f0a2f..adeee0830e76 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -93,10 +93,6 @@ linux,code = ; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -124,6 +120,14 @@ extcon = <&muic>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index d4984b3af802..1a41a4db874d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -272,14 +272,6 @@ status = "okay"; }; -&pronto { - status = "okay"; - - iris { - compatible = "qcom,wcn3660b"; - }; -}; - &sdhc_1 { status = "okay"; @@ -320,6 +312,14 @@ extcon = <&muic>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index cdf34b74fa8f..50bae6f214f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -99,10 +99,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -122,6 +118,14 @@ extcon = <&pm8916_usbin>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index a87be1d95b14..ac56c7595f78 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -153,10 +153,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -184,6 +180,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 639b158b4fbe..7e0fa37a3adf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1870,7 +1870,7 @@ }; }; - pronto: remoteproc@a21b000 { + wcnss: remoteproc@a21b000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; @@ -1896,9 +1896,8 @@ status = "disabled"; - iris { - compatible = "qcom,wcn3620"; - + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ clocks = <&rpmcc RPM_SMD_RF_CLK2>; clock-names = "xo"; }; @@ -1916,13 +1915,13 @@ compatible = "qcom,wcnss"; qcom,smd-channels = "WCNSS_CTRL"; - qcom,mmio = <&pronto>; + qcom,mmio = <&wcnss>; - bluetooth { + wcnss_bt: bluetooth { compatible = "qcom,wcnss-bt"; }; - wifi { + wcnss_wifi: wifi { compatible = "qcom,wcnss-wlan"; interrupts = , -- cgit v1.2.3 From 7a888e143f0c87017d91490ea9d0ecc2dc21f2a9 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Fri, 10 Mar 2023 22:33:30 +0800 Subject: arm64: dts: qcom: msm8916-yiming-uz801v3: Add initial device tree This commit adds support for the uz801 v3.0 WiFi/LTE dongle made by Henan Yiming Technology Co., Ltd. based on MSM8916. Note: The original firmware does not support 64-bit OS. It is necessary to flash 64-bit TZ firmware to boot arm64. Currently supported: - All CPU cores - Buttons - LEDs - Modem - SDHC - USB Device Mode - UART Signed-off-by: Yang Xiwen Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_62395CA0D608DD0078DD3D889F6E4E22BA05@qq.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts | 35 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1a29403400b7..f6ff4024a60e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts new file mode 100644 index 000000000000..74ce6563be18 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-ufi.dtsi" + +/ { + model = "uz801 v3.0 4G Modem Stick"; + compatible = "yiming,uz801-v3", "qcom,msm8916"; +}; + +&button_restart { + gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>; +}; + +&led_r { + gpios = <&msmgpio 7 GPIO_ACTIVE_HIGH>; +}; + +&led_g { + gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; +}; + +&led_b { + gpios = <&msmgpio 6 GPIO_ACTIVE_HIGH>; +}; + +&button_default { + pins = "gpio23"; + bias-pull-up; +}; + +&gpio_leds_default { + pins = "gpio6", "gpio7", "gpio8"; +}; -- cgit v1.2.3 From 0d8d77228aa1efec69f92ef92e1cd9270c1151c4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:15 +0100 Subject: arm64: dts: qcom: sda660-inforce: correct key node name gpio-key bindings expect children to be named with generic prefix: sda660-inforce-ifc6560.dtb: gpio-keys: 'volup' does not match any of the regexes: ... Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 7c81918eee66..7459525d9982 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -29,7 +29,7 @@ gpio-keys { compatible = "gpio-keys"; - volup { + key-volup { label = "Volume Up"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,code = ; -- cgit v1.2.3 From de88b1759b35086d5e63736fb604ea2d06486b1a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:16 +0100 Subject: arm64: dts: qcom: sc7280-herobrine-villager: correct trackpad supply The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other Herobrine boards which use elan,ekth3000 with valid VCC: sc7280-herobrine-villager-r1-lte.dtb: trackpad@2c: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: ee2a62116015 ("arm64: dts: qcom: sc7280: Add device tree for herobrine villager") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 818d4046d2c7..38c8a3679fcb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -33,7 +33,7 @@ ap_tp_i2c: &i2c0 { interrupts = <7 IRQ_TYPE_EDGE_FALLING>; hid-descr-addr = <0x20>; - vcc-supply = <&pp3300_z1>; + vdd-supply = <&pp3300_z1>; wakeup-source; }; -- cgit v1.2.3 From 52e2996f253d82520011340d40dbc1c76ea79208 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:17 +0100 Subject: arm64: dts: qcom: sc7180-trogdor-lazor: correct trackpad supply The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other boards which use elan,ekth3000 with valid VCC: sc7180-trogdor-lazor-limozeen-nots-r4.dtb: trackpad@2c: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: 2c26adb8dbab ("arm64: dts: qcom: Add sc7180-lazor-limozeen skus") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts index 850776c5323d..70d5a7aa8873 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts @@ -26,7 +26,7 @@ interrupt-parent = <&tlmm>; interrupts = <58 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&pp3300_fp_tp>; + vdd-supply = <&pp3300_fp_tp>; hid-descr-addr = <0x20>; wakeup-source; -- cgit v1.2.3 From 24f39eec6a70768e7c2eb2f3d8158f45050ff75a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:18 +0100 Subject: arm64: dts: qcom: sc7180-trogdor-pazquel: correct trackpad supply The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other boards which use elan,ekth3000 with valid VCC: sc7180-trogdor-pazquel360-lte.dtb: trackpad@15: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: fb69f6adaf88 ("arm64: dts: qcom: sc7180: Add pazquel dts files") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index d06cc4ea3375..8823edbb4d6e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -39,7 +39,7 @@ interrupt-parent = <&tlmm>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&pp3300_fp_tp>; + vdd-supply = <&pp3300_fp_tp>; post-power-on-delay-ms = <100>; hid-descr-addr = <0x0001>; -- cgit v1.2.3 From 97b4fdc6b82d6d5cfb92a9b164540278720fb700 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:19 +0100 Subject: arm64: dts: qcom: msm8998-oneplus-cheeseburger: revert "fix backlight pin function" This reverts commit 46546f28825cf3a5ef6873b9cf947cd85c8a7258 because it mistakenly took PMIC pinctrl/GPIO as TLMM. The TLMM pinctrl uses "gpio" function, but PMIC uses "normal", so original code was correct: msm8998-oneplus-cheeseburger.dtb: pmic@2: gpio@c000:button-backlight-state: 'oneOf' conditional failed, one must be fixed: 'gpio' is not one of ['normal', 'paired', 'func1', 'func2', 'dtest1', 'dtest2', 'dtest3', 'dtest4', 'func3', 'func4'] Fixes: 46546f28825c ("arm64: dts: qcom: msm8998-oneplus-cheeseburger: fix backlight pin function") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index d36b36af49d0..fac8b3510cd3 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -34,7 +34,7 @@ &pmi8998_gpios { button_backlight_default: button-backlight-state { pins = "gpio5"; - function = "gpio"; + function = "normal"; bias-pull-down; qcom,drive-strength = ; }; -- cgit v1.2.3 From 3555dd528ba9c08d6ccd56239c695dbeac3b63e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:20 +0100 Subject: arm64: dts: qcom: msm8994-kitakami: drop unit address from PMI8994 regulator The PMIC regulators are not supposed to have unit addresses. Fixes: e9783584c9b7 ("arm64: dts: qcom: msm8994-kitakami: Add VDD_GFX regulator") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 3ceb86b06209..26059f861250 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -173,8 +173,7 @@ * power domain.. which still isn't enough and forces us to bind * OXILI_CX and OXILI_GX together! */ - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; + vdd_gfx: s2 { regulator-name = "VDD_GFX"; regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; -- cgit v1.2.3 From 7a202df0f3eed006e4a9e7c06d62cf67be56c14c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:21 +0100 Subject: arm64: dts: qcom: msm8994-msft-lumia-octagon: drop unit address from PMI8994 regulator The PMIC regulators are not supposed to have unit addresses. Fixes: 60b214effb80 ("arm64: dts: qcom: msm8994-octagon: Configure regulators") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index e9480c4208f6..2861bcdf87b7 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -540,8 +540,7 @@ }; &pmi8994_spmi_regulators { - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; + vdd_gfx: s2 { regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; }; -- cgit v1.2.3 From ec57cbce1a6d9384f8ac1ff966b204dc262f4927 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:22 +0100 Subject: arm64: dts: qcom: apq8096-db820c: drop unit address from PMI8994 regulator The PMIC regulators are not supposed to have unit addresses. Fixes: 2317b87a2a6f ("arm64: dts: qcom: db820c: Add vdd_gfx and tie it into mmcc") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 3 +-- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index c965a8c81d9b..b599909c4463 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -703,8 +703,7 @@ &pmi8994_spmi_regulators { vdd_s2-supply = <&vph_pwr>; - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; + vdd_gfx: s2 { regulator-name = "VDD_GFX"; regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index a0af91698d49..0192968f4d9b 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -49,8 +49,6 @@ pmi8994_spmi_regulators: regulators { compatible = "qcom,pmi8994-regulators"; - #address-cells = <1>; - #size-cells = <1>; }; pmi8994_wled: wled@d800 { -- cgit v1.2.3 From 6209038f131fee84ff1536dc59864f54d06740f2 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 13 Mar 2023 18:27:31 +0530 Subject: arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on QDU1000 and QRU1000 SoCs. Signed-off-by: Komal Bajaj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313125731.17745-1-quic_kbajaj@quicinc.com --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 99d784085fb3..734438113bba 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1321,6 +1321,18 @@ qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + + system-cache-controller@19200000 { + compatible = "qcom,qdu1000-llcc"; + reg = <0 0x19200000 0 0xd80000>, + <0 0x1a200000 0 0x80000>, + <0 0x221c8128 0 0x4>; + reg-names = "llcc_base", + "llcc_broadcast_base", + "multi_channel_register"; + interrupts = ; + multi-ch-bit-off = <24 2>; + }; }; timer { -- cgit v1.2.3 From d20ad168b7d024d8cbe6b54e9c029537aa412576 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Mon, 13 Mar 2023 10:42:26 -0500 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: add notification LED The Poco F1 has a single color white notification LED. Enable the Qualcomm Light Pulse Generator (LPG) driver based notification LED. Signed-off-by: Joel Selvaraj Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313154226.136726-1-joelselvaraj.oss@gmail.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index e444ef1cd742..5ed975cc6ecb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -2,6 +2,7 @@ /dts-v1/; +#include #include #include #include @@ -319,6 +320,16 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + led@5 { + reg = <5>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + &pmi8998_wled { status = "okay"; qcom,current-boost-limit = <970>; -- cgit v1.2.3 From 900007f26aa82e28ac4f494cd0121a75673d39ff Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 14 Mar 2023 14:28:34 +0100 Subject: arm64: dts: qcom: msm8998-yoshino: Use SONY GPIO names Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Yoshino devices DTs to better document the hardware. Lilac and Poplar have identical pin assignments. Diff between these two and maple: TLMM: - "NC", + "TS_VDDIO_EN", PMI8998: - "NC" + "USB_SWITCH_SEL" - "NC" + "4K_DISP_DCDC_EN" PM8005: - "NC" + "EAR_EN" Which is probably due to Maple being designed and released quite a bit earlier than the other two and it having a super high tech true-4K display. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-yoshino_gpio-v2-1-4cb80e187e38@linaro.org --- .../dts/qcom/msm8998-sony-xperia-yoshino-maple.dts | 175 ++++++++++++++++++ .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 199 +++++++++++++++++++++ 2 files changed, 374 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 1868ad649415..8b6a718835c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -37,7 +37,29 @@ qcom,soft-start-us = <200>; }; +&pm8005_gpios { + gpio-line-names = "EAR_EN", /* GPIO_1 */ + "NC", + "SLB", + "OPTION_1_PM8005"; +}; + &pmi8998_gpios { + gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */ + "NC", + "NC", + "TYPEC_UUSB_SEL", + "VIB_LDO_EN", + "NC", + "DISPLAY_TYPE_SEL", + "USB_SWITCH_SEL", + "NC", + "4K_DISP_DCDC_EN", /* GPIO_10 */ + "NC", + "DIV_CLK3", + "SPMI_I2C_SEL", + "NC"; + disp_dvdd_en: disp-dvdd-en-active-state { pins = "gpio10"; function = "normal"; @@ -49,6 +71,159 @@ }; }; +&tlmm { + gpio-line-names = "", /* GPIO_0 */ + "", + "", + "", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "NC", + "NC", + "MDP_VSYNC_P", /* GPIO_10 */ + "RGBC_IR_INT", + "NFC_VEN", + "CAM_MCLK0", + "CAM_MCLK1", + "NC", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "MAIN_CAM_PWR_EN", + "TOF_INT_N", + "NC", + "NC", + "CHAT_CAM_PWR_EN", + "NC", + "TOF_RESET_N", + "CAM2_RSTN", + "NC", + "CAM1_RSTN", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "CC_DIR", + "UIM2_DETECT_EN", + "FP_RESET_N", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "BT_HCI_UART_TXD", + "BT_HCI_UART_RXD", + "BT_HCI_UART_CTS_N", + "BT_HCI_UART_RFR_N", + "NC", + "NC", /* GPIO_50 */ + "NC", + "NC", + "CODEC_INT2_N", + "CODEC_INT1_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "NC", + "TRAY2_DET_DS", + "CODEC_RST_N", + "WSA_L_EN", + "WSA_R_EN", + "NC", + "NC", + "NC", + "LPASS_SLIMBUS_CLK", /* GPIO_70 */ + "LPASS_SLIMBUS_DATA0", + "LPASS_SLIMBUS_DATA1", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "NC", + "NC", /* GPIO_80 */ + "SW_SERVICE", + "TX_GTR_THRES_IN", + "HW_ID0", + "HW_ID1", + "NC", + "NC", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_RESET_N", + "NC", /* GPIO_90 */ + "NC", + "NFC_IRQ", + "NFC_DWLD_EN", + "DISP_RESET_N", + "TRAY2_DET", + "CAM_SOF", + "RFFE6_CLK", + "RFFE6_DATA", + "DEBUG_GPIO0", + "DEBUG_GPIO1", /* GPIO_100 */ + "GRFC4", + "NC", + "NC", + "RSVD", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RST", + "UIM1_PRESENT", + "UIM_BATT_ALARM", + "RSVD", + "NC", + "NC", + "ACCEL_INT", + "GYRO_INT", + "COMPASS_INT", + "ALS_PROX_INT_N", /* GPIO_120 */ + "FP_INT_N", + "NC", + "BAROMETER_INT", + "ACC_COVER_OPEN", + "TS_INT_N", + "NC", + "NC", + "USB_DETECT_EN", + "NC", + "QLINK_REQUEST", /* GPIO_130 */ + "QLINK_ENABLE", + "NC", + "TS_VDDIO_EN", + "WMSS_RESET_N", + "PA_INDICATOR_OR", + "NC", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", /* GPIO_140 */ + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", + "RFFE2_DATA", + "RFFE2_CLK", + "RFFE1_DATA", + "RFFE1_CLK"; +}; + &vreg_l22a_2p85 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index fa02e45f1c24..bb1c1e86ac2a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -292,6 +292,13 @@ regulator-soft-start; }; +&pm8005_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "SLB", + "OPTION_1_PM8005"; +}; + &pm8005_regulators { /* VDD_GFX supply */ pm8005_s1: s1 { @@ -304,6 +311,33 @@ }; &pm8998_gpios { + gpio-line-names = "UIM_BATT_ALARM", /* GPIO_1 */ + "NC", + "WLAN_SW_CTRL (DISALLOWED)", + "SSC_PWR_EN", + "VOL_DOWN_N", + "VOL_UP_N", + "SNAPSHOT_N", + "FOCUS_N", + "FLASH_THERM", + "", /* GPIO_10 */ + "", + "", + "DIV_CLK1", + "NC", + "NC (DISALLOWED)", + "DIV_CLK3", + "NC", + "NC", + "NC", + "NC (DISALLOWED)", /* GPIO_20 */ + "NFC_CLK_REQ", + "NC (DISALLOWED)", + "WCSS_PWR_REQ", + "OPTION_1 (DISALLOWED)", + "OPTION_2 (DISALLOWED)", + "PM_SLB (DISALLOWED)"; + vol_down_pin_a: vol-down-active-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; @@ -336,6 +370,21 @@ }; &pmi8998_gpios { + gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */ + "NC", + "NC", + "TYPEC_UUSB_SEL", + "VIB_LDO_EN", + "NC", + "DISPLAY_TYPE_SEL", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "DIV_CLK3", + "SPMI_I2C_SEL", + "NC"; + cam_vio_default: cam-vio-active-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; @@ -590,6 +639,156 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + gpio-line-names = "", /* GPIO_0 */ + "", + "", + "", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "NC", + "NC", + "MDP_VSYNC_P", /* GPIO_10 */ + "RGBC_IR_INT", + "NFC_VEN", + "CAM_MCLK0", + "CAM_MCLK1", + "NC", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "MAIN_CAM_PWR_EN", + "TOF_INT_N", + "NC", + "NC", + "CHAT_CAM_PWR_EN", + "NC", + "TOF_RESET_N", + "CAM2_RSTN", + "NC", + "CAM1_RSTN", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "CC_DIR", + "UIM2_DETECT_EN", + "FP_RESET_N", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "BT_HCI_UART_TXD", + "BT_HCI_UART_RXD", + "BT_HCI_UART_CTS_N", + "BT_HCI_UART_RFR_N", + "NC", + "NC", /* GPIO_50 */ + "NC", + "NC", + "CODEC_INT2_N", + "CODEC_INT1_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "NC", + "TRAY2_DET_DS", + "CODEC_RST_N", + "WSA_L_EN", + "WSA_R_EN", + "NC", + "NC", + "NC", + "LPASS_SLIMBUS_CLK", /* GPIO_70 */ + "LPASS_SLIMBUS_DATA0", + "LPASS_SLIMBUS_DATA1", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "NC", + "NC", /* GPIO_80 */ + "SW_SERVICE", + "TX_GTR_THRES_IN", + "HW_ID0", + "HW_ID1", + "NC", + "NC", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_RESET_N", + "NC", /* GPIO_90 */ + "NC", + "NFC_IRQ", + "NFC_DWLD_EN", + "DISP_RESET_N", + "TRAY2_DET", + "CAM_SOF", + "RFFE6_CLK", + "RFFE6_DATA", + "DEBUG_GPIO0", + "DEBUG_GPIO1", /* GPIO_100 */ + "GRFC4", + "NC", + "NC", + "RSVD", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RST", + "UIM1_PRESENT", + "UIM_BATT_ALARM", + "RSVD", + "NC", + "NC", + "ACCEL_INT", + "GYRO_INT", + "COMPASS_INT", + "ALS_PROX_INT_N", /* GPIO_120 */ + "FP_INT_N", + "NC", + "BAROMETER_INT", + "ACC_COVER_OPEN", + "TS_INT_N", + "NC", + "NC", + "USB_DETECT_EN", + "NC", + "QLINK_REQUEST", /* GPIO_130 */ + "QLINK_ENABLE", + "NC", + "NC", + "WMSS_RESET_N", + "PA_INDICATOR_OR", + "NC", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", /* GPIO_140 */ + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", + "RFFE2_DATA", + "RFFE2_CLK", + "RFFE1_DATA", + "RFFE1_CLK"; mdp_vsync_n: mdp-vsync-n-state { pins = "gpio10"; -- cgit v1.2.3 From a9eaa4798473fd3cfe39210c64e403d6cbc31984 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 14 Mar 2023 14:28:35 +0100 Subject: arm64: dts: qcom: msm8998-yoshino: Use actual pin names for pin nodes With the gpio-line-names in place coming from SONY themselves, we can now make the pin nodes and their labels to more closely resemble the actual thing. 4k has been renamed to four_k due to dtc limitations. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-yoshino_gpio-v2-2-4cb80e187e38@linaro.org --- .../dts/qcom/msm8998-sony-xperia-yoshino-maple.dts | 4 +- .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 59 +++++++++++----------- 2 files changed, 31 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 8b6a718835c7..055b6a643d82 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -22,7 +22,7 @@ enable-active-high; gpio = <&pmi8998_gpios 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&disp_dvdd_en>; + pinctrl-0 = <&four_k_disp_dcdc_en>; }; }; @@ -60,7 +60,7 @@ "SPMI_I2C_SEL", "NC"; - disp_dvdd_en: disp-dvdd-en-active-state { + four_k_disp_dcdc_en: 4k-disp-dcdc-en-state { pins = "gpio10"; function = "normal"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index bb1c1e86ac2a..8e1c25b15f57 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -21,7 +21,7 @@ clocks { div1_mclk: divclk1 { compatible = "gpio-gate-clock"; - pinctrl-0 = <&audio_mclk_pin>; + pinctrl-0 = <&div_clk1>; pinctrl-names = "default"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>; #clock-cells = <0>; @@ -46,7 +46,7 @@ enable-active-high; gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cam0_vdig_default>; + pinctrl-0 = <&main_cam_pwr_en>; }; cam1_vdig_vreg: cam1-vdig { @@ -56,7 +56,7 @@ enable-active-high; gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cam1_vdig_default>; + pinctrl-0 = <&chat_cam_pwr_en>; vin-supply = <&vreg_s3a_1p35>; }; @@ -67,7 +67,7 @@ enable-active-high; gpio = <&pmi8998_gpios 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cam_vio_default>; + pinctrl-0 = <&main_cam_pwr_io_en>; vin-supply = <&vreg_lvs1a_1p8>; }; @@ -92,15 +92,14 @@ id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&usb_extcon_active &usb_vbus_active>; + pinctrl-0 = <&cc_dir_default &usb_detect_en>; }; gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; pinctrl-names = "default"; - pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, - <&cam_snapshot_pin_a>; + pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>; button-vol-down { label = "Volume Down"; gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; @@ -131,7 +130,7 @@ compatible = "gpio-keys"; label = "Hall sensors"; pinctrl-names = "default"; - pinctrl-0 = <&hall_sensor0_default>; + pinctrl-0 = <&acc_cover_open>; event-hall-sensor0 { label = "Cover Hall Sensor"; @@ -189,7 +188,7 @@ compatible = "gpio-vibrator"; enable-gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vib_default>; + pinctrl-0 = <&vib_ldo_en>; }; }; @@ -263,7 +262,7 @@ vdd-supply = <&cam_vio_vreg>; pinctrl-names = "default"; - pinctrl-0 = <&tof_int &tof_reset>; + pinctrl-0 = <&tof_int_n &tof_reset>; }; }; @@ -338,7 +337,7 @@ "OPTION_2 (DISALLOWED)", "PM_SLB (DISALLOWED)"; - vol_down_pin_a: vol-down-active-state { + vol_down_n: vol-down-n-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -346,7 +345,7 @@ qcom,drive-strength = ; }; - cam_focus_pin_a: cam-focus-btn-active-state { + focus_n: focus-n-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -354,7 +353,7 @@ qcom,drive-strength = ; }; - cam_snapshot_pin_a: cam-snapshot-btn-active-state { + snapshot_n: snapshot-n-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -362,7 +361,7 @@ qcom,drive-strength = ; }; - audio_mclk_pin: audio-mclk-pin-active-state { + div_clk1: div-clk1-state { pins = "gpio13"; function = "func2"; power-source = <0>; @@ -385,7 +384,7 @@ "SPMI_I2C_SEL", "NC"; - cam_vio_default: cam-vio-active-state { + main_cam_pwr_io_en: main-cam-pwr-io-en-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -395,7 +394,7 @@ power-source = <1>; }; - vib_default: vib-en-state { + vib_ldo_en: vib-ldo-en-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -790,7 +789,7 @@ "RFFE1_DATA", "RFFE1_CLK"; - mdp_vsync_n: mdp-vsync-n-state { + mdp_vsync_p: mdp-vsync-p-state { pins = "gpio10"; function = "mdp_vsync_a"; drive-strength = <2>; @@ -805,14 +804,14 @@ output-low; }; - msm_mclk0_default: msm-mclk0-active-state { + cam_mclk0_active: cam-mclk0-active-state { pins = "gpio13"; function = "cam_mclk"; drive-strength = <2>; bias-disable; }; - msm_mclk1_default: msm-mclk1-active-state { + cam_mclk1_active: cam-mclk1-active-state { pins = "gpio14"; function = "cam_mclk"; drive-strength = <2>; @@ -833,14 +832,14 @@ drive-strength = <2>; }; - cam0_vdig_default: cam0-vdig-default-state { + main_cam_pwr_en: main-cam-pwr-en-default-state { pins = "gpio21"; function = "gpio"; bias-disable; drive-strength = <2>; }; - tof_int: tof-int-state { + tof_int_n: tof-int-n-state { pins = "gpio22"; function = "gpio"; bias-pull-up; @@ -848,28 +847,28 @@ input-enable; }; - cam1_vdig_default: cam1-vdig-default-state { + chat_cam_pwr_en: chat-cam-pwr-en-default-state { pins = "gpio25"; function = "gpio"; bias-disable; drive-strength = <2>; }; - usb_extcon_active: usb-extcon-active-state { - pins = "gpio38"; + tof_reset: tof-reset-state { + pins = "gpio27"; function = "gpio"; bias-disable; - drive-strength = <16>; + drive-strength = <2>; }; - tof_reset: tof-reset-state { - pins = "gpio27"; + cc_dir_default: cc-dir-active-state { + pins = "gpio38"; function = "gpio"; bias-disable; - drive-strength = <2>; + drive-strength = <16>; }; - hall_sensor0_default: acc-cover-open-state { + acc_cover_open: acc-cover-open-state { pins = "gpio124"; function = "gpio"; bias-disable; @@ -884,7 +883,7 @@ bias-pull-up; }; - usb_vbus_active: usb-vbus-active-state { + usb_detect_en: usb-detect-en-active-state { pins = "gpio128"; function = "gpio"; bias-disable; -- cgit v1.2.3 From fc7c39d61cf8cd03e197ac492241fa5a007dd2c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:52:09 +0100 Subject: arm64: dts: qcom: sm6115: Add GPUCC and Adreno SMMU Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU itself. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315-topic-kamorta_adrsmmu-v1-2-d1c0dea90bd9@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 2a51c938bbcb..2505c815c65a 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1111,6 +1112,43 @@ }; }; + gpucc: clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@59a0000 { + compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + power-domains = <&gpucc GPU_CX_GDSC>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,sm6115-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; -- cgit v1.2.3 From bad26511c4cb5469545834886e8df1d2b4c117d8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:22 +0100 Subject: arm64: dts: qcom: sc7280: Use the correct BWMON fallback compatible Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-4-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5e6f9f441f1a..0cdb16316021 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3540,7 +3540,7 @@ }; pmu@90b6400 { - compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; -- cgit v1.2.3 From 5e1b11c00ffc0a2d105af5a92053fa10ca15fcd0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:23 +0100 Subject: arm64: dts: qcom: sc8280xp: Use the correct BWMON fallback compatible Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-5-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index af7bee14fa06..cc7be432ec3c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2953,7 +2953,7 @@ }; pmu@90b6400 { - compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; -- cgit v1.2.3 From e95b60f1207dee16e0d3d66254ece655fd4e73c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:24 +0100 Subject: arm64: dts: qcom: sdm845: Use the correct BWMON compatible Drop the incorrect msm8998 fallback and use the new qcom,sdm845-cpu-bwmon compatible to distinguish the CPU BWMON found on this platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-6-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f32179c7d1b..589b3470c3e1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2252,7 +2252,7 @@ }; pmu@1436400 { - compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x01436400 0 0x600>; interrupts = ; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; -- cgit v1.2.3 From feffd767971e25f43ba47bf2ab23a660f3a3758c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:25 +0100 Subject: arm64: dts: qcom: sm8550: Use the correct BWMON fallback compatible Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-7-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ed2554be467f..7a1994bf4086 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3406,7 +3406,7 @@ }; pmu@240b6400 { - compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; -- cgit v1.2.3 From 2cecb9c2419f78e939e6e902895591ce3e3a7cc7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:53 +0100 Subject: arm64: dts: qcom: sm6375: Add RPM sleep stats Add a node for RPM sleep stats to enable sleep monitoring. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-4-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 86d733ca9b4f..a47cd80d0e1c 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -735,6 +735,11 @@ reg = <0 0x045f0000 0 0x7000>; }; + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0 0x04690000 0 0x400>; + }; + sdhc_2: mmc@4784000 { compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x04784000 0 0x1000>; -- cgit v1.2.3 From 528630df2fa6d34eca0268a293fe354c71e48556 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:54 +0100 Subject: arm64: dts: qcom: sm6375: Add IMEM Add a node for the IMEM block on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-5-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index a47cd80d0e1c..46b39fa8d5b8 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1251,6 +1251,20 @@ }; }; + sram@c125000 { + compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; + reg = <0 0x0c125000 0 0x1000>; + ranges = <0 0 0x0c125000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; reg = <0 0x0c600000 0 0x100000>; -- cgit v1.2.3 From 149d179d1408bc67b6af10af160ac13b48fa3399 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:56 +0100 Subject: arm64: dts: qcom: sm6375: Add wifi node Add a node for ATH10K_SNoC wifi on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-7-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 46b39fa8d5b8..37f4b726959a 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1341,6 +1341,28 @@ #iommu-cells = <2>; }; + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x0c800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&pil_wlan_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x80 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ -- cgit v1.2.3 From 31cc61104f6894f686491dbbb5c8ece97b06e75d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:57 +0100 Subject: arm64: dts: qcom: sm6375: Add modem nodes Add required nodes to make the embedded 5G modem boot up on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-8-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 82 ++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 37f4b726959a..b768b767604f 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -572,6 +572,47 @@ }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -1177,6 +1218,47 @@ }; }; + remoteproc_mss: remoteproc@6000000 { + compatible = "qcom,sm6375-mpss-pas"; + reg = <0 0x06000000 0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6375_VDDCX>; + power-domain-names = "cx"; + + memory-region = <&pil_mpss_wlan_mem>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + remoteproc_adsp: remoteproc@a400000 { compatible = "qcom,sm6375-adsp-pas"; reg = <0 0x0a400000 0 0x100>; -- cgit v1.2.3 From 2f51d9231485250c0e4cf4d7326c30109c553382 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:58 +0100 Subject: arm64: dts: qcom: sm6375: Add CPUCP L3 node Configure the L3 cache DVFS scaler within the CPUCP block to allow for dynamic frequency switching. Reviewed-by: Sibi Sankar Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index b768b767604f..a5dde682ede0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1513,6 +1513,15 @@ }; }; + cpucp_l3: interconnect@fd90000 { + compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; + reg = <0 0x0fd90000 0 0x1000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; -- cgit v1.2.3 From 3f54391526b407a419d2dfd4055fdc9e6e223551 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:59 +0100 Subject: arm64: dts: qcom: sm6375: Add TSENS Add nodes for the two TSENS v2.8.0 controllers present on the SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-10-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index a5dde682ede0..bf95608e1116 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -771,6 +771,28 @@ #interrupt-cells = <4>; }; + tsens0: thermal-sensor@4411000 { + compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; + reg = <0 0x04411000 0 0x140>, /* TM */ + <0 0x04410000 0 0x20>; /* SROT */ + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <15>; + }; + + tsens1: thermal-sensor@4413000 { + compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; + reg = <0 0x04413000 0 0x140>, /* TM */ + <0 0x04412000 0 0x20>; /* SROT */ + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <11>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0 0x045f0000 0 0x7000>; -- cgit v1.2.3 From 33555cdae863984c7840ba742cfffe839a0f71e4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:00 +0100 Subject: arm64: dts: qcom: sm6375: Configure TSENS thermal zones Add a thermal zones configuration for all 15+11 TSENS sensors. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-11-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 704 +++++++++++++++++++++++++++++++++++ 1 file changed, 704 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index bf95608e1116..036e36ceebb5 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1559,6 +1559,710 @@ }; }; + thermal-zones { + mapss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + mapss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss0_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + cluster0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + cluster1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-unk0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu_unk0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-unk1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu_unk1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 13>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 14>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mapss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 0>; + + trips { + mapss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss1_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cwlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 1>; + + trips { + cwlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cwlan_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cwlan_crit: cwlan-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + audio-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 2>; + + trips { + audio_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + audio_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + audio_crit: audio-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 3>; + + trips { + ddr_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + ddr_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + ddr_crit: ddr-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + q6hvx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6hvx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + q6hvx_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + q6hvx_crit: q6hvx-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-core0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 6>; + + trips { + mdm_core0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core0_crit: mdm-core0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-core1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 7>; + + trips { + mdm_core1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core1_crit: mdm-core1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-vec-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 8>; + + trips { + mdm_vec_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_vec_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_vec_crit: mdm-vec-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + msm-scl-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 9>; + + trips { + msm_scl_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + msm_scl_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + msm_scl_crit: msm-scl-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 10>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- cgit v1.2.3 From 097d6525af378f4be768c05cc1d77183a4e742e3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:01 +0100 Subject: arm64: dts: qcom: sm6375: Bump CPU rail power collapse index In preparation for supporting a less-deep sleep state, rename the existing rail power off from _0 to _1. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-12-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 036e36ceebb5..6b75d8611077 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -214,7 +214,7 @@ idle-states { entry-method = "psci"; - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -224,7 +224,7 @@ local-timer-stop; }; - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -275,49 +275,49 @@ CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&BIG_CPU_SLEEP_1>; }; CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&BIG_CPU_SLEEP_1>; }; CLUSTER_PD: power-domain-cpu-cluster0 { -- cgit v1.2.3 From dbe38b9cba6d0de56ca186151f3f54f9c776f9d9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:02 +0100 Subject: arm64: dts: qcom: sm6375: Introduce C3 power state for both ARM clusters Introduce the C3 power state, which - to the best of my understanding - gates the CPU clock, but does not shut off the power rail. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-13-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 6b75d8611077..f66f7ec66387 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -214,6 +214,16 @@ idle-states { entry-method = "psci"; + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; @@ -224,6 +234,16 @@ local-timer-stop; }; + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; @@ -275,49 +295,49 @@ CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_1>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; }; CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_1>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; }; CLUSTER_PD: power-domain-cpu-cluster0 { -- cgit v1.2.3 From 795ee50e55f4e869ad1d56f0262d0baa401f6c3d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:03 +0100 Subject: arm64: dts: qcom: sm6375-pdx225: Add volume down GPIO key Add the required nodes to enable the volume down key on the Sony Xperia 10 IV. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-14-708b8191f7eb@linaro.org --- .../dts/qcom/sm6375-sony-xperia-murray-pdx225.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index b691c3834b6b..8220e6f44117 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -46,6 +46,23 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&vol_down_n>; + pinctrl-names = "default"; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + reserved-memory { cont_splash_mem: memory@85200000 { reg = <0 0x85200000 0 0xc00000>; @@ -133,6 +150,16 @@ status = "okay"; }; +&pmr735a_gpios { + vol_down_n: vol-down-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + &pon_pwrkey { status = "okay"; }; -- cgit v1.2.3 From dffc4b5c086cf1d3dae4761427122a56b9d1253a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:08 +0100 Subject: arm64: dts: qcom: sm8250: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8250-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Ulf Hansson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7b78761f2041..69becde511c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -362,12 +362,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-llcc-off"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3264>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; -- cgit v1.2.3 From 1766e9155d086cd238c24113a7be9740d35c2ebe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:09 +0100 Subject: arm64: dts: qcom: sdm845: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sdm845-shift-axolotl.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 589b3470c3e1..47cd1ff46a91 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -339,12 +339,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; -- cgit v1.2.3 From ac7944f01b771af7718a81793ca5b38b0e3a0c21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:10 +0100 Subject: arm64: dts: qcom: sm6375: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm6375-sony-xperia-murray-pdx225.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index f66f7ec66387..ae9b6bc446cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -258,12 +258,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <2752>; exit-latency-us = <3048>; min-residency-us = <6118>; - local-timer-stop; }; }; }; -- cgit v1.2.3 From 770f85c19536fde3591f4f2f70ac32f33d86b975 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:11 +0100 Subject: arm64: dts: qcom: sm8150: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8150-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 9491be4a6bf0..c9c04ac9bfcd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -295,12 +295,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; -- cgit v1.2.3 From 7983224c6a6cea77aa0b9b4e23bb7651241df961 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:12 +0100 Subject: arm64: dts: qcom: sm8350: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8350-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7fbc288eca58..8985a59602f9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -257,12 +257,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; -- cgit v1.2.3 From ea1811e2614cd66608961ae3c5a9ee6038fc424b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:13 +0100 Subject: arm64: dts: qcom: sc8280xp: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name': sc8280xp-crd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index cc7be432ec3c..451cd85cbac8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -276,7 +276,6 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; exit-latency-us = <6562>; -- cgit v1.2.3 From 35fa9a7fc577a4d1ed541ff37d9dda83b0635e4b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:28:47 +0100 Subject: arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes Fixes the following DT bindings check error: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 31877f18dce2..c59a922ce9f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -256,22 +256,18 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <1050>; exit-latency-us = <2500>; min-residency-us = <5309>; - local-timer-stop; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <2700>; exit-latency-us = <3500>; min-residency-us = <13959>; - local-timer-stop; }; }; }; -- cgit v1.2.3 From 3042fb4b61c8a6ce692a4914b1970daa56e6f04e Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:49 +0100 Subject: arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Assign RPM_SMD_XO_CLK_SRC from rpmcc in place of fixed-clock where possible. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-1-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index da00c2f04cda..438a70eb6152 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ #include +#include #include #include #include @@ -637,7 +638,7 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&xo_board>, + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, <0>, <0>, @@ -801,7 +802,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; @@ -868,7 +869,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; @@ -992,7 +993,7 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; power-domains = <&rpmpd MSM8953_VDDCX>; @@ -1052,7 +1053,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; power-domains = <&rpmpd MSM8953_VDDCX>; -- cgit v1.2.3 From 635abd877516f6d5e35343d3c3eb233ab195ebc5 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:50 +0100 Subject: arm64: dts: msm8953: Provide dsi_phy clocks to gcc Provide clocks from dsi_phy to gcc, this will make sure we don't fallback to global name lookup. Signed-off-by: Adam Skladowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-2-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 438a70eb6152..5dd10c35ee0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -640,10 +640,10 @@ #power-domain-cells = <1>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>; + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; clock-names = "xo", "sleep", "dsi0pll", -- cgit v1.2.3 From c0494df2cdac723f4c7df834c05d548ea3a804e9 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:51 +0100 Subject: arm64: dts: msm8953: Drop unsupported dwc3 flag Property phy_mode according to binding checker does not exist, drop it. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-3-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 5dd10c35ee0d..0a1bf1058cbf 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -977,7 +977,6 @@ snps,hird-threshold = /bits/ 8 <0x00>; maximum-speed = "high-speed"; - phy_mode = "utmi"; }; }; -- cgit v1.2.3 From 26aae2310fd7375a5ca0dd772cd3bc57cf5e02bb Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:52 +0100 Subject: arm64: dts: msm8953: Pad regs to 8 digits Follow other dtses and pad regs to 8 digits. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-4-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 98 +++++++++++++++++------------------ 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 0a1bf1058cbf..684668170353 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -350,12 +350,12 @@ rpm_msg_ram: sram@60000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x60000 0x8000>; + reg = <0x00060000 0x8000>; }; hsusb_phy: phy@79000 { compatible = "qcom,msm8953-qusb2-phy"; - reg = <0x79000 0x180>; + reg = <0x00079000 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, @@ -378,8 +378,8 @@ tsens0: thermal-sensor@4a9000 { compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; - reg = <0x4a9000 0x1000>, /* TM */ - <0x4a8000 0x1000>; /* SROT */ + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; @@ -389,12 +389,12 @@ restart@4ab000 { compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; + reg = <0x004ab000 0x4>; }; tlmm: pinctrl@1000000 { compatible = "qcom,msm8953-pinctrl"; - reg = <0x1000000 0x300000>; + reg = <0x01000000 0x300000>; interrupts = ; gpio-controller; gpio-ranges = <&tlmm 0 0 142>; @@ -634,7 +634,7 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-msm8953"; - reg = <0x1800000 0x80000>; + reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -654,25 +654,25 @@ tcsr_mutex: hwlock@1905000 { compatible = "qcom,tcsr-mutex"; - reg = <0x1905000 0x20000>; + reg = <0x01905000 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1937000 { compatible = "qcom,tcsr-msm8953", "syscon"; - reg = <0x1937000 0x30000>; + reg = <0x01937000 0x30000>; }; tcsr_phy_clk_scheme_sel: syscon@193f044 { compatible = "qcom,tcsr-msm8953", "syscon"; - reg = <0x193f044 0x4>; + reg = <0x0193f044 0x4>; }; mdss: display-subsystem@1a00000 { compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ab0000 0x1040>; + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x1040>; reg-names = "mdss_phys", "vbif_phys"; @@ -699,7 +699,7 @@ mdp: display-controller@1a01000 { compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; - reg = <0x1a01000 0x89000>; + reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; interrupt-parent = <&mdss>; @@ -740,7 +740,7 @@ dsi0: dsi@1a94000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x1a94000 0x400>; + reg = <0x01a94000 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -792,9 +792,9 @@ dsi0_phy: phy@1a94400 { compatible = "qcom,dsi-phy-14nm-8953"; - reg = <0x1a94400 0x100>, - <0x1a94500 0x300>, - <0x1a94800 0x188>; + reg = <0x01a94400 0x100>, + <0x01a94500 0x300>, + <0x01a94800 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -810,7 +810,7 @@ dsi1: dsi@1a96000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x1a96000 0x400>; + reg = <0x01a96000 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -859,9 +859,9 @@ dsi1_phy: phy@1a96400 { compatible = "qcom,dsi-phy-14nm-8953"; - reg = <0x1a96400 0x100>, - <0x1a96500 0x300>, - <0x1a96800 0x188>; + reg = <0x01a96400 0x100>, + <0x01a96500 0x300>, + <0x01a96800 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -878,7 +878,7 @@ apps_iommu: iommu@1e00000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1e20000 0x20000>; + ranges = <0 0x01e20000 0x20000>; clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_APSS_TCU_ASYNC_CLK>; @@ -914,11 +914,11 @@ spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f000 0x1000>, - <0x2400000 0x800000>, - <0x2c00000 0x800000>, - <0x3800000 0x200000>, - <0x200a000 0x2100>; + reg = <0x0200f000 0x1000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -933,7 +933,7 @@ usb3: usb@70f8800 { compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; - reg = <0x70f8800 0x400>; + reg = <0x070f8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -983,7 +983,7 @@ sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; + reg = <0x07824900 0x500>, <0x07824000 0x800>; reg-names = "hc", "core"; interrupts = , @@ -1043,7 +1043,7 @@ sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg = <0x07864900 0x500>, <0x07864000 0x800>; reg-names = "hc", "core"; interrupts = , @@ -1098,7 +1098,7 @@ uart_0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; + reg = <0x078af000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -1109,7 +1109,7 @@ i2c_1: i2c@78b5000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b5000 0x600>; + reg = <0x078b5000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, @@ -1127,7 +1127,7 @@ i2c_2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b6000 0x600>; + reg = <0x078b6000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, @@ -1145,7 +1145,7 @@ i2c_3: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x600>; + reg = <0x078b7000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, @@ -1162,7 +1162,7 @@ i2c_4: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b8000 0x600>; + reg = <0x078b8000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, @@ -1179,7 +1179,7 @@ i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af5000 0x600>; + reg = <0x07af5000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, @@ -1196,7 +1196,7 @@ i2c_6: i2c@7af6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af6000 0x600>; + reg = <0x07af6000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, @@ -1213,7 +1213,7 @@ i2c_7: i2c@7af7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af7000 0x600>; + reg = <0x07af7000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, @@ -1230,7 +1230,7 @@ i2c_8: i2c@7af8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af8000 0x600>; + reg = <0x07af8000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, @@ -1254,13 +1254,13 @@ apcs: mailbox@b011000 { compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; - reg = <0xb011000 0x1000>; + reg = <0x0b011000 0x1000>; #mbox-cells = <1>; }; timer@b120000 { compatible = "arm,armv7-timer-mem"; - reg = <0xb120000 0x1000>; + reg = <0x0b120000 0x1000>; #address-cells = <0x01>; #size-cells = <0x01>; ranges; @@ -1269,49 +1269,49 @@ frame-number = <0>; interrupts = , ; - reg = <0xb121000 0x1000>, - <0xb122000 0x1000>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = ; - reg = <0xb123000 0x1000>; + reg = <0x0b123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = ; - reg = <0xb124000 0x1000>; + reg = <0x0b124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = ; - reg = <0xb125000 0x1000>; + reg = <0x0b125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = ; - reg = <0xb126000 0x1000>; + reg = <0x0b126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = ; - reg = <0xb127000 0x1000>; + reg = <0x0b127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = ; - reg = <0xb128000 0x1000>; + reg = <0x0b128000 0x1000>; status = "disabled"; }; }; -- cgit v1.2.3 From 5dcc6587fde26fa03fe6993278d9bd01daed09b1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:18 +0200 Subject: arm64: dts: qcom: sdm845-tama: Add display nodes Add required nodes to support display on XZ2/XZ2c. XZ3 has a different power rail setup and needs to be handled separately. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-1-2b1567c039d7@linaro.org --- .../dts/qcom/sdm845-sony-xperia-tama-akari.dts | 4 + .../dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts | 44 +++++++++- .../dts/qcom/sdm845-sony-xperia-tama-apollo.dts | 6 ++ .../boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 93 ++++++++++++++++++++++ 4 files changed, 146 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts index 34f84f1f1eb4..d97b7f1e7140 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts @@ -11,3 +11,7 @@ model = "Sony Xperia XZ2"; compatible = "sony,akari-row", "qcom,sdm845"; }; + +&panel { + compatible = "sony,td4353-jdi-tama"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts index 2f5e12deaada..81cbf535cb76 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -10,9 +10,51 @@ / { model = "Sony Xperia XZ3"; compatible = "sony,akatsuki-row", "qcom,sdm845"; + + /* Fixed DCDC for the OLED panel */ + ts_vddio_supply: ts-vddio-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_vddio"; + + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <1840000>; + + gpio = <&tlmm 133 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ibb { + status = "disabled"; +}; + +&lab { + status = "disabled"; +}; + +&panel { + /* Akatsuki uses an OLED panel. */ + /delete-property/ backlight; + /delete-property/ vsp-supply; + /delete-property/ vsn-supply; + /delete-property/ touch-reset-gpios; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&tlmm { + ts_vddio_en: ts-vddio-en-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; }; -/* For the future: WLED + LAB/IBB/OLEDB are not used on Akatsuki */ &vreg_l14a_1p8 { regulator-min-microvolt = <1840000>; regulator-max-microvolt = <1840000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts index c9e62c72f60e..cd056f78070f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts @@ -11,3 +11,9 @@ model = "Sony Xperia XZ2 Compact"; compatible = "sony,apollo-row", "qcom,sdm845"; }; + +&panel { + compatible = "sony,td4353-jdi-tama"; + height-mm = <112>; + width-mm = <56>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 4984c7496c31..3c7d129d9d8e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -356,6 +356,43 @@ }; }; +&dsi0 { + vdda-supply = <&vreg_l26a_1p2>; + status = "okay"; + + panel: panel@0 { + /* The compatible is assigned in device DTs. */ + reg = <0>; + + backlight = <&pmi8998_wled>; + vddio-supply = <&vreg_l14a_1p8>; + vsp-supply = <&lab>; + vsn-supply = <&ibb>; + panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + vdds-supply = <&vreg_l1a_0p9>; + status = "okay"; +}; + &gcc { protected-clocks = , , @@ -388,6 +425,31 @@ /* AMS TCS3490 RGB+IR color sensor @ 72 */ }; +&ibb { + qcom,discharge-resistor-kohms = <300>; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5700000>; + regulator-min-microamp = <0>; + regulator-max-microamp = <800000>; + regulator-over-current-protection; + regulator-soft-start; + regulator-pull-down; +}; + +&lab { + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5700000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-over-current-protection; + regulator-soft-start; + regulator-pull-down; +}; + +&mdss { + status = "okay"; +}; + &pm8998_gpios { focus_n: focus-n-state { pins = "gpio2"; @@ -422,6 +484,16 @@ }; }; +&pmi8998_wled { + default-brightness = <800>; + qcom,switching-freq = <800>; + qcom,ovp-millivolt = <29600>; + qcom,current-boost-limit = <970>; + qcom,current-limit-microamp = <20000>; + qcom,enabled-strings = <0 1 2 3>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -465,6 +537,27 @@ bias-pull-up; }; }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_sleep: sde-dsi-sleep-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active_sleep: sde-te-active-sleep-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart6 { -- cgit v1.2.3 From 3ab8216de2fab6a6efeb5b22d8d61676b67964dc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:19 +0200 Subject: arm64: dts: qcom: sdm845-tama: Add Synaptics Touchscreen Add required pins and RMI4 node to the common DT and remove it from Akatsuki, as it uses a different touch. Since the panels are super high tech proprietary incell, they need to be handled with very precise timings. As such the panel driver sets up the power rails and GPIOs and the touchscreen driver *has to* probe afterwards. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-2-2b1567c039d7@linaro.org --- .../dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts | 3 + .../boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 68 +++++++++++++++++++++- 2 files changed, 69 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts index 81cbf535cb76..5d2052a0ff69 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -7,6 +7,9 @@ #include "sdm845-sony-xperia-tama.dtsi" +/* XZ3 uses an Atmel touchscreen instead. */ +/delete-node/ &touchscreen; + / { model = "Sony Xperia XZ3"; compatible = "sony,akatsuki-row", "qcom,sdm845"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 3c7d129d9d8e..8172d0c9c1a3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -402,10 +402,42 @@ }; &i2c5 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; + + touchscreen: touchscreen@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vreg_l14a_1p8>; + /* + * This is a blatant abuse of OF, but the panel driver *needs* + * to probe first, as the power/gpio switching needs to be precisely + * timed in order for both the display and touch panel to function properly. + */ + incell-supply = <&panel>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <1000>; + + pinctrl-0 = <&ts_default>; + pinctrl-1 = <&ts_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; - /* Synaptics touchscreen @ 2c, 3c */ + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; }; &i2c10 { @@ -558,6 +590,38 @@ drive-strength = <2>; bias-pull-down; }; + + ts_default: ts-default-state { + reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + int-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ts_sleep: ts-sleep-state { + reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + int-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; &uart6 { -- cgit v1.2.3 From 1d99fee382a6ada0cd05ae8afaea2dd1884c58a3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:20 +0200 Subject: arm64: dts: qcom: sdm845-tama: Add regulator-system-load to l14a/l28a Add the properties to ensure the ever so delicate touchscreen setup matches downstream. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-3-2b1567c039d7@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 8172d0c9c1a3..208ed466081d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -228,6 +228,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-system-load = <62000>; }; vreg_l15a_1p8: ldo15 { @@ -314,6 +315,7 @@ regulator-min-microvolt = <2856000>; regulator-max-microvolt = <3008000>; regulator-initial-mode = ; + regulator-system-load = <100000>; }; vreg_lvs1a_1p8: lvs1 { -- cgit v1.2.3 From 39e0f8076f6fc5022902c62f5046ad91cf2b7a59 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:21 +0200 Subject: arm64: dts: qcom: sdm845-tama: Enable remoteprocs Enable ADSP, CDSP and Venus. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-4-2b1567c039d7@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 208ed466081d..48916a3216e5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -98,6 +98,11 @@ }; }; +&adsp_pas { + firmware-name = "qcom/sdm845/Sony/tama/adsp.mbn"; + status = "okay"; +}; + &apps_rsc { regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; @@ -358,6 +363,11 @@ }; }; +&cdsp_pas { + firmware-name = "qcom/sdm845/Sony/tama/cdsp.mbn"; + status = "okay"; +}; + &dsi0 { vdda-supply = <&vreg_l26a_1p2>; status = "okay"; @@ -659,3 +669,8 @@ vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p1>; }; + +&venus { + firmware-name = "qcom/sdm845/Sony/tama/venus.mbn"; + status = "okay"; +}; -- cgit v1.2.3 From ff9108ea69adc0b38e5bbc8575434355f0e20579 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:22 +0200 Subject: arm64: dts: qcom: sdm845-tama: Enable GPU Enable the A630 GPU and its GMU. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-5-2b1567c039d7@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 48916a3216e5..df8dd6e45a38 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -413,6 +413,19 @@ ; }; +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; + }; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; -- cgit v1.2.3 From da51e2ceedc2df7248bad6bec45ae3280de9ada2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:23 +0200 Subject: arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1 Enable both GPI DMAs. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-6-2b1567c039d7@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index df8dd6e45a38..420ffede3e80 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -417,6 +417,14 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; -- cgit v1.2.3 From 894e258b6a38922f9860a20ca07cf2f745e3b090 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 3 Apr 2023 15:23:28 +0200 Subject: arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name The bindings expect second Soundwire interrupt to be "wakeup" (Linux driver takes by index): sc8280xp-crd.dtb: soundwire-controller@3330000: interrupt-names:1: 'wakeup' was expected Fixes: c18773d162a6 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403132328.61414-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 451cd85cbac8..a33df7a1adea 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2605,7 +2605,7 @@ reg = <0 0x03330000 0 0x2000>; interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "core", "wake"; + interrupt-names = "core", "wakeup"; clocks = <&txmacro>; clock-names = "iface"; -- cgit v1.2.3 From 3fd7e2eec8f4fedbe3b252cf436be8527f7a5f82 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:52:59 +0200 Subject: arm64: dts: qcom: sa8775p: pad reg properties to 8 digits The file has inconsistent padding of the address part of soc node children's reg properties. Fix it. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index c5b73c591e0f..5aa28a3b12ae 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -440,7 +440,7 @@ gcc: clock-controller@100000 { compatible = "qcom,sa8775p-gcc"; - reg = <0x0 0x100000 0x0 0xc7018>; + reg = <0x0 0x00100000 0x0 0xc7018>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -464,7 +464,7 @@ ipcc: mailbox@408000 { compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; - reg = <0x0 0x408000 0x0 0x1000>; + reg = <0x0 0x00408000 0x0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; @@ -473,7 +473,7 @@ qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0xac0000 0x0 0x6000>; + reg = <0x0 0x00ac0000 0x0 0x6000>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -485,7 +485,7 @@ uart10: serial@a8c000 { compatible = "qcom,geni-uart"; - reg = <0x0 0xa8c000 0x0 0x4000>; + reg = <0x0 0x00a8c000 0x0 0x4000>; interrupts = ; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; @@ -735,7 +735,7 @@ tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x1f40000 0x0 0x20000>; + reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; @@ -754,7 +754,7 @@ tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; - reg = <0x0 0xf000000 0x0 0x1000000>; + reg = <0x0 0x0f000000 0x0 0x1000000>; interrupts = ; gpio-controller; #gpio-cells = <2>; -- cgit v1.2.3 From f95f988cf7b609157630dd1f2f7e8d297aadbe2b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:00 +0200 Subject: arm64: dts: qcom: sa8775p: sort soc nodes by reg property Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 394 +++++++++++++++++----------------- 1 file changed, 197 insertions(+), 197 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 5aa28a3b12ae..296ba69b81ab 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -471,50 +471,6 @@ #mbox-cells = <2>; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x443 0x0>; - status = "disabled"; - - uart10: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a8c000 0x0 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 - &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_1 0>; - power-domains = <&rpmhpd SA8775P_CX>; - operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - - uart12: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - power-domains = <&rpmhpd SA8775P_CX>; - status = "disabled"; - }; - }; - qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -585,173 +541,56 @@ }; }; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - }; - - memtimer: timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <1>; - #size-cells = <1>; - - frame@17c21000 { - reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; - interrupts = , - ; - frame-number = <0>; - }; - - frame@17c23000 { - reg = <0x17c23000 0x1000>; - interrupts = ; - frame-number = <1>; - status = "disabled"; - }; - - frame@17c25000 { - reg = <0x17c25000 0x1000>; - interrupts = ; - frame-number = <2>; - status = "disabled"; - }; - - frame@17c27000 { - reg = <0x17c27000 0x1000>; - interrupts = ; - frame-number = <3>; - status = "disabled"; - }; - - frame@17c29000 { - reg = <0x17c29000 0x1000>; - interrupts = ; - frame-number = <4>; - status = "disabled"; - }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; - frame@17c2b000 { - reg = <0x17c2b000 0x1000>; - interrupts = ; - frame-number = <5>; + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; - frame@17c2d000 { - reg = <0x17c2d000 0x1000>; - interrupts = ; - frame-number = <6>; + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; }; - apps_rsc: rsc@18200000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - label = "apps_rsc"; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sa8775p-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board_clk>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sa8775p-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-0 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp-1 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp-4 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp-5 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp-6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp-7 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp-8 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp-9 { - opp-level = ; - }; - }; - }; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sa8775p-cpufreq-epss", - "qcom,cpufreq-epss"; - reg = <0x0 0x18591000 0x0 0x1000>, - <0x0 0x18593000 0x0 0x1000>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; @@ -900,6 +739,167 @@ , ; }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; arch_timer: timer { -- cgit v1.2.3 From 8696cd072e955bd6f5df757774e47f0b9dd29920 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:02 +0200 Subject: arm64: dts: qcom: sa8775p: add the pdc node Add the Power Domain Controller node for SA8775p. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-5-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 +++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 296ba69b81ab..6bb1db1839cc 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,53 @@ #hwlock-cells = <1>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sa8775p-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; -- cgit v1.2.3 From fdd55b3babedce5abd1c1f90afc3ab2199a772ad Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:03 +0200 Subject: arm64: dts: qcom: sa8775p: add the spmi node Add the SPMI PMIC Arbiter node for SA8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-6-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 6bb1db1839cc..2343df7e0ea4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -638,6 +638,28 @@ interrupt-controller; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + qcom,channel = <0>; + qcom,ee = <0>; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; -- cgit v1.2.3 From 634a3de323fc5c67c144919e298259d8d9d44a4b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:05 +0200 Subject: arm64: dts: qcom: sa8775p: add support for the on-board PMICs Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced to the SoC via SPMI. Enable the PMICs for sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 37 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 1 + 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi new file mode 100644 index 000000000000..afe220b374c2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include + +&spmi_bus { + pmm8654au_0: pmic@0 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_1: pmic@2 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_2: pmic@4 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_3: pmic@6 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 1020dfd21da2..b7ee4cc676b5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" / { model = "Qualcomm SA8775P Ride"; -- cgit v1.2.3 From d2d9a592746cd454bd5b8f72193f2d3db2e62a44 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:06 +0200 Subject: arm64: dts: qcom: sa8775p: add the Power On device node Add the PON node to PMIC #0 for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-9-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index afe220b374c2..dbc596e32253 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -12,6 +12,14 @@ reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_0_pon: pon@1200 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1200>, <0x800>; + reg-names = "hlos", "pbs"; + mode-recovery = <0x1>; + mode-bootloader = <0x2>; + }; }; pmm8654au_1: pmic@2 { -- cgit v1.2.3 From b3a755ba16e6f61d93c811b827edacc9946b0500 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:07 +0200 Subject: arm64: dts: qcom: sa8775p: pmic: add the power key Add the power key node under the PON node for PMIC #0 on sa8775p. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-10-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index dbc596e32253..f421d4d64c8e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -19,6 +19,13 @@ reg-names = "hlos", "pbs"; mode-recovery = <0x1>; mode-bootloader = <0x2>; + + pmm8654au_0_pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts-extended = <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + debounce = <15625>; + }; }; }; -- cgit v1.2.3 From cecff1f5429d975df9649376e2bd5a2fb004f988 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:08 +0200 Subject: arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input Add the RESIN input for sa8775p platforms' PMIC. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-11-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index f421d4d64c8e..8616ead3daf5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -26,6 +26,13 @@ linux,code = ; debounce = <15625>; }; + + pmm8654au_0_pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts-extended = <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From fa40ca07e943333a14d247988ef5008a59949153 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:09 +0200 Subject: arm64: dts: qcom: sa8775p: pmic: add thermal zones Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-12-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 112 ++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index 8616ead3daf5..be12997a080c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -6,6 +6,90 @@ #include #include +/ { + thermal-zones { + pmm8654au_0_thermal: pm8775-0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_0_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8775-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_1_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8775-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_2_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8775-3-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_3_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmm8654au_0: pmic@0 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; @@ -13,6 +97,13 @@ #address-cells = <1>; #size-cells = <0>; + pmm8654au_0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmm8654au_0_pon: pon@1200 { compatible = "qcom,pmk8350-pon"; reg = <0x1200>, <0x800>; @@ -41,6 +132,13 @@ reg = <0x2 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_2: pmic@4 { @@ -48,6 +146,13 @@ reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_3: pmic@6 { @@ -55,5 +160,12 @@ reg = <0x6 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_3_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; }; -- cgit v1.2.3 From e5a893a7cec5776e10c25d7fa80b5ad1edf88c17 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:12 +0200 Subject: arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-15-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 40 +++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index be12997a080c..7602cca47bae 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -125,6 +125,16 @@ status = "disabled"; }; }; + + pmm8654au_0_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_0_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_1: pmic@2 { @@ -139,6 +149,16 @@ interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_1_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_2: pmic@4 { @@ -153,6 +173,16 @@ interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_2_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_3: pmic@6 { @@ -167,5 +197,15 @@ interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_3_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_3_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; }; -- cgit v1.2.3 From 81767c1591dcb711f1f78a80e510b667b1fb5718 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:13 +0200 Subject: arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs Set line names for GPIO lines exposed by PMICs on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 51 +++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index b7ee4cc676b5..a0d2024a69df 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -32,6 +32,57 @@ status = "okay"; }; +&pmm8654au_0_gpios { + gpio-line-names = "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_1_gpios { + gpio-line-names = "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; +}; + +&pmm8654au_2_gpios { + gpio-line-names = "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; +}; + +&pmm8654au_3_gpios { + gpio-line-names = "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + &qupv3_id_1 { status = "okay"; }; -- cgit v1.2.3 From b8e0ed06d1a569694c8976c3563bbd0aae728e1d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 16 Mar 2023 13:41:14 +0530 Subject: arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316081117.14288-17-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 47cd1ff46a91..da4b200281d8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2291,8 +2291,9 @@ reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c07000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; @@ -2396,8 +2397,9 @@ reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; + <0 0x40100000 0 0x100000>, + <0 0x01c0c000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; -- cgit v1.2.3 From 89210342406b91954c514d171baeabb91f85f0a5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 16 Mar 2023 13:41:15 +0530 Subject: arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 69becde511c4..4e7875f8786f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1829,8 +1829,9 @@ <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; @@ -1938,8 +1939,9 @@ <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x40100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; @@ -2046,8 +2048,9 @@ <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>, <0 0x64001000 0 0x1000>, - <0 0x64100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x64100000 0 0x100000>, + <0 0x01c13000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <2>; bus-range = <0x00 0xff>; -- cgit v1.2.3 From de7d3d2f9ddef9a3305decccdd3b95b09fd2bd46 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 16 Mar 2023 13:41:16 +0530 Subject: arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316081117.14288-19-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a33df7a1adea..2b76be6a5f1c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1660,8 +1660,9 @@ <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, - <0x0 0x30100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x30100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, @@ -1759,8 +1760,9 @@ <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, - <0x0 0x32100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x32100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, @@ -1856,8 +1858,9 @@ <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, - <0x0 0x34100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x34100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, @@ -1956,8 +1959,9 @@ <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, - <0x0 0x38100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x38100000 0x0 0x100000>, + <0x0 0x01c1b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, @@ -2053,8 +2057,9 @@ <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, - <0x0 0x3c100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, -- cgit v1.2.3 From 9db28f297526f17c6575ec0eefc93a8b1642cff7 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 26 Mar 2023 18:38:11 -0500 Subject: arm64: dts: qcom: sc8280xp: Define uart2 Add the definition for uart2 for sc8280xp devices. Signed-off-by: Bjorn Andersson Signed-off-by: Steev Klimaszewski Reviewed-by: Brian Masney Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326233812.28058-4-steev@kali.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 2b76be6a5f1c..4c75da1bac2d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1214,6 +1214,20 @@ status = "disabled"; }; + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + operating-points-v2 = <&qup_opp_table_100mhz>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; -- cgit v1.2.3 From 105560b4fca4df0d42dba6656105b5e4131d8ad3 Mon Sep 17 00:00:00 2001 From: Steev Klimaszewski Date: Sun, 26 Mar 2023 18:38:12 -0500 Subject: arm64: dts: qcom: sc8280xp-x13s: Add bluetooth The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2, add this. Signed-off-by: Steev Klimaszewski Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326233812.28058-5-steev@kali.org --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 4884e22ccca1..a1db3cf80c47 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -24,6 +24,7 @@ aliases { i2c4 = &i2c4; i2c21 = &i2c21; + serial1 = &uart2; }; wcd938x: audio-codec { @@ -1067,6 +1068,32 @@ status = "okay"; }; +&uart2 { + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + + vddio-supply = <&vreg_s10b>; + vddbtcxmx-supply = <&vreg_s12b>; + vddrfacmn-supply = <&vreg_s12b>; + vddrfa0p8-supply = <&vreg_s12b>; + vddrfa1p2-supply = <&vreg_s11b>; + vddrfa1p7-supply = <&vreg_s1c>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + &usb_0 { status = "okay"; }; @@ -1187,6 +1214,21 @@ &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + bt_default: bt-default-state { + hstp-bt-en-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hstp-sw-ctrl-pins { + pins = "gpio132"; + function = "gpio"; + bias-pull-down; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio25"; function = "gpio"; @@ -1353,6 +1395,34 @@ }; }; + uart2_default: uart2-default-state { + cts-pins { + pins = "gpio121"; + function = "qup2"; + bias-bus-hold; + }; + + rts-pins { + pins = "gpio122"; + function = "qup2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio124"; + function = "qup2"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio123"; + function = "qup2"; + drive-strength = <2>; + bias-disable; + }; + }; + usb0_sbu_default: usb0-sbu-state { oe-n-pins { pins = "gpio101"; -- cgit v1.2.3