From 0a52d413afc6236cd120286be8cb44714c36bc3c Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:42 +0800 Subject: arm64: dts: apple: s5l8960x: Add CPU caches Add information about CPU caches in Apple A7 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-1-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index d820b0e43050..5b5175d6978c 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -37,6 +37,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -47,6 +50,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; }; }; -- cgit v1.2.3 From 1ed7edcf5caa4332e33c4f43a1a36750ac61a652 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:43 +0800 Subject: arm64: dts: apple: t7000: Add CPU caches Add information about CPU caches in Apple A8 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-2-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t7000.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi index 85a34dc7bc01..52edc8d776a9 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -37,6 +37,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -47,6 +50,16 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; }; }; -- cgit v1.2.3 From 93669da1d1e35cb8d4df7e7f9765721c998521e7 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:44 +0800 Subject: arm64: dts: apple: t7001: Add CPU caches Add information about CPU caches in Apple A8X SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-3-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t7001.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index 8e2c67e19c41..a2efa81305df 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -39,6 +39,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -49,6 +52,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu2: cpu@2 { @@ -59,6 +65,16 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; }; }; -- cgit v1.2.3 From a7a38536f2ea5d3797b9d647d4a8abdaa36ebeb3 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:45 +0800 Subject: arm64: dts: apple: s800-0-3: Add CPU caches Add information about CPU caches in both variants of Apple A9 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-4-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi index c0e9ae45627c..09db4ed64054 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -46,6 +49,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; }; }; -- cgit v1.2.3 From a5a6ce8a7abd48a266c0478b6ca457f7c99692b7 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:46 +0800 Subject: arm64: dts: apple: s8001: Add CPU caches Add information about CPU caches in Apple A9X SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-5-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s8001.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index d56d49c048bb..fee350765894 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -46,6 +49,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; }; }; -- cgit v1.2.3 From a3ffd38110b70a1c8a5b2410d54d04c5275f9bd0 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:47 +0800 Subject: arm64: dts: apple: t8010: Add CPU caches Add information about CPU caches in the P-cluster of Apple A10 SoC. Due to "Apple Fusion Architecture" big.LITTLE switcher, only caches from one of the clusters can be used at any given moment. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-6-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8010.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi index 17e294bd7c44..b961d4f65bc3 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu1: cpu@1 { @@ -46,6 +49,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; /* P-cluster */ }; }; -- cgit v1.2.3 From 66be2180e9626c42a2b95262fb2b240c18e39798 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:48 +0800 Subject: arm64: dts: apple: t8011: Add CPU caches Add information about CPU caches in the P-cluster of Apple A10X SoC. Due to "Apple Fusion Architecture" big.LITTLE switcher, only caches from one of the clusters can be used at any given moment. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-7-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8011.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi index 5b280c896b76..974f78cc77cf 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu1: cpu@1 { @@ -46,6 +49,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu2: cpu@2 { @@ -56,6 +62,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x800000>; /* P-cluster */ }; }; -- cgit v1.2.3 From 0b311f8d69a7bca791055549e19c7edaad494ef7 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:49 +0800 Subject: arm64: dts: apple: t8012: Add CPU caches Add information about CPU caches in the P-cluster of Apple T2 SoC. Due to "Apple Fusion Architecture" big.LITTLE switcher, only caches from one of the clusters can be used at any given moment. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-8-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8012.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi index 42df2f51ad7b..a259e5735d93 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu1: cpu@10001 { @@ -46,6 +49,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; /* P-cluster */ }; }; -- cgit v1.2.3 From 21da4ec75a61480b8a4b0fddac43a59c6a4d71ed Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:50 +0800 Subject: arm64: dts: apple: t8015: Add CPU caches Add information about CPU caches in Apple A11 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-9-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8015.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index 4d54afcecd50..12acf8fc8bc6 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -63,6 +63,9 @@ capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_e1: cpu@1 { @@ -74,6 +77,9 @@ capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_e2: cpu@2 { @@ -85,6 +91,9 @@ capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_e3: cpu@3 { @@ -96,6 +105,9 @@ capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_p0: cpu@10004 { @@ -107,6 +119,9 @@ capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu_p1: cpu@10005 { @@ -118,6 +133,23 @@ capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x800000>; }; }; -- cgit v1.2.3 From 2e0e70c95077172b29a5b13716c4b159d578e82c Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein Date: Wed, 9 Apr 2025 23:52:14 +0200 Subject: arm64: dts: apple: Add SPMI controller nodes Add device tree entries for the SPMI controller Reviewed-by: Nick Chan Signed-off-by: Sasha Finkelstein Reviewed-by: Neal Gompa Link: https://lore.kernel.org/r/20250409-spmi-v4-3-eb81ecfd1f64@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 7 +++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 8 ++++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 7 +++++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index e9b3140ba1a9..4c224e686ffe 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -45,6 +45,13 @@ ; }; + nub_spmi0: spmi@2920a1300 { + compatible = "apple,t6000-spmi", "apple,spmi"; + reg = <0x2 0x920a1300 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + wdt: watchdog@2922b0000 { compatible = "apple,t6000-wdt", "apple,wdt"; reg = <0x2 0x922b0000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 97b6a067394e..bdb1cb9e406a 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "apple,t8103", "apple,arm-platform"; @@ -741,6 +742,13 @@ }; }; + nub_spmi: spmi@23d0d9300 { + compatible = "apple,t8103-spmi", "apple,spmi"; + reg = <0x2 0x3d0d9300 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + pinctrl_nub: pinctrl@23d1f0000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3d1f0000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index d9b966d68e4f..950d1f906ba3 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -782,6 +782,13 @@ interrupts = ; }; + nub_spmi: spmi@23d714000 { + compatible = "apple,t8112-spmi", "apple,spmi"; + reg = <0x2 0x3d714000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8112-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; -- cgit v1.2.3 From d8bf82081c9e5a4f0f239cdd01296377ba490471 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 23 Apr 2025 19:55:15 +0200 Subject: arm64: dts: apple: Add PMIC NVMEM Add device tree entries for NVMEM cells present on the PMIC Signed-off-by: Hector Martin Reviewed-by: Nick Chan Reviewed-by: Alyssa Rosenzweig Co-developed-by: Sasha Finkelstein Signed-off-by: Sasha Finkelstein Reviewed-by: Neal Gompa Link: https://lore.kernel.org/r/20250423-spmi-nvmem-v3-3-2985aa722ddc@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6001.dtsi | 1 + arch/arm64/boot/dts/apple/t6002.dtsi | 1 + arch/arm64/boot/dts/apple/t600x-die0.dtsi | 50 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 50 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 50 +++++++++++++++++++++++++++++++ 5 files changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi index 620b17e4031f..d2cf81926f28 100644 --- a/arch/arm64/boot/dts/apple/t6001.dtsi +++ b/arch/arm64/boot/dts/apple/t6001.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index a963a5011799..e36f422d257d 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 4c224e686ffe..110bc6719512 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -50,6 +50,56 @@ reg = <0x2 0x920a1300 0x0 0x100>; #address-cells = <2>; #size-cells = <0>; + + pmic1: pmic@f { + compatible = "apple,maverick-pmic", "apple,spmi-nvmem"; + reg = <0xf SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + pm_setting: pm-setting@1405 { + reg = <0x1405 0x1>; + }; + + rtc_offset: rtc-offset@1411 { + reg = <0x1411 0x6>; + }; + + boot_stage: boot-stage@6001 { + reg = <0x6001 0x1>; + }; + + boot_error_count: boot-error-count@6002 { + reg = <0x6002 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@6002 { + reg = <0x6002 0x1>; + bits = <4 4>; + }; + + boot_error_stage: boot-error-stage@6003 { + reg = <0x6003 0x1>; + }; + + shutdown_flag: shutdown-flag@600f { + reg = <0x600f 0x1>; + bits = <3 1>; + }; + + fault_shadow: fault-shadow@867b { + reg = <0x867b 0x10>; + }; + + socd: socd@8b00 { + reg = <0x8b00 0x400>; + }; + }; + }; }; wdt: watchdog@2922b0000 { diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index bdb1cb9e406a..20faf0c0d809 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -747,6 +747,56 @@ reg = <0x2 0x3d0d9300 0x0 0x100>; #address-cells = <2>; #size-cells = <0>; + + pmic1: pmic@f { + compatible = "apple,sera-pmic", "apple,spmi-nvmem"; + reg = <0xf SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + boot_stage: boot-stage@9f01 { + reg = <0x9f01 0x1>; + }; + + boot_error_count: boot-error-count@9f02 { + reg = <0x9f02 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@9f02 { + reg = <0x9f02 0x1>; + bits = <4 4>; + }; + + boot_error_stage: boot-error-stage@9f03 { + reg = <0x9f03 0x1>; + }; + + shutdown_flag: shutdown-flag@9f0f { + reg = <0x9f0f 0x1>; + bits = <3 1>; + }; + + fault_shadow: fault-shadow@a67b { + reg = <0xa67b 0x10>; + }; + + socd: socd@ab00 { + reg = <0xab00 0x400>; + }; + + pm_setting: pm-setting@d001 { + reg = <0xd001 0x1>; + }; + + rtc_offset: rtc-offset@d100 { + reg = <0xd100 0x6>; + }; + }; + }; }; pinctrl_nub: pinctrl@23d1f0000 { diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 950d1f906ba3..e95711d8337f 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -787,6 +787,56 @@ reg = <0x2 0x3d714000 0x0 0x100>; #address-cells = <2>; #size-cells = <0>; + + pmic1: pmic@e { + compatible = "apple,stowe-pmic", "apple,spmi-nvmem"; + reg = <0xe SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + fault_shadow: fault-shadow@867b { + reg = <0x867b 0x10>; + }; + + socd: socd@8b00 { + reg = <0x8b00 0x400>; + }; + + boot_stage: boot-stage@f701 { + reg = <0xf701 0x1>; + }; + + boot_error_count: boot-error-count@f702 { + reg = <0xf702 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@f702 { + reg = <0xf702 0x1>; + bits = <4 4>; + }; + + boot_error_stage: boot-error-stage@f703 { + reg = <0xf703 0x1>; + }; + + shutdown_flag: shutdown-flag@f70f { + reg = <0xf70f 0x1>; + bits = <3 1>; + }; + + pm_setting: pm-setting@f801 { + reg = <0xf801 0x1>; + }; + + rtc_offset: rtc-offset@f900 { + reg = <0xf900 0x6>; + }; + }; + }; }; pinctrl_smc: pinctrl@23e820000 { -- cgit v1.2.3