From 3c0d5d6e11c980890e9f5d6e1eb734e9297ea252 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 12 Feb 2016 14:19:27 +0900 Subject: drm/nouveau/clk/gk20a: only restore divider to 1:1 if needed Only restore the 1:1 divider if it is not set already. Also use the proper masks for this operation and add a second write as done in the Android code. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index e72e20a0d009..0746bb3e3075 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -429,9 +429,16 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) /* restore out divider 1:1 */ val = nvkm_rd32(device, GPC2CLK_OUT); - val &= ~GPC2CLK_OUT_VCODIV_MASK; - udelay(2); - nvkm_wr32(device, GPC2CLK_OUT, val); + if ((val & GPC2CLK_OUT_VCODIV_MASK) != + (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT)) { + val &= ~GPC2CLK_OUT_VCODIV_MASK; + val |= GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT; + udelay(2); + nvkm_wr32(device, GPC2CLK_OUT, val); + /* Intentional 2nd write to assure linear divider operation */ + nvkm_wr32(device, GPC2CLK_OUT, val); + nvkm_rd32(device, GPC2CLK_OUT); + } /* slide up to new NDIV */ return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; -- cgit v1.2.3