From 564ee46fb7b3d1cb9214ab32dde60cbe044b1f16 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Thu, 15 Mar 2012 18:40:28 +0100 Subject: powerpc/85xx: p2020rdb & p1010rdb - lower spi flash freq to 40Mhz This is here most likely since the FSL bsp. Back in the FSL bsp it was set to 50Mhz and working. However the driver divided the SoC freq. only by 2. According to the TRM the platform clock (which the manual refers in its formula) is the system clock divided by two. So in the end it has to divide by 4 and this is what the fsl-spi driver in tree is doing. Since then the flash is not wokring I guess. After chaning the freq from 50Mhz to 40Mhz like others do then I can access the flash. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1010rdb.dtsi | 2 +- arch/powerpc/boot/dts/p2020rdb.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi index d4c4a7730285..1c41ef0c817c 100644 --- a/arch/powerpc/boot/dts/p1010rdb.dtsi +++ b/arch/powerpc/boot/dts/p1010rdb.dtsi @@ -138,7 +138,7 @@ #size-cells = <1>; compatible = "spansion,s25sl12801"; reg = <0>; - spi-max-frequency = <50000000>; + spi-max-frequency = <40000000>; partition@0 { /* 1MB for u-boot Bootloader Image */ diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts index 8f25ef2e6e42..153bc76bb48e 100644 --- a/arch/powerpc/boot/dts/p2020rdb.dts +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -157,7 +157,7 @@ #size-cells = <1>; compatible = "spansion,s25sl12801"; reg = <0>; - spi-max-frequency = <50000000>; + spi-max-frequency = <40000000>; partition@0 { /* 512KB for u-boot Bootloader Image */ -- cgit v1.2.3