From 599d85ccb7f64abb539e9795999e8a082bdbdc97 Mon Sep 17 00:00:00 2001 From: yagi Date: Mon, 4 Jun 2012 18:59:13 +0900 Subject: update MSL and serial --- arch/arm/mach-mvf/Kconfig | 10 +- arch/arm/mach-mvf/Makefile | 2 +- arch/arm/mach-mvf/board-twr_vf600.c | 37 +- arch/arm/mach-mvf/cpu.c | 25 +- arch/arm/mach-mvf/devices-mvf.h | 6 +- arch/arm/mach-mvf/pcie.c | 484 ---------------------- arch/arm/mach-mvf/system.c | 12 +- arch/arm/plat-mxc/cpu.c | 4 + arch/arm/plat-mxc/devices/platform-imx-uart.c | 18 + arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c | 5 + arch/arm/plat-mxc/include/mach/mvf.h | 14 +- 11 files changed, 67 insertions(+), 550 deletions(-) delete mode 100644 arch/arm/mach-mvf/pcie.c diff --git a/arch/arm/mach-mvf/Kconfig b/arch/arm/mach-mvf/Kconfig index 38c3acd19659..08a5c33d1dce 100644 --- a/arch/arm/mach-mvf/Kconfig +++ b/arch/arm/mach-mvf/Kconfig @@ -7,7 +7,7 @@ config ARCH_VF6XX #select ARCH_MXC_AUDMUX_V2 select ARM_GIC #select ARCH_HAS_CPUFREQ - #select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_FEC #select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL #select IMX_HAVE_PLATFORM_IMX_IPUV3 @@ -22,7 +22,7 @@ config MACH_TWR_VF600 bool "Support MVF TWR-VF600 platform" select ARCH_VF6XX select SOC_VF6XX - #select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_UART #select IMX_HAVE_PLATFORM_DMA select IMX_HAVE_PLATFORM_FEC #select IMX_HAVE_PLATFORM_GPMI_NFC @@ -43,7 +43,7 @@ config MACH_TWR_VF600 #select IMX_HAVE_PLATFORM_IMX_OCOTP #select IMX_HAVE_PLATFORM_IMX_VIIM #select IMX_HAVE_PLATFORM_IMX2_WDT - #select IMX_HAVE_PLATFORM_IMX_SNVS_RTC + select IMX_HAVE_PLATFORM_IMX_SNVS_RTC #select IMX_HAVE_PLATFORM_IMX_PM #select IMX_HAVE_PLATFORM_MXC_HDMI #select IMX_HAVE_PLATFORM_IMX_ASRC @@ -82,8 +82,4 @@ endchoice endmenu -config IMX_PCIE - bool "PCI Express support" - select PCI - endif diff --git a/arch/arm/mach-mvf/Makefile b/arch/arm/mach-mvf/Makefile index a601ac34fa12..a96c70307259 100644 --- a/arch/arm/mach-mvf/Makefile +++ b/arch/arm/mach-mvf/Makefile @@ -3,6 +3,6 @@ # # Object file lists. -obj-y := mm.o devices.o irq.o clock.o bus_freq.o system.o mvf_fec.o +obj-y := cpu.o mm.o devices.o irq.o clock.o bus_freq.o system.o mvf_fec.o obj-$(CONFIG_MACH_TWR_VF600) += board-twr_vf600.o diff --git a/arch/arm/mach-mvf/board-twr_vf600.c b/arch/arm/mach-mvf/board-twr_vf600.c index e2a4bf71794d..d9c6658554c0 100644 --- a/arch/arm/mach-mvf/board-twr_vf600.c +++ b/arch/arm/mach-mvf/board-twr_vf600.c @@ -79,21 +79,20 @@ //#include "cpu_op-mvf.h" #include "board-twr_vf600.h" -#if 0 //FIXME void __init early_console_setup(unsigned long base, struct clk *clk); +#if 0 //FIXME static const struct imxuart_platform_data mx6_arm2_uart1_data __initconst = { .flags = IMXUART_HAVE_RTSCTS | IMXUART_USE_DCEDTE | IMXUART_SDMA, .dma_req_rx = MX6Q_DMA_REQ_UART2_RX, .dma_req_tx = MX6Q_DMA_REQ_UART2_TX, }; +#endif //FIXME static inline void twr_vf600_init_uart(void) { - imx6q_add_imx_uart(3, NULL); - imx6q_add_imx_uart(1, &mx6_arm2_uart1_data); + mvf_add_imx_uart(1, NULL); } -#endif //FIXME //FIXME static int twr_vf600_fec_phy_init(struct phy_device *phydev) @@ -182,31 +181,8 @@ static void __init twr_vf600_init(void) BUG_ON(!common_pads); mxc_iomux_vmvf_setup_multiple_pads(common_pads, common_pads_cnt); - /* - * IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive - * because all of them use GPIO_16. - * S/PDIF out and can1 stby are mutually exclusive because both - * use GPIO_17. - */ - /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock - * For MX6 GPR1 bit21 meaning: - * Bit21: 0 - GPIO_16 pad output - * 1 - GPIO_16 pad input - */ - //mxc_iomux_set_gpr_register(1, 21, 1, 1); - - /* - * the following is the common devices support on the shared ARM2 boards - * Since i.MX6DQ/DL share the same memory/Register layout, we don't - * need to diff the i.MX6DQ or i.MX6DL here. We can simply use the - * mx6q_add_features() for the shared devices. For which only exist - * on each indivual SOC, we can use cpu_is_mx6q/6dl() to diff it. - */ - -#if 0 twr_vf600_init_uart(); - mvf_add_imx_snvs_rtc(); -#endif + vf6xx_add_imx_snvs_rtc(); mvf_init_fec(fec_data); #if 0 @@ -228,13 +204,8 @@ static void __init mvf_timer_init(void) #endif mvf_clocks_init(128000, 24000000, 32000, 24000000); -#if 1 //FIXME uart_clk = clk_get_sys("imx-uart.1", NULL); early_console_setup(MVF_UART1_BASE_ADDR, uart_clk); -#else - uart_clk = clk_get_sys("imx-uart.2", NULL); - early_console_setup(MVF_UART2_BASE_ADDR, uart_clk); -#endif } static struct sys_timer mxc_timer = { diff --git a/arch/arm/mach-mvf/cpu.c b/arch/arm/mach-mvf/cpu.c index 79ba9c4db1fb..d3734f576502 100644 --- a/arch/arm/mach-mvf/cpu.c +++ b/arch/arm/mach-mvf/cpu.c @@ -34,12 +34,14 @@ #include "cpu_op-mvf.h" +#if 0 //FIXME void *mvf_wait_in_iram_base; void (*mvf_wait_in_iram)(void); extern void mvf_wait(void); struct cpu_op *(*get_cpu_op)(int *op); +#endif bool enable_wait_mode; u32 arm_max_freq = CPU_AT_450MHz; @@ -65,15 +67,15 @@ static int get_vf6xx_srev(void) iounmap(romcp); switch (rev) { case 0x02: - cpu_silicon_rev = CHIP_REV_1_1; + cpu_silicon_rev = IMX_CHIP_REVISION_1_1; break; case 0x10: break; case 0x20: - cpu_silicon_rev = CHIP_REV_3_0; + cpu_silicon_rev = IMX_CHIP_REVISION_3_0; break; default: - cpu_silicon_rev = CHIP_REV_1_0; + cpu_silicon_rev = IMX_CHIP_REVISION_1_0; break; } return 0; @@ -103,7 +105,9 @@ static int __init post_cpu_init(void) unsigned long iram_paddr, cpaddr; +#if 0 //FIXME iram_init(MVF_IRAM0_BASE_ADDR, MVF_IRAM0_SIZE); //FIXME +#endif base = ioremap(AIPS0_ON_BASE_ADDR, PAGE_SIZE); __raw_writel(0x0, base + 0x20); @@ -126,7 +130,7 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x80); iounmap(base); - base = ioremap(AIPS2_ON_BASE_ADDR, PAGE_SIZE); + base = ioremap(AIPS1_ON_BASE_ADDR, PAGE_SIZE); __raw_writel(0x0, base + 0x20); __raw_writel(0x0, base + 0x24); __raw_writel(0x0, base + 0x28); @@ -147,6 +151,7 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x80); iounmap(base); +#if 0 //FIXME if (enable_wait_mode) { /* Allow SCU_CLK to be disabled when all cores are in WFI*/ base = MVF_IO_ADDRESS(MVF_CA5_SCU_GIC_BASE_ADDR); @@ -155,13 +160,11 @@ static int __init post_cpu_init(void) __raw_writel(reg, base); } -#if 0 //FIXME /* Disable SRC warm reset to work aound system reboot issue */ base = MVF_IO_ADDRESS(MVF_ASRC_BASE_ADDR); reg = __raw_readl(base); reg &= ~0x1; __raw_writel(reg, base); -#endif /* Allocate IRAM for WAIT code. */ /* Move wait routine into iRAM */ @@ -171,7 +174,7 @@ static int __init post_cpu_init(void) mvf_wait_in_iram_base = __arm_ioremap(iram_paddr, SZ_4K, MT_MEMORY_NONCACHED); pr_info("cpaddr = %x wait_iram_base=%x\n", - (unsigned int)cpaddr, (unsigned int)mx6_wait_in_iram_base); + (unsigned int)cpaddr, (unsigned int)mvf_wait_in_iram_base); /* * Need to run the suspend code from IRAM as the DDR needs @@ -179,14 +182,16 @@ static int __init post_cpu_init(void) */ memcpy((void *)cpaddr, mvf_wait, SZ_4K); mvf_wait_in_iram = (void *)mvf_wait_in_iram_base; +#endif gpc_base = MVF_IO_ADDRESS(MVF_GPC_BASE_ADDR); - ccm_base = MX6_IO_ADDRESS(MVF_CCM_BASE_ADDR); + ccm_base = MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR); return 0; } postcore_initcall(post_cpu_init); +#if 0 //FIXME static int __init enable_wait(char *p) { if (memcmp(p, "on", 2) == 0) { @@ -203,12 +208,12 @@ early_param("enable_wait_mode", enable_wait); static int __init arm_core_max(char *p) { if (memcmp(p, "450", 3) == 0) { - arm_max_freq = CPU_AT_1_450MHz; + arm_max_freq = CPU_AT_450MHz; p += 3; } return 0; } early_param("arm_freq", arm_core_max); - +#endif diff --git a/arch/arm/mach-mvf/devices-mvf.h b/arch/arm/mach-mvf/devices-mvf.h index 0174224f0c70..821afa0a5624 100644 --- a/arch/arm/mach-mvf/devices-mvf.h +++ b/arch/arm/mach-mvf/devices-mvf.h @@ -21,9 +21,9 @@ #include #include -extern const struct imx_imx_uart_1irq_data vf6xx_imx_uart_data[] __initconst; -#define vf6xx_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&vf6xx_imx_uart_data[id], pdata) +extern const struct imx_imx_uart_1irq_data mvf_imx_uart_data[] __initconst; +#define mvf_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&mvf_imx_uart_data[id], pdata) extern const struct imx_snvs_rtc_data vf6xx_imx_snvs_rtc_data __initconst; #define vf6xx_add_imx_snvs_rtc() \ diff --git a/arch/arm/mach-mvf/pcie.c b/arch/arm/mach-mvf/pcie.c deleted file mode 100644 index 9959bbceaa4d..000000000000 --- a/arch/arm/mach-mvf/pcie.c +++ /dev/null @@ -1,484 +0,0 @@ -/* - * arch/arm/mach-mx6/pcie.c - * - * PCIe host controller driver for IMX6 SOCs - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Bits taken from arch/arm/mach-dove/pcie.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "crm_regs.h" - -/* Register Definitions */ -#define PRT_LOG_R_BaseAddress 0x700 - -/* Register DB_R0 */ -/* Debug Register 0 */ -#define DB_R0 (PRT_LOG_R_BaseAddress + 0x28) -#define DB_R0_RegisterSize 32 -#define DB_R0_RegisterResetValue 0x0 -#define DB_R0_RegisterResetMask 0xFFFFFFFF -/* End of Register Definition for DB_R0 */ - -/* Register DB_R1 */ -/* Debug Register 1 */ -#define DB_R1 (PRT_LOG_R_BaseAddress + 0x2c) -#define DB_R1_RegisterSize 32 -#define DB_R1_RegisterResetValue 0x0 -#define DB_R1_RegisterResetMask 0xFFFFFFFF -/* End of Register Definition for DB_R1 */ - -#define ATU_R_BaseAddress 0x900 -#define ATU_VIEWPORT_R (ATU_R_BaseAddress + 0x0) -#define ATU_REGION_CTRL1_R (ATU_R_BaseAddress + 0x4) -#define ATU_REGION_CTRL2_R (ATU_R_BaseAddress + 0x8) -#define ATU_REGION_LOWBASE_R (ATU_R_BaseAddress + 0xC) -#define ATU_REGION_UPBASE_R (ATU_R_BaseAddress + 0x10) -#define ATU_REGION_LIMIT_ADDR_R (ATU_R_BaseAddress + 0x14) -#define ATU_REGION_LOW_TRGT_ADDR_R (ATU_R_BaseAddress + 0x18) -#define ATU_REGION_UP_TRGT_ADDR_R (ATU_R_BaseAddress + 0x1C) - -/* GPR1: iomuxc_gpr1_pcie_ref_clk_en(iomuxc_gpr1[16]) */ -#define iomuxc_gpr1_pcie_ref_clk_en (1 << 16) -/* GPR1: iomuxc_gpr1_test_powerdown(iomuxc_gpr1_18) */ -#define iomuxc_gpr1_test_powerdown (1 << 18) - -/* GPR12: iomuxc_gpr12_los_level(iomuxc_gpr12[8:4]) */ -#define iomuxc_gpr12_los_level (0x1F << 4) -/* GPR12: iomuxc_gpr12_app_ltssm_enable(iomuxc_gpr12[10]) */ -#define iomuxc_gpr12_app_ltssm_enable (1 << 10) -/* GPR12: iomuxc_gpr12_device_type(iomuxc_gpr12[15:12]) */ -#define iomuxc_gpr12_device_type (0xF << 12) - -/* GPR8: iomuxc_gpr8_tx_deemph_gen1(iomuxc_gpr8[5:0]) */ -#define iomuxc_gpr8_tx_deemph_gen1 (0x3F << 0) -/* GPR8: iomuxc_gpr8_tx_deemph_gen2_3p5db(iomuxc_gpr8[11:6]) */ -#define iomuxc_gpr8_tx_deemph_gen2_3p5db (0x3F << 6) -/* GPR8: iomuxc_gpr8_tx_deemph_gen2_6db(iomuxc_gpr8[17:12]) */ -#define iomuxc_gpr8_tx_deemph_gen2_6db (0x3F << 12) -/* GPR8: iomuxc_gpr8_tx_swing_full(iomuxc_gpr8[24:18]) */ -#define iomuxc_gpr8_tx_swing_full (0x7F << 18) -/* GPR8: iomuxc_gpr8_tx_swing_low(iomuxc_gpr8[31:25]) */ -#define iomuxc_gpr8_tx_swing_low (0x7F << 25) - -/* End of Register Definitions */ - -#define PCIE_DBI_BASE_ADDR (PCIE_ARB_END_ADDR - SZ_16K + 1) - -#define PCIE_CONF_BUS(b) (((b) & 0xFF) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1F) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) - -enum { - MemRdWr = 0, - MemRdLk = 1, - IORdWr = 2, - CfgRdWr0 = 4, - CfgRdWr1 = 5 -}; - -struct imx_pcie_port { - u8 index; - u8 root_bus_nr; - void __iomem *base; - void __iomem *dbi_base; - spinlock_t conf_lock; - - char io_space_name[16]; - char mem_space_name[16]; - - struct resource res[2]; -}; - -static struct imx_pcie_port imx_pcie_port[1]; -static int num_pcie_ports; - -/* IMX PCIE GPR configure routines */ -static inline void imx_pcie_clrset(u32 mask, u32 val, void __iomem *addr) -{ - writel(((readl(addr) & ~mask) | (val & mask)), addr); -} - -static struct imx_pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = imx_pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } - - return i >= 0 ? imx_pcie_port + i : NULL; -} - -static int __init imx_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct imx_pcie_port *pp; - - if (nr >= num_pcie_ports) - return 0; - - pp = &imx_pcie_port[nr]; - pp->root_bus_nr = sys->busnr; - - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = PCIE_ARB_BASE_ADDR; - pp->res[0].end = pp->res[0].start + SZ_64K - 1; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &pp->res[0]; - - /* - * IORESOURCE_MEM - */ - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), - "PCIe %d MEM", pp->index); - pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; - if (pp->index == 0) { - pp->res[1].start = PCIE_ARB_BASE_ADDR + SZ_64K; - pp->res[1].end = pp->res[1].start + SZ_16M - SZ_128K - 1; - } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) - panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &pp->res[1]; - - sys->resource[2] = NULL; - - return 1; -} - -static void __init imx_pcie_preinit(void) -{ - pcibios_setup("debug"); -} - -static int imx_pcie_link_up(void __iomem *dbi_base) -{ - /* Check the pcie link up or link down */ - u32 rc, iterations = 0x100000; - - do { - /* link is debug bit 36 debug 1 start in bit 32 */ - rc = readl(dbi_base + DB_R1) & (0x1 << (36-32)) ; - iterations--; - if ((iterations % 0x100000) == 0) - pr_info("link up failed!\n"); - } while (!rc && iterations); - - if (!rc) - return 0; - return 1; -} - -static int pcie_valid_config(struct imx_pcie_port *pp, int bus_num, int dev) -{ - /*If there is no link, then there is no device*/ - if (bus_num != pp->root_bus_nr) { - if (!imx_pcie_link_up(pp->dbi_base)) - return 0; - } - - /* - * Don't go out when trying to access nonexisting devices - * on the local bus. - * We have only one slot on the root port. - */ - if (bus_num == pp->root_bus_nr && dev > 0) - return 0; - - return 1; -} - -static void imx_pcie_regions_setup(void __iomem *dbi_base) -{ - /* - * i.MX6 defines 16MB in the AXI address map for PCIe. - * - * That address space excepted the pcie registers is - * split and defined into different regions by iATU, - * with sizes and offsets as follows: - * - * 0x0100_0000 --- 0x0100_FFFF 64KB IORESOURCE_IO - * 0x0101_0000 --- 0x01FE_FFFF 16MB - 128KB IORESOURCE_MEM - * 0x01FF_0000 --- 0x01FF_FFFF 64KB Cfg + Registers - */ - - /* CMD reg:I/O space, MEM space, and Bus Master Enable */ - writel(readl(dbi_base + PCI_COMMAND) - | PCI_COMMAND_IO - | PCI_COMMAND_MEMORY - | PCI_COMMAND_MASTER, - dbi_base + PCI_COMMAND); - /* - * region0 outbound used to access target cfg - */ - writel(0, dbi_base + ATU_VIEWPORT_R); - writel(PCIE_ARB_END_ADDR - SZ_64K + 1, dbi_base + ATU_REGION_LOWBASE_R); - writel(0, dbi_base + ATU_REGION_UPBASE_R); - writel(PCIE_ARB_END_ADDR, dbi_base + ATU_REGION_LIMIT_ADDR_R); - writel(0, dbi_base + ATU_REGION_LOW_TRGT_ADDR_R); - writel(0, dbi_base + ATU_REGION_UP_TRGT_ADDR_R); - writel(CfgRdWr0, dbi_base + ATU_REGION_CTRL1_R); - writel((1<<31), dbi_base + ATU_REGION_CTRL2_R); - - /* - * region1 outbound used to as IORESOURCE_IO - */ - writel(1, dbi_base + ATU_VIEWPORT_R); - writel(0, dbi_base + ATU_REGION_LOWBASE_R); - writel(0, dbi_base + ATU_REGION_UPBASE_R); - writel(SZ_64K - 1, dbi_base + ATU_REGION_LIMIT_ADDR_R); - writel(0, dbi_base + ATU_REGION_LOW_TRGT_ADDR_R); - writel(0, dbi_base + ATU_REGION_UP_TRGT_ADDR_R); - writel(IORdWr, dbi_base + ATU_REGION_CTRL1_R); - writel((1<<31), dbi_base + ATU_REGION_CTRL2_R); - - /* - * region2 outbound used to as IORESOURCE_MEM - */ - writel(2, dbi_base + ATU_VIEWPORT_R); - writel(0, dbi_base + ATU_REGION_LOWBASE_R); - writel(0, dbi_base + ATU_REGION_UPBASE_R); - writel(SZ_16M - SZ_128K - 1, dbi_base + ATU_REGION_LIMIT_ADDR_R); - writel(0, dbi_base + ATU_REGION_LOW_TRGT_ADDR_R); - writel(0, dbi_base + ATU_REGION_UP_TRGT_ADDR_R); - writel(MemRdWr, dbi_base + ATU_REGION_CTRL1_R); - writel((1<<31), dbi_base + ATU_REGION_CTRL2_R); -} - -static int imx_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) -{ - struct imx_pcie_port *pp = bus_to_port(bus->number); - unsigned long flags; - u32 va_address; - - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { - *val = 0xFFFFFFFF; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - - spin_lock_irqsave(&pp->conf_lock, flags); - - va_address = (u32)pp->base + - PCIE_CONF_BUS(bus->number) + - PCIE_CONF_DEV(PCI_SLOT(devfn)) + - PCIE_CONF_FUNC(PCI_FUNC(devfn)) + - (where & ~0x3); - - *val = readl(va_address); - - if (size == 1) - *val = (*val >> (8 * (where & 3))) & 0xFF; - else if (size == 2) - *val = (*val >> (8 * (where & 3))) & 0xFFFF; - - spin_unlock_irqrestore(&pp->conf_lock, flags); - - return PCIBIOS_SUCCESSFUL; -} - -static int imx_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - struct imx_pcie_port *pp = bus_to_port(bus->number); - unsigned long flags; - u32 va_address = 0, mask = 0, tmp = 0; - int ret = PCIBIOS_SUCCESSFUL; - - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - spin_lock_irqsave(&pp->conf_lock, flags); - - va_address = (u32)pp->base + - PCIE_CONF_BUS(bus->number) + - PCIE_CONF_DEV(PCI_SLOT(devfn)) + - PCIE_CONF_FUNC(PCI_FUNC(devfn)) + - (where & ~0x3); - - if (size == 4) { - writel(val, va_address); - goto exit; - } - - if (size == 2) - mask = ~(0xFFFF << ((where & 0x3) * 8)); - else if (size == 1) - mask = ~(0xFF << ((where & 0x3) * 8)); - else - ret = PCIBIOS_BAD_REGISTER_NUMBER; - - tmp = readl(va_address) & mask; - tmp |= val << ((where & 0x3) * 8); - writel(tmp, va_address); -exit: - spin_unlock_irqrestore(&pp->conf_lock, flags); - - return ret; -} - -static struct pci_ops imx_pcie_ops = { - .read = imx_pcie_rd_conf, - .write = imx_pcie_wr_conf, -}; - -static struct pci_bus __init * -imx_pcie_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct pci_bus *bus; - - if (nr < num_pcie_ports) { - bus = pci_scan_bus(sys->busnr, &imx_pcie_ops, sys); - } else { - bus = NULL; - BUG(); - } - - return bus; -} - -static int __init imx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - return MXC_INT_PCIE_0; -} - -static struct hw_pci imx_pci __initdata = { - .nr_controllers = 1, - .swizzle = pci_std_swizzle, - .setup = imx_pcie_setup, - .preinit = imx_pcie_preinit, - .scan = imx_pcie_scan_bus, - .map_irq = imx_pcie_map_irq, -}; - -static void imx_pcie_enable_controller(void) -{ - struct clk *pcie_clk; - - imx_pcie_clrset(iomuxc_gpr1_test_powerdown, 0 << 18, IOMUXC_GPR1); - - /* enable the clks */ - pcie_clk = clk_get(NULL, "pcie_clk"); - if (IS_ERR(pcie_clk)) - pr_err("no pcie clock.\n"); - - if (clk_enable(pcie_clk)) { - pr_err("can't enable pcie clock.\n"); - clk_put(pcie_clk); - } -} - -static void card_reset(void) -{ - /* Add one reset to the pcie external device */ -} - -static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base) -{ - if (imx_pcie_link_up(dbi_base)) { - struct imx_pcie_port *pp = &imx_pcie_port[num_pcie_ports++]; - - pr_info("IMX PCIe port: link up.\n"); - - pp->index = 0; - pp->root_bus_nr = -1; - pp->base = base; - pp->dbi_base = dbi_base; - spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); - } else - pr_info("IMX PCIe port: link down!\n"); -} - -static int __init imx_pcie_init(void) -{ - void __iomem *base, *dbi_base; - - base = ioremap_nocache(PCIE_ARB_END_ADDR - SZ_64K + 1, SZ_32K); - if (!base) { - pr_err("error with ioremap in function %s\n", __func__); - return -EIO; - } - - dbi_base = ioremap_nocache(PCIE_DBI_BASE_ADDR, SZ_16K); - if (!dbi_base) { - pr_err("error with ioremap in function %s\n", __func__); - iounmap(base); - return -EIO; - } - - /* FIXME the field name should be aligned to RM */ - imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 0 << 10, IOMUXC_GPR12); - - /* configure constant input signal to the pcie ctrl and phy */ - imx_pcie_clrset(iomuxc_gpr12_device_type, PCI_EXP_TYPE_ROOT_PORT << 12, - IOMUXC_GPR12); - imx_pcie_clrset(iomuxc_gpr12_los_level, 9 << 4, IOMUXC_GPR12); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen1, 21 << 0, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_3p5db, 21 << 6, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 32 << 12, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_swing_full, 115 << 18, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_swing_low, 115 << 25, IOMUXC_GPR8); - - /* Enable the pwr, clks and so on */ - imx_pcie_enable_controller(); - - imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 1 << 16, IOMUXC_GPR1); - - /* togle the external card's reset */ - card_reset() ; - - usleep_range(3000, 4000); - imx_pcie_regions_setup(dbi_base); - usleep_range(3000, 4000); - - /* start link up */ - imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 1 << 10, IOMUXC_GPR12); - - /* add the pcie port */ - add_pcie_port(base, dbi_base); - - pci_common_init(&imx_pci); - pr_info("pcie init successful\n"); - return 0; -} -subsys_initcall(imx_pcie_init); diff --git a/arch/arm/mach-mvf/system.c b/arch/arm/mach-mvf/system.c index 7feca9297700..64eb8b9bd25a 100644 --- a/arch/arm/mach-mvf/system.c +++ b/arch/arm/mach-mvf/system.c @@ -33,12 +33,12 @@ #include "regs-anadig.h" #if 0 -#define SCU_CTRL 0x00 -#define SCU_CONFIG 0x04 -#define SCU_CPU_STATUS 0x08 -#define SCU_INVALIDATE 0x0c -#define SCU_FPGA_REVISION 0x10 -#define GPC_CNTR_OFFSET 0x0 +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 +#define GPC_CNTR_OFFSET 0x0 #define GPC_PGC_GPU_PGCR_OFFSET 0x260 #define GPC_PGC_CPU_PDN_OFFSET 0x2a0 #define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c index 143a9b7b0aaa..bb02d697b5c0 100755 --- a/arch/arm/plat-mxc/cpu.c +++ b/arch/arm/plat-mxc/cpu.c @@ -22,6 +22,7 @@ unsigned int __mxc_cpu_type; EXPORT_SYMBOL(__mxc_cpu_type); extern int mxc_early_serial_console_init(unsigned long base, struct clk *clk); +extern int mvf_early_serial_console_init(unsigned long base, struct clk *clk); void (*set_num_cpu_op)(int num); void mxc_set_cpu_type(unsigned int type) @@ -67,4 +68,7 @@ void __init early_console_setup(unsigned long base, struct clk *clk) #ifdef CONFIG_SERIAL_IMX_CONSOLE mxc_early_serial_console_init(base, clk); #endif +#ifdef CONFIG_SERIAL_MVF_CONSOLE + mvf_early_serial_console_init(base, clk); +#endif } diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index ecfadc3060ea..6b2b9dd6ced2 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -137,6 +137,19 @@ const struct imx_imx_uart_1irq_data imx6q_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX6Q */ +#ifdef CONFIG_SOC_VF6XX +const struct imx_imx_uart_1irq_data mvf_imx_uart_data[] __initconst = { +#define mvf_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MVF, _id, _hwid, SZ_4K) + mvf_imx_uart_data_entry(0, 0), + mvf_imx_uart_data_entry(1, 1), + mvf_imx_uart_data_entry(2, 2), + mvf_imx_uart_data_entry(3, 3), + mvf_imx_uart_data_entry(4, 4), + mvf_imx_uart_data_entry(5, 5), +}; +#endif /* ifdef CONFIG_SOC_VF6XX */ + struct platform_device *__init imx_add_imx_uart_3irq( const struct imx_imx_uart_3irq_data *data, const struct imxuart_platform_data *pdata) @@ -181,6 +194,11 @@ struct platform_device *__init imx_add_imx_uart_1irq( }, }; +#ifdef CONFIG_ARCH_MVF + return imx_add_platform_device("mvf-uart", data->id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +#else return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +#endif } diff --git a/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c b/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c index 031a074162fc..04e1a96f62e3 100644 --- a/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c @@ -33,6 +33,11 @@ const struct imx_snvs_rtc_data imx6q_imx_snvs_rtc_data __initconst = imx_snvs_rtc_data_entry_single(MX6Q); #endif /* ifdef CONFIG_SOC_IMX6Q */ +#ifdef CONFIG_SOC_VF6XX +const struct imx_snvs_rtc_data vf6xx_imx_snvs_rtc_data __initconst = + imx_snvs_rtc_data_entry_single(VF6XX); +#endif /* ifdef CONFIG_SOC_VF6XX */ + struct platform_device *__init imx_add_snvs_rtc( const struct imx_snvs_rtc_data *data) { diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index ed7646beb682..b21f02634371 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -291,6 +291,7 @@ #define VF6XX_UART4_BASE_ADDR MVF_UART4_BASE_ADDR #define VF6XX_UART5_BASE_ADDR MVF_UART5_BASE_ADDR #define VF6XX_FEC_BASE_ADDR MVF_ENET0_IEEE1588_BASE_ADDR +#define VF6XX_SNVS_BASE_ADDR MVF_SNVS_BASE_ADDR #define MVF_IO_P2V(x) IMX_IO_P2V(x) #define MVF_IO_ADDRESS(x) IOMEM(MVF_IO_P2V(x)) @@ -395,13 +396,14 @@ #define MXC_INT_GPIOE 153 #define MXC_INT_END 153 -#define VF6XX_INT_UART0 MXC_INT_UART0 -#define VF6XX_INT_UART1 MXC_INT_UART1 -#define VF6XX_INT_UART2 MXC_INT_UART2 -#define VF6XX_INT_UART3 MXC_INT_UART3 -#define VF6XX_INT_UART4 MXC_INT_UART4 -#define VF6XX_INT_UART5 MXC_INT_UART5 +#define MVF_INT_UART0 MXC_INT_UART0 +#define MVF_INT_UART1 MXC_INT_UART1 +#define MVF_INT_UART2 MXC_INT_UART2 +#define MVF_INT_UART3 MXC_INT_UART3 +#define MVF_INT_UART4 MXC_INT_UART4 +#define MVF_INT_UART5 MXC_INT_UART5 #define VF6XX_INT_FEC MXC_INT_ENET_MAC0 +#define VF6XX_INT_SNVS MXC_INT_SNVS_FUNCTIONAL #define IRQ_GLOBALTIMER 27 #define IRQ_LOCALTIMER 29 -- cgit v1.2.3