From 7d33bebaf50ad911bfa85668040a4ca42150ca09 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Sat, 14 Jan 2012 22:54:23 -0800 Subject: ARM: tegra: cardhu: Specify PLLD2 as backup clock source Since not all possible PLLP output rates (216MHz, 408MHz or 204MHz) can provide accurate enough pixel clock rate for cardhu panel, use PLLD2 as backup clock source. Bug 928260 Change-Id: I767e621606e849cb7d1976fbed198b9427660544 Reviewed-on: http://git-master/r/76034 Reviewed-by: Jon Mayo Reviewed-by: Kevin Huang (Eng-SW) Signed-off-by: Alex Frid Signed-off-by: Varun Wadekar Reviewed-on: http://git-master/r/76816 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/board-cardhu-panel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 230e5f428dc0..90801b0e610d 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -942,6 +942,8 @@ static struct tegra_dc_out cardhu_disp1_out = { .parent_clk = "pll_p", #ifndef CONFIG_TEGRA_CARDHU_DSI + .parent_clk_backup = "pll_d2_out0", + .type = TEGRA_DC_OUT_RGB, .depth = 18, .dither = TEGRA_DC_ORDERED_DITHER, -- cgit v1.2.3