From 87098700b3cb953d0a2ccd1946ca01853b22e783 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 11 Sep 2026 21:21:05 +0000 Subject: dt-bindings: iommu: arm,smmu-v3: Add arm,instdata-override property arm,instdata-override DT property is intended to be used for SMMUs that have a silicon integration issue with the AxPROT[2] signal always being 1 making all transactions appear as instructions. Google Tensor G5 (Laguna) is an example of an SoC with this silicon erratum. The DT property can be specified to enable a software workaround which overrides the incoming attribute to data. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring (Arm) Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 82957334bea2..3c044e4f03d4 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -83,6 +83,16 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. + arm,instdata-override: + type: boolean + description: + Some SoCs like Google Tensor G5 (Laguna) have an SMMU integration + silicon erratum where AxPROT[2] signal is always 1, making all + transactions appear as instructions. + + This property enables a software workaround to override the + instruction/data attribute of incoming traffic to data. + allOf: - if: not: -- cgit v1.2.3