From 538321bd97188563d739e28a2f21ad874bd28b2e Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 6 Oct 2016 00:31:30 +0300 Subject: ARM: shmobile: r8a7743: add power domain index macros Add macros usable by the device tree sources to reference R8A7743 SYSC power domains by index. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- include/dt-bindings/power/r8a7743-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/r8a7743-sysc.h diff --git a/include/dt-bindings/power/r8a7743-sysc.h b/include/dt-bindings/power/r8a7743-sysc.h new file mode 100644 index 000000000000..61cfbb2907ea --- /dev/null +++ b/include/dt-bindings/power/r8a7743-sysc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7743_PD_CA15_CPU0 0 +#define R8A7743_PD_CA15_CPU1 1 +#define R8A7743_PD_CA15_SCU 12 +#define R8A7743_PD_SGX 20 + +/* Always-on power area */ +#define R8A7743_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */ -- cgit v1.2.3 From 97ca8402997cd2aa6faaa9cd1e59ec3556d8948c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 5 Nov 2016 00:44:43 +0300 Subject: ARM: shmobile: r8a7745: add power domain index macros Add macros usable by the device tree sources to reference R8A7745 SYSC power domains by index. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- include/dt-bindings/power/r8a7745-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/r8a7745-sysc.h diff --git a/include/dt-bindings/power/r8a7745-sysc.h b/include/dt-bindings/power/r8a7745-sysc.h new file mode 100644 index 000000000000..1844c1171c04 --- /dev/null +++ b/include/dt-bindings/power/r8a7745-sysc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7745_PD_CA7_CPU0 5 +#define R8A7745_PD_CA7_CPU1 6 +#define R8A7745_PD_SGX 20 +#define R8A7745_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A7745_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */ -- cgit v1.2.3 From 5591aa4249436615b12ed980a457840f886656f9 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 3 Nov 2016 20:34:46 +0100 Subject: ARM: dts: alt: Fix PFC names for DU Update the PFC pin groups and function names of DU interface for r8a7794 ALT board. The currently specified pin groups and function names prevented PFC and DU interfaces from being correctly configured: sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table rcar-du: probe of feb00000.display failed with error -22 Signed-off-by: Jacopo Mondi Acked-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 325d3f972c57..a3e74684289b 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -165,8 +165,8 @@ pinctrl-names = "default"; du_pins: du { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; - function = "du"; + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; + function = "du1"; }; scif2_pins: scif2 { -- cgit v1.2.3 From dc8ee9dbdba509fb58e23ba79f2e6059fe5d8b3b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 Nov 2016 20:07:07 +0100 Subject: ARM: dts: r8a7794: Correct hsusb parent clock The parent clock of the HSUSB clock is the HP clock, not the MP clock. Fixes: c7bab9f929e51761 ("ARM: shmobile: r8a7794: Add USB clocks to device tree") Signed-off-by: Geert Uytterhoeven Acked-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 01816ac775a8..7d9f0601d3ca 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1262,7 +1262,7 @@ mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&mp_clk>, + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>; -- cgit v1.2.3 From 24b2d930a50662c11918fd0c22931f1448488da4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 Nov 2016 20:10:04 +0100 Subject: ARM: dts: r8a7794: Use SYSC "always-on" PM Domain for sound Hook up the Audio-DMAC and sound device nodes to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Cfr. commit 0761ff2ad0c581f3 ("ARM: dts: r8a7794: Add SYSC PM Domains"). Fixes: 320d6c5a08a4abd3 ("ARM: dts: r8a7794: add sound support") Fixes: 298e4ee3d213a076 ("ARM: dts: r8a7794: add Audio-DMAC support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7d9f0601d3ca..364b4aa8d1c1 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -319,7 +319,7 @@ "ch12"; clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; clock-names = "fck"; - power-domains = <&cpg_clocks>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #dma-cells = <1>; dma-channels = <13>; }; @@ -1485,7 +1485,7 @@ "mix.0", "mix.1", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&cpg_clocks>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; -- cgit v1.2.3 From 1e26fcf31c5c70557689184185913881e4557bc0 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Sun, 6 Nov 2016 21:20:19 +0100 Subject: ARM: dts: lager: rename and reindex i2cexio The rename from i2cexio to i2cexio0 is in preparation for adding i2cexio1 which will use the demuxer for IIC1/I2C1. The reindexing from i2c8 to i2c10 is to allow space for grouping of additional GPIO buses to be added by follow-up patches to support demuxing of other i2c buses. Also note that fallback to GPIO is not provided by the hardware for IIC0/I2C0. Signed-off-by: Simon Horman [wsa: rebased, fixed alias and removed typo in commit message] Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/r8a7790-lager.dts | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 434268262d88..5645444cd21a 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -50,7 +50,7 @@ aliases { serial0 = &scif0; serial1 = &scifa1; - i2c8 = "i2cexio"; + i2c10 = &i2cexio0; }; chosen { @@ -273,11 +273,13 @@ * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and * instantiate the slave device at runtime according to the documentation. * You can then communicate with the slave via IIC3. + * + * IIC0/I2C0 does not appear to support fallback to GPIO. */ - i2cexio: i2c-8 { + i2cexio0: i2c-10 { compatible = "i2c-demux-pinctrl"; i2c-parent = <&iic0>, <&i2c0>; - i2c-bus-name = "i2c-exio"; + i2c-bus-name = "i2c-exio0"; #address-cells = <1>; #size-cells = <0>; }; @@ -596,12 +598,12 @@ &i2c0 { pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "i2c-exio"; + pinctrl-names = "i2c-exio0"; }; &iic0 { pinctrl-0 = <&iic0_pins>; - pinctrl-names = "i2c-exio"; + pinctrl-names = "i2c-exio0"; }; &iic1 { -- cgit v1.2.3 From b2f15ca697a11c8df64ac6c8086ababc5c9e6060 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Sun, 6 Nov 2016 21:20:20 +0100 Subject: ARM: dts: lager: use demuxer for IIC1/I2C1 Make it possible to select which I2C1 IP core you want to run on the EXIO-A connector. This is based on reference work for the I2C0 core of the lager board by Wolfram Sang. Signed-off-by: Simon Horman [wsa: rebased and fixed aliases] Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/r8a7790-lager.dts | 39 +++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 5645444cd21a..9b9748548702 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -50,7 +50,9 @@ aliases { serial0 = &scif0; serial1 = &scifa1; + i2c8 = &gpioi2c1; i2c10 = &i2cexio0; + i2c11 = &i2cexio1; }; chosen { @@ -265,6 +267,17 @@ clock-frequency = <148500000>; }; + gpioi2c1: i2c-8 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */ + &gpio1 16 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + /* * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. * We use the I2C demuxer, so the desired IP core can be selected at runtime @@ -283,6 +296,19 @@ #address-cells = <1>; #size-cells = <0>; }; + + /* + * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). + * This is similar to the arangement described for i2cexio0 (above) + * with a fallback to GPIO also provided. + */ + i2cexio1: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-exio1"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -405,6 +431,11 @@ function = "iic0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + iic1_pins: iic1 { groups = "iic1"; function = "iic1"; @@ -606,10 +637,14 @@ pinctrl-names = "i2c-exio0"; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-exio1"; +}; + &iic1 { - status = "okay"; pinctrl-0 = <&iic1_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-exio1"; }; &iic2 { -- cgit v1.2.3 From 6723438b3b98ba8434655fa13fc6d5153f70ee98 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Sun, 6 Nov 2016 21:20:23 +0100 Subject: ARM: dts: koelsch: use demuxer for I2C1 Make it possible to fallback to GPIO for I2C1 on the EXIO-C connector. This is based on reference work for the I2C0 core of the lager/r8a7790 by Wolfram Sang. Signed-off-by: Simon Horman [wsa: rebased and fixed aliases] Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/r8a7791-koelsch.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index c457b43deb7d..d5c80e6bff22 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -50,6 +50,8 @@ aliases { serial0 = &scif0; serial1 = &scif1; + i2c9 = &gpioi2c1; + i2c12 = &i2cexio1; }; chosen { @@ -298,6 +300,29 @@ #clock-cells = <0>; clock-frequency = <148500000>; }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */ + &gpio7 15 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + + /* + * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio1: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-exio1"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -333,6 +358,11 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + i2c2_pins: i2c2 { groups = "i2c2"; function = "i2c2"; @@ -581,6 +611,11 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-exio1"; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From e60a19f03cdb5a16fdad72d0776a1ede10fd2a57 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Sun, 6 Nov 2016 21:20:30 +0100 Subject: ARM: dts: alt: use demuxer for I2C4 Make it possible to fallback to GPIO for I2C4 on the EXIO-B connector. This is based on reference work for the I2C0 core of the lager/r8a7790 by Wolfram Sang. Signed-off-by: Simon Horman [wsa: rebased and fixed aliases] Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/r8a7794-alt.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index a3e74684289b..7270d4224b1a 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -18,6 +18,8 @@ aliases { serial0 = &scif2; + i2c10 = &gpioi2c4; + i2c12 = &i2cexio4; }; chosen { @@ -135,6 +137,29 @@ #clock-cells = <0>; clock-frequency = <148500000>; }; + + gpioi2c4: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ + &gpio4 8 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + + /* + * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-14 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -194,6 +219,11 @@ function = "i2c1"; }; + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + vin0_pins: vin0 { groups = "vin0_data8", "vin0_clk"; function = "vin0"; @@ -314,6 +344,11 @@ }; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + &vin0 { status = "okay"; pinctrl-0 = <&vin0_pins>; -- cgit v1.2.3 From dcc2fe783d5338125214335b7168623a4b81adbb Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 3 Nov 2016 16:07:23 +0100 Subject: ARM: dts: lager: Enable UHS-I SDR-104 Add the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang --- arch/arm/boot/dts/r8a7790-lager.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 9b9748548702..bd512c86e852 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -608,6 +608,7 @@ vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; -- cgit v1.2.3 From 0726729a4c6882086fe0db150a4dd0493f15dea3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 3 Nov 2016 16:07:24 +0100 Subject: ARM: dts: koelsch: Enable UHS-I SDR-104 And the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/r8a7791-koelsch.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index d5c80e6bff22..5405d337d744 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -529,6 +529,7 @@ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; -- cgit v1.2.3 From f9f2fc0b8d659158cafa95df4ca1d38b1c081d94 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 3 Nov 2016 16:07:25 +0100 Subject: ARM: dts: alt: Enable UHS-I SDR-104 And the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/r8a7794-alt.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 7270d4224b1a..569e3f0e97a5 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -307,6 +307,7 @@ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; -- cgit v1.2.3 From 34e8d993a68ae459ad98c27afc07647e439deacc Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 31 Oct 2016 22:54:01 +0300 Subject: ARM: dts: r8a7743: initial SoC device tree The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7743.dtsi diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi new file mode 100644 index 000000000000..db9cb41be79b --- /dev/null +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; -- cgit v1.2.3 From 6ed5ed500a5c67eed7b76e5353f7bca3b3daae92 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 31 Oct 2016 22:54:50 +0300 Subject: ARM: dts: r8a7743: add SYS-DMAC support Describe SYS-DMAC0/1 in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index db9cb41be79b..4807b08a3541 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -93,6 +93,70 @@ compatible = "renesas,r8a7743-rst"; reg = <0 0xe6160000 0 0x100>; }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; }; /* External root clock */ -- cgit v1.2.3 From 809c01342691469456489bbe87d2d79ed9638631 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 31 Oct 2016 22:55:39 +0300 Subject: ARM: dts: r8a7743: add [H]SCIF{A|B} support Describe [H]SCIF{|A|B} ports in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven [simon: consistently use tabs for indentation] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 4807b08a3541..874bcf2b4da6 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -157,6 +157,267 @@ #dma-cells = <1>; dma-channels = <15>; }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; }; /* External root clock */ -- cgit v1.2.3 From 75f97fb45e6297e3fbaf837fc30850cf724c8f83 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 31 Oct 2016 22:56:36 +0300 Subject: ARM: dts: r8a7743: add Ether support Define the generic R8A7743 part of the Ether device node. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 874bcf2b4da6..87563a5379b5 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -418,6 +418,18 @@ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; status = "disabled"; }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; /* External root clock */ -- cgit v1.2.3 From ef0ca50774495c4ca4d1211252c8ee5af5136187 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 31 Oct 2016 22:58:12 +0300 Subject: ARM: dts: r8a7743: add IRQC support Describe the IRQC interrupt controller in the R8A7743 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 87563a5379b5..216cb1f37f87 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -62,6 +62,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = Date: Mon, 31 Oct 2016 22:59:03 +0300 Subject: ARM: dts: sk-rzg1m: initial device tree Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index befcd2619902..f83ea57c97f9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -677,6 +677,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts new file mode 100644 index 000000000000..ed26961c9434 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -0,0 +1,44 @@ +/* + * Device Tree Source for the SK-RZG1M board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743.dtsi" + +/ { + model = "SK-RZG1M"; + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; -- cgit v1.2.3 From d05ab65b1d0b7fdd0f25439a3bf234324a419d94 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 31 Oct 2016 23:00:03 +0300 Subject: ARM: dts: sk-rzg1m: add Ether support Define the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts index ed26961c9434..3a22538208f2 100644 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -42,3 +42,16 @@ &scif0 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; -- cgit v1.2.3 From c95360247bdd67d39b55f7e743153efa64e4efe3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 5 Nov 2016 00:53:38 +0300 Subject: ARM: dts: r8a7745: initial SoC device tree The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7745.dtsi diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi new file mode 100644 index 000000000000..fbf72ddd82b7 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for the r8a7745 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7745"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; + power-domains = <&sysc R8A7745_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA7: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7745_PD_CA7_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7745-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7745-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7745-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; -- cgit v1.2.3 From 06a80bad04291b6e305ef521550581d62b4656a3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 5 Nov 2016 00:54:51 +0300 Subject: ARM: dts: r8a7745: add SYS-DMAC support Describe SYS-DMAC0/1 in the R8A7745 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index fbf72ddd82b7..437c5ad933d1 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -93,6 +93,70 @@ compatible = "renesas,r8a7745-rst"; reg = <0 0xe6160000 0 0x100>; }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; }; /* External root clock */ -- cgit v1.2.3 From e0d2da54c4d01ba27a4f50c9da94f7a011c6056b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 5 Nov 2016 00:55:52 +0300 Subject: ARM: dts: r8a7745: add [H]SCIF{|A|B} support Describe [H]SCIF{|A|B} ports in the R8A7745 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven [simon: consistently use tabs for indentation] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 437c5ad933d1..99ccdd0d3014 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -157,6 +157,267 @@ #dma-cells = <1>; dma-channels = <15>; }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; }; /* External root clock */ -- cgit v1.2.3 From bed98a59b62d3e121da2d8372425fd4e424b0aa6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 4 Nov 2016 14:57:01 -0700 Subject: ARM: dts: r8a7745: add Ether support Define the generic R8A7745 part of the Ether device node. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 99ccdd0d3014..6fe48157f906 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -418,6 +418,18 @@ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; status = "disabled"; }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7745"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; /* External root clock */ -- cgit v1.2.3 From 28c43fbb3ca0a9a8f547aece94dac8d791358444 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 5 Nov 2016 00:59:37 +0300 Subject: ARM: dts: r8a7745: add IRQC support Describe the IRQC interrupt controller in the R8A7745 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 6fe48157f906..0b2e2f37150f 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -62,6 +62,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = Date: Sat, 5 Nov 2016 01:04:32 +0300 Subject: ARM: dts: sk-rzg1e: initial device tree Add the initial device tree for the R8A7745 SoC based SK-RZG1E board. The board has 1 debug serial port (SCIF2); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 ++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7745-sk-rzg1e.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f83ea57c97f9..6f8cd1436ee8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts new file mode 100644 index 000000000000..667ec4b259d5 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -0,0 +1,39 @@ +/* + * Device Tree Source for the SK-RZG1E board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745.dtsi" + +/ { + model = "SK-RZG1E"; + compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif2 { + status = "okay"; +}; -- cgit v1.2.3 From 6b334366e63678c777367002eb87c297a10d2751 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 5 Nov 2016 01:05:28 +0300 Subject: ARM: dts: sk-rzg1e: add Ether support Define the SK-RZG1E board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index 667ec4b259d5..97840b340197 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -37,3 +37,16 @@ &scif2 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; -- cgit v1.2.3 From f02703320698bf60c81c8b74aeed1e64442f29c5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:09 +0100 Subject: ARM: dts: r8a73a4: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index ca8672778fe0..53183ffe04c1 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -751,6 +751,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; -- cgit v1.2.3 From 9ba368e2226e949e42596cc6027854656f6216a2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:10 +0100 Subject: ARM: dts: r8a7779: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 3005308a1807..9d3bb74bd3f6 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -590,6 +590,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0xff000044 4>; + }; + sysc: system-controller@ffd85000 { compatible = "renesas,r8a7779-sysc"; reg = <0xffd85000 0x0200>; -- cgit v1.2.3 From 328f39b84d4312f3bbc390524f6c6e8be5852500 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:11 +0100 Subject: ARM: dts: r8a7790: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index a946474be9cf..f554ef3c8096 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1471,6 +1471,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7790-sysc"; reg = <0 0xe6180000 0 0x0200>; -- cgit v1.2.3 From 366cd112025838fbbb1be73b7efd7f70bed33b65 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:12 +0100 Subject: ARM: dts: r8a7791: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 091d7fb6ee7d..4c50de2faef1 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1485,6 +1485,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7791-sysc"; reg = <0 0xe6180000 0 0x0200>; -- cgit v1.2.3 From 7cbae74e641761ed117a5a8d903b97a9892a2426 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:13 +0100 Subject: ARM: dts: r8a7792: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index a75e0cd312c5..69789020cf39 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -120,6 +120,11 @@ IRQ_TYPE_LEVEL_LOW)>; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7792-sysc"; reg = <0 0xe6180000 0 0x0200>; -- cgit v1.2.3 From c832999d3af2a9229c1c518997963def42fbaf4b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:14 +0100 Subject: ARM: dts: r8a7793: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 629d3d60d1cd..a377dda17724 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1306,6 +1306,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7793-sysc"; reg = <0 0xe6180000 0 0x0200>; -- cgit v1.2.3 From 2357adb625f15e7f2b05a1464076c79876563636 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:15 +0100 Subject: ARM: dts: r8a7794: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 364b4aa8d1c1..63dc7f29d216 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1377,6 +1377,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7794-sysc"; reg = <0 0xe6180000 0 0x0200>; -- cgit v1.2.3