From a96d6877756d575c02c83f510c74c081b854bb87 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Mon, 11 May 2020 13:21:15 +0800 Subject: MLK-24012-06 arm64: dts: add imx8m pcie ep support Add the PCIe EP mode on iMX8MQ/MM/MP platforms. And enable the EP mode on EVK boards. Signed-off-by: Richard Zhu Reviewed-by: Fugang Duan --- arch/arm64/boot/dts/freescale/Makefile | 5 +++-- .../boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts | 16 +++++++++++++++ .../boot/dts/freescale/imx8mm-evk-pcie-ep.dts | 16 +++++++++++++++ arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 12 +++++++++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 21 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-evk-pcie-ep.dts | 16 +++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 16 +++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 24 ++++++++++++++++++++++ .../boot/dts/freescale/imx8mq-evk-pcie-ep.dts | 20 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 11 ++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 +++++++++++++++++ 11 files changed, 174 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b99bcde5396b..3d6fc7b12413 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191 imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \ imx8mm-ddr4-evk-rm67191.dtb imx8mm-evk-revb.dtb imx8mm-ddr4-evk-revb.dtb \ imx8mm-ddr4-evk-revb-rm67191.dtb imx8mm-ddr3l-val.dtb \ + imx8mm-evk-pcie-ep.dtb imx8mm-ddr4-evk-pcie-ep.dtb \ imx8mm-evk-usd-wifi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb @@ -64,9 +65,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ab2.dtb imx8mn-ddr4-ab2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-rpmsg.dtb \ imx8mp-evk-rm67191.dtb imx8mp-evk-flexcan2.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \ imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \ - imx8mp-evk-dsp.dtb imx8mp-evk-ov2775.dtb imx8mp-evk-basler.dtb + imx8mp-evk-dsp.dtb imx8mp-evk-ov2775.dtb imx8mp-evk-basler.dtb imx8mp-evk-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ - imx8mq-evk-usdhc2-m2.dtb + imx8mq-evk-usdhc2-m2.dtb imx8mq-evk-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67191.dtb imx8mq-evk-lcdif-adv7535.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts new file mode 100644 index 000000000000..da61f5b76d26 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts new file mode 100644 index 000000000000..2f96420e3230 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 50487c7f49cd..bdf343f99e7e 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -232,6 +232,18 @@ status = "okay"; }; +&pcie0_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + ext_osc = <1>; + status = "disabled"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 43bd59015f06..0247ff9b25cf 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1304,6 +1304,27 @@ status = "disabled"; }; + pcie0_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x000400000>, + <0x18000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts new file mode 100644 index 000000000000..3ed4f2121e5a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index cf1232b032c9..b03ad0dee82c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -664,6 +664,22 @@ status = "okay"; }; +&pcie_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + ext_osc = <0>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_PCIE_PHY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "disabled"; +}; + &pcie_phy{ status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a3e96d52aa9e..9175639d6e45 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1950,6 +1950,30 @@ status = "disabled"; }; + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x0 0x33800000 0x0 0x000400000>, + <0x0 0x18000000 0x0 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu_3d: gpu3d@38000000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x38000000 0x0 0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts new file mode 100644 index 000000000000..7534041490c7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&pcie1_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e211234e80ff..b757c95e3cef 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -639,6 +639,17 @@ status = "okay"; }; +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "disabled"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5943d2ed653d..51d2d3a2830b 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1466,6 +1466,25 @@ status = "disabled"; }; + pcie1_ep: pcie_ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ -- cgit v1.2.3