From 2c8613ec65f47f745bcab346f7637817f47b157f Mon Sep 17 00:00:00 2001 From: Han Gao Date: Thu, 1 Oct 2026 15:44:10 +0800 Subject: dt-bindings: riscv: thead: add Milk-V Meles Document the Milk-V Meles board compatible with the TH1520 fallback. Signed-off-by: Han Gao Acked-by: Conor Dooley Reviewed-by: Drew Fustini Link: https://patch.msgid.link/20261001-rv-meles-v2-1-c61052262f84@iscas.ac.cn Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/thead.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml index 301912dcd290..e8170915f4d6 100644 --- a/Documentation/devicetree/bindings/riscv/thead.yaml +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -17,9 +17,11 @@ properties: const: '/' compatible: oneOf: - - description: BeagleV Ahead single board computer + - description: TH1520 single board computers items: - - const: beagle,beaglev-ahead + - enum: + - beagle,beaglev-ahead + - milkv,meles - const: thead,th1520 - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A items: -- cgit v1.2.3 From 8360e1bcc246d4c44b7308ba5c7a25255de3ba55 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Thu, 1 Oct 2026 15:44:11 +0800 Subject: riscv: dts: thead: add Milk-V Meles Add the Milk-V Meles board with UART0, eMMC, SD, Ethernet and the PWM2 fan. Describe the board pin assignments and the PHY on the GMAC0 MDIO bus. Give GPIO banks aliases and name the exposed 40-pin header lines. The eMMC I/O supply is fixed at 1.8 V. Enable DDR52 at that voltage and retain the 52 MHz board limit. Describe 8 GiB as the default memory size; firmware updates it to match the detected RAM capacity. Reviewed-by: Drew Fustini Signed-off-by: Han Gao Link: https://patch.msgid.link/20261001-rv-meles-v2-2-c61052262f84@iscas.ac.cn Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/Makefile | 1 + arch/riscv/boot/dts/thead/th1520-milkv-meles.dts | 227 +++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/th1520-milkv-meles.dts diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile index b55a17127c2b..25f7fe068368 100644 --- a/arch/riscv/boot/dts/thead/Makefile +++ b/arch/riscv/boot/dts/thead/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb +dtb-$(CONFIG_ARCH_THEAD) += th1520-milkv-meles.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts b/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts new file mode 100644 index 000000000000..371404719078 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021-2022 Alibaba Group Holding Limited. + * Copyright (C) 2026 Han Gao + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Milk-V Meles"; + compatible = "milkv,meles", "thead,th1520"; + + aliases { + ethernet0 = &gmac0; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &aogpio; + mmc0 = &emmc; + mmc1 = &sdio0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x0>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&fan_pins>; + pwms = <&pwm 2 10000000 0>; + cooling-levels = <0 64 192 255>; + #cooling-cells = <2>; + }; +}; + +/* Names follow the 40-pin header signal labels. */ +&aogpio { + gpio-line-names = "", "", "", "", "", "", "", "AOGPIO_7", + "AOGPIO_8", "", "AOGPIO_10", "AOGPIO_11"; +}; + +&emmc { + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +&gmac0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "", "", "", "GPIO0_8", + "GPIO0_9", "GPIO0_10", "GPIO0_11", "", "", "", + "", "GPIO0_16", "GPIO0_17"; +}; + +&gpio2 { + gpio-line-names = "GPIO2_0", "GPIO2_1", "", "", "", "", "", "", + "", "", "", "GPIO2_11", "GPIO2_12", "", + "GPIO2_14", "GPIO2_15", "GPIO2_16", "GPIO2_17", + "", "", "", "", "GPIO2_22", "GPIO2_23", + "GPIO2_24", "GPIO2_25", "", "", "", "", "", + "GPIO2_31"; +}; + +&gpio3 { + gpio-line-names = "GPIO3_0", "GPIO3_1", "GPIO3_2", "GPIO3_3"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&padctrl0_apsys { + fan_pins: fan-0 { + pwm2-pins { + pins = "QSPI0_CSN1"; + function = "pwm"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + gmac0_pins: gmac0-0 { + tx-pins { + pins = "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + mdio0_pins: mdio0-0 { + mdc-pins { + pins = "GMAC0_MDC"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mdio-pins { + pins = "GMAC0_MDIO"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + sdio0_pins: sdio0-0 { + detn-pins { + pins = "SDIO0_DETN"; + function = "sdio"; + bias-disable; /* external pull-up */ + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + +&sdio0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_pins>; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + no-sdio; + + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; -- cgit v1.2.3 From a7f2539005c43f94ea5a931f8ab534488b335880 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Thu, 1 Oct 2026 15:44:12 +0800 Subject: riscv: dts: thead: enable AP6256 Wi-Fi on Milk-V Meles Connect AP6256 to SDIO1 with its fixed supplies and PMIC LPO clock. Use GPIO0_20 for WL_REG_ON and GPIO0_21 for the host-wake interrupt. Keep GPIO1_24 low to select the external antenna by default. Use the existing BCM43456 binding and the 198 MHz board limit. Keep module power during suspend and assign mmc2 to SDIO1. Reviewed-by: Drew Fustini Signed-off-by: Han Gao Link: https://patch.msgid.link/20261001-rv-meles-v2-3-c61052262f84@iscas.ac.cn Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-milkv-meles.dts | 94 ++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts b/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts index 371404719078..bb1be3775690 100644 --- a/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts +++ b/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "th1520.dtsi" +#include / { model = "Milk-V Meles"; @@ -22,6 +23,7 @@ gpio5 = &aogpio; mmc0 = &emmc; mmc1 = &sdio0; + mmc2 = &sdio1; serial0 = &uart0; }; @@ -29,6 +31,13 @@ stdout-path = "serial0:115200n8"; }; + wifi_32k: clock-wifi-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + /* The module LPO input is supplied by PMIC_32K_OUT. */ + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x2 0x0>; @@ -42,6 +51,30 @@ cooling-levels = <0 64 192 255>; #cooling-cells = <2>; }; + + wifi_vbat: regulator-wifi-vbat { + compatible = "regulator-fixed"; + regulator-name = "WIFI_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wifi_vddio: regulator-wifi-vddio { + compatible = "regulator-fixed"; + regulator-name = "WIFI_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_pins>; + reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <50>; + }; }; /* Names follow the 40-pin header signal labels. */ @@ -77,6 +110,16 @@ "", "GPIO0_16", "GPIO0_17"; }; +&gpio1 { + /* GPIO1_24 low selects the external antenna through U39. */ + wifi-antenna-select-hog { + gpio-hog; + gpios = <24 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "wifi-external-antenna"; + }; +}; + &gpio2 { gpio-line-names = "GPIO2_0", "GPIO2_1", "", "", "", "", "", "", "", "", "", "GPIO2_11", "GPIO2_12", "", @@ -206,6 +249,27 @@ }; }; +&padctrl1_apsys { + wifi_enable_pins: wifi-enable-0 { + gpio-pins { + pins = "GPIO0_20"; + bias-disable; + drive-strength = <7>; + input-disable; + }; + }; + + wifi_host_wake_pins: wifi-host-wake-0 { + gpio-pins { + pins = "GPIO0_21"; + function = "gpio"; + bias-disable; + input-enable; + input-schmitt-enable; + }; + }; +}; + &sdio0 { pinctrl-names = "default"; pinctrl-0 = <&sdio0_pins>; @@ -219,6 +283,36 @@ status = "okay"; }; +&sdio1 { + bus-width = <4>; + max-frequency = <198000000>; + cap-sd-highspeed; + cap-sdio-irq; + non-removable; + no-sd; + no-mmc; + keep-power-in-suspend; + vmmc-supply = <&wifi_vbat>; + vqmmc-supply = <&wifi_vddio>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + clocks = <&wifi_32k>; + clock-names = "lpo"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_pins>; + interrupt-parent = <&gpio0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; -- cgit v1.2.3 From d43b33e0253cf9dea8d5f2502db2175f2fde779a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Thu, 1 Oct 2026 15:44:13 +0800 Subject: riscv: dts: thead: enable HDMI on Milk-V Meles Enable the DC8200 display controller and DW-HDMI transmitter. Connect the transmitter to the board Type-A HDMI connector with reciprocal graph endpoints. Reviewed-by: Drew Fustini Signed-off-by: Han Gao Link: https://patch.msgid.link/20261001-rv-meles-v2-4-c61052262f84@iscas.ac.cn Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-milkv-meles.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts b/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts index bb1be3775690..1c9de6b37a3e 100644 --- a/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts +++ b/arch/riscv/boot/dts/thead/th1520-milkv-meles.dts @@ -38,6 +38,17 @@ /* The module LPO input is supplied by PMIC_32K_OUT. */ }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x2 0x0>; @@ -83,6 +94,10 @@ "AOGPIO_8", "", "AOGPIO_10", "AOGPIO_11"; }; +&dpu { + status = "okay"; +}; + &emmc { bus-width = <8>; max-frequency = <52000000>; @@ -133,6 +148,16 @@ gpio-line-names = "GPIO3_0", "GPIO3_1", "GPIO3_2", "GPIO3_3"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mdio0 { phy0: ethernet-phy@1 { reg = <1>; -- cgit v1.2.3 From 2414ca8f5a0cafdfdb2b5899fd173adc09b5adf1 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Wed, 30 Sep 2026 10:10:18 -0700 Subject: MAINTAINERS: Move RISC-V T-Head SoC tree to kernel.org Update the T-Head SoC entry to reflect that the branches are hosted on kernel.org. Signed-off-by: Drew Fustini --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3a19da74d00c..7e8b59e1fc18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23619,7 +23619,7 @@ M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained Q: https://patchwork.kernel.org/project/riscv-thead/list/ -T: git https://github.com/pdp7/linux.git +T: git https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml -- cgit v1.2.3