From ca1c054fe0df9da0e4fe828a69e3ed75f9befa7b Mon Sep 17 00:00:00 2001 From: Martin Chi Date: Sat, 28 Jun 2014 10:05:06 +0800 Subject: USB: Phy: tegra: Enable POSTAMBLE_OUTPUT for HSIC As part of Phy power_on the POSTAMBLE_OUTPUT_ENABLE should be set for HSIC. Bug 200008073 Change-Id: I925cd632bcf5b1d10e5390c755d485adf623e745 Signed-off-by: Martin Chi Reviewed-on: http://git-master/r/432201 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Gray Lei Reviewed-by: Suresh Mangipudi --- arch/arm/mach-tegra/tegra11x_usb_phy.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-tegra/tegra11x_usb_phy.c b/arch/arm/mach-tegra/tegra11x_usb_phy.c index c37d5b6ed83d..885ae12f9f08 100644 --- a/arch/arm/mach-tegra/tegra11x_usb_phy.c +++ b/arch/arm/mach-tegra/tegra11x_usb_phy.c @@ -219,6 +219,7 @@ #define UHSIC_TX_CFG0 0xc10 #define UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9) +#define UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 6) #define UHSIC_MISC_CFG0 0xc14 #define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7) @@ -1876,6 +1877,10 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN); writel(val, base + USB_PORTSC); + val = readl(base + UHSIC_TX_CFG0); + val |= UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE; + writel(val, base + UHSIC_TX_CFG0); + val = readl(base + UHSIC_PADS_CFG0); /* Clear RTUNEP SLEWP & SLEWN bit fields */ val &= ~(UHSIC_TX_RTUNEP | UHSIC_TX_SLEWP | UHSIC_TX_SLEWN); -- cgit v1.2.3