From 19648dddb14bdb722e83ab1dc8a54525c9846600 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Mon, 29 Aug 2022 20:52:59 +0200 Subject: clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock() Currently we loop over meson_parm_read() up to 24mln times. This results in a unpredictable timeout period. In my case it's over 5s on a S905X4-based system. Make the timeout period predictable and set it to 100ms. Signed-off-by: Heiner Kallweit Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/a801afc0-a8f2-a0a4-0f2b-a7201351d563@gmail.com --- drivers/clk/meson/clk-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 9e55617bc3b4..f7b59f7389af 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -277,15 +277,15 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - int delay = 24000000; + int delay = 5000; do { - /* Is the clock locked now ? */ + /* Is the clock locked now ? Time out after 100ms. */ if (meson_parm_read(clk->map, &pll->l)) return 0; - delay--; - } while (delay > 0); + udelay(20); + } while (--delay); return -ETIMEDOUT; } -- cgit v1.2.3 From d73406ed2dcfab7d25493ff3a62dd57f0d9c2bf2 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 14 Aug 2022 23:25:31 +0200 Subject: clk: meson: pll: add pcie lock retry workaround The PCIe PLL locking may be unreliable under some circumstance, such as high or low temperature. If the PLL fails to lock, reset it a try again. This helps on the S905X4 Signed-off-by: Heiner Kallweit [commit message amend] Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/cc80cda0-4dda-2e3e-3fc8-afa97717479b@gmail.com --- drivers/clk/meson/clk-pll.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index f7b59f7389af..5dfb7d38f452 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -320,12 +320,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) static int meson_clk_pcie_pll_enable(struct clk_hw *hw) { - meson_clk_pll_init(hw); + int retries = 10; - if (meson_clk_pll_wait_lock(hw)) - return -EIO; + do { + meson_clk_pll_init(hw); + if (!meson_clk_pll_wait_lock(hw)) + return 0; + pr_info("Retry enabling PCIe PLL clock\n"); + } while (--retries); - return 0; + return -EIO; } static int meson_clk_pll_enable(struct clk_hw *hw) -- cgit v1.2.3