From 7fe0d46c5bd13b43d801e10b177a65987a6b1208 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Tue, 23 Feb 2016 13:20:37 +0800 Subject: MLK-12623-01 cpufreq: imx: Add support for 700MHz setpoint in cpufreq On i.MX6UL EVK board, we use a external GPIO DC regulator to control the VDD_ARM_SOC_IN voltage, if default voltage is 1.4V when the system is bootup. Per design team, when the highest setpoint freq is not bigger than 528MHz, we can decrease this regulator voltage to 1.3V. On i.MX6UL TO1.1, we add a 700MHz setpoint. When the highest setpoint freq is 700MHz, the DC regulator should be at 1.4V to to cover the IR drop. Signed-off-by: Bai Ping (cherry picked from commit 0e3293e53f4bd5b122abc250b610dd61850e3ce9) --- drivers/cpufreq/imx6q-cpufreq.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index d9093e14571e..2447a4561410 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -24,6 +24,7 @@ #define DC_VOLTAGE_MAX 1400000 #define FREQ_1P2_GHZ 1200000000 #define FREQ_396_MHZ 396000 +#define FREQ_696_MHZ 696000 static struct regulator *arm_reg; static struct regulator *pu_reg; @@ -50,6 +51,7 @@ static unsigned int transition_latency; static struct mutex set_cpufreq_lock; static u32 *imx6_soc_volt; static u32 soc_opp_count; +static bool ignore_dc_reg; static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) { @@ -140,6 +142,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) clk_set_parent(secondary_sel, pll2_pfd2_396m_clk); clk_set_parent(step_clk, secondary_sel); clk_set_parent(pll1_sw_clk, step_clk); + if (freq_hz > clk_get_rate(pll2_bus)) { + clk_set_rate(pll1, new_freq * 1000); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + } } else { clk_set_parent(step_clk, pll2_pfd2_396m_clk); clk_set_parent(pll1_sw_clk, step_clk); @@ -246,13 +252,13 @@ static int imx6_cpufreq_pm_notify(struct notifier_block *nb, cpufreq_policy_min_pre_suspend = data->user_policy.min; data->user_policy.min = data->user_policy.max; - if (!IS_ERR(dc_reg)) + if (!IS_ERR(dc_reg) && !ignore_dc_reg) regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MAX, 0); break; case PM_POST_SUSPEND: data->user_policy.min = cpufreq_policy_min_pre_suspend; - if (!IS_ERR(dc_reg)) + if (!IS_ERR(dc_reg) && !ignore_dc_reg) regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); break; default: @@ -322,8 +328,6 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) } dc_reg = devm_regulator_get_optional(cpu_dev, "dc"); - if (!IS_ERR(dc_reg)) - regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); /* * soc_reg sync with arm_reg if arm shares the same regulator @@ -365,6 +369,15 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto out_free_opp; } + /* + * On i.MX6UL EVK board, if the SOC is run in overide frequency, + * the dc_regulator voltage should not be touched. + */ + if (freq_table[num - 1].frequency == FREQ_696_MHZ) + ignore_dc_reg = true; + if (!IS_ERR(dc_reg) && !ignore_dc_reg) + regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + /* Make imx6_soc_volt array's size same as arm opp number */ imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); if (imx6_soc_volt == NULL) { -- cgit v1.2.3 From b1d1ba85054b7dd875a2959ec171afdc18af0ca4 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Tue, 23 Feb 2016 13:37:14 +0800 Subject: MLK-12623-02 ARM: dts: imx: Add 700MHz setpoint define in dts According to the latest datasheet(Rev. 0, 12/2015), When the chip is run at LDO enabled mode, the highest setpoint can be set to 700MHz in overdrive mode. Signed-off-by: Bai Ping (cherry picked from commit 9838ff4b9dfaaacdea01b2bf5f54020ccf991f23) --- arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts | 2 ++ arch/arm/boot/dts/imx6ul.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts index 7729da6a0d74..9aba93c81a12 100644 --- a/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts @@ -11,12 +11,14 @@ &cpu0 { operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index af8bcf3cc5a5..5350727a6be3 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -56,12 +56,14 @@ clock-latency = <61036>; /* two CLK32 periods */ operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 -- cgit v1.2.3 From d5d7c02d2fb59de6f61bb0962d08baecdf10c169 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 11 Apr 2016 10:56:40 +0800 Subject: MLK-12623-03 ARM: imx: Add cpu speed grading check for imx6ul In the OCOTP fuse map, the speed grading[1:0] define the MAX CPU speed the chip can run. The detailed definition is below: 2b'00: Reserved; 2b'01: 528000000Hz; 2b'10: 696000000Hz; 2b'11: Reserved; We need to disable the illegal setpoints according to the fuse map. Signed-off-by: Bai Ping (cherry picked from commit 1fc5419ba08a8da302cfcddb0ea76226d7bdc8c3) --- arch/arm/mach-imx/mach-imx6ul.c | 78 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 5dc1feacbeb5..76054ac798b0 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,76 @@ static void __init imx6ul_enet_phy_init(void) phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, ksz8081_phy_fixup); } +#define OCOTP_CFG3 0x440 +#define OCOTP_CFG3_SPEED_SHIFT 16 +#define OCOTP_CFG3_SPEED_696MHZ 0x2 + +static void __init imx6ul_opp_check_speed_grading(struct device *cpu_dev) +{ + struct device_node *np; + void __iomem *base; + u32 val; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); + if (!np) { + pr_warn("failed to find ocotp node\n"); + return; + } + + base = of_iomap(np, 0); + if (!base) { + pr_warn("failed to map ocotp\n"); + goto put_node; + } + + /* + * Speed GRADING[1:0] defines the max speed of ARM: + * 2b'00: Reserved; + * 2b'01: 528000000Hz; + * 2b'10: 700000000Hz; + * 2b'11: Reserved; + * We need to set the max speed of ARM according to fuse map. + */ + val = readl_relaxed(base + OCOTP_CFG3); + val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 0x3; + + if (val != OCOTP_CFG3_SPEED_696MHZ) { + if (dev_pm_opp_disable(cpu_dev, 696000000)) + pr_warn("Failed to disable 696MHz OPP\n"); + } + iounmap(base); + +put_node: + of_node_put(np); +} + +static void __init imx6ul_opp_init(void) +{ + struct device_node *np; + struct device *cpu_dev = get_cpu_device(0); + + if (!cpu_dev) { + pr_warn("failed to get cpu0 device\n"); + return; + } + np = of_node_get(cpu_dev->of_node); + if (!np) { + pr_warn("failed to find cpu0 node\n"); + return; + } + + if (of_init_opp_table(cpu_dev)) { + pr_warn("failed to init OPP table\n"); + goto put_node; + } + + imx6ul_opp_check_speed_grading(cpu_dev); + +put_node: + of_node_put(np); +} + static inline void imx6ul_enet_init(void) { imx6ul_enet_clk_init(); @@ -85,7 +156,10 @@ static void __init imx6ul_init_irq(void) static void __init imx6ul_init_late(void) { - platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { + imx6ul_opp_init(); + platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + } imx6ul_cpuidle_init(); } -- cgit v1.2.3 From 3b2520f17d427b8fa8db37a6d9a4311f20c29036 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 5 Apr 2016 17:43:38 +0800 Subject: MLK-12617 mmc: Fix compile error when CONFIG_MMC=m When CONFIG_MMC=m, compile error shows up ERROR: "of_alias_max_index" [drivers/mmc/core/mmc_core.ko] undefined! ERROR: "mmc_get_reserved_index" [drivers/mmc/card/mmc_block.ko] undefined! ERROR: "mmc_first_nonreserved_index" [drivers/mmc/card/mmc_block.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 make: *** Waiting for unfinished jobs.... This patch export the upper three symbol for module runtime load. Signed-off-by: Haibo Chen --- drivers/mmc/core/core.c | 2 ++ drivers/of/base.c | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 910cc7c61c68..be86d920ab6d 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2831,6 +2831,7 @@ int mmc_first_nonreserved_index(void) { return __mmc_max_reserved_idx + 1; } +EXPORT_SYMBOL(mmc_first_nonreserved_index); /** * mmc_get_reserved_index() - get the index reserved for this host @@ -2842,6 +2843,7 @@ int mmc_get_reserved_index(struct mmc_host *host) { return of_alias_get_id(host->parent->of_node, "mmc"); } +EXPORT_SYMBOL(mmc_get_reserved_index); static void mmc_of_reserve_idx(void) { diff --git a/drivers/of/base.c b/drivers/of/base.c index 169bbafd1ace..ab53ed849158 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1912,6 +1912,7 @@ int of_alias_max_index(const char *stem) return max; } +EXPORT_SYMBOL_GPL(of_alias_max_index); /** * of_alias_scan - Scan all properties of the 'aliases' node -- cgit v1.2.3 From c35a5ddbb9ec3bf5f569b93dad7aa7f1e598c379 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 18 Apr 2016 14:40:47 +0800 Subject: MLK-12671 ARM: imx: support single soc config Need to make sure build pass with single SOC config, in current build for single SOC config, if both SOC_IMX7D and SOC_IMX6SX are NOT selected, below build error will occur, add MU module config to fix this build issue. LD init/built-in.o arch/arm/mach-imx/built-in.o: In function `busfreq_probe': :(.text+0x5370): undefined reference to `imx_mu_lpm_ready' arch/arm/mach-imx/built-in.o: In function `bus_freq_pm_notify': :(.text+0x5d50): undefined reference to `imx_mu_lpm_ready' :(.text+0x5d68): undefined reference to `imx_mu_lpm_ready' make: *** [vmlinux] Error 1 Signed-off-by: Anson Huang --- arch/arm/mach-imx/Kconfig | 5 +++++ arch/arm/mach-imx/Makefile | 5 +++-- arch/arm/mach-imx/common.h | 4 ++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f834eda794fa..dba87a40310d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -69,6 +69,9 @@ config HAVE_IMX_AMP config HAVE_IMX_DDRC bool +config HAVE_IMX_MU + bool + config HAVE_IMX_RPMSG bool @@ -597,6 +600,7 @@ config SOC_IMX6SX select PINCTRL_IMX6SX select HAVE_IMX_AMP select SOC_IMX6 + select HAVE_IMX_MU select HAVE_IMX_RPMSG select RPMSG select IMX_SEMA4 @@ -632,6 +636,7 @@ config SOC_IMX7D select SOC_IMX7 select PCI_DOMAINS if PCI select PINCTRL_IMX7D + select HAVE_IMX_MU select HAVE_IMX_RPMSG select RPMSG select KEYBOARD_SNVS_PWRKEY diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d32d2aae1492..d973b16f99b8 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_HAVE_IMX_GPCV2) += gpcv2.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_DDRC) += ddrc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o +obj-$(CONFIG_HAVE_IMX_MU) += mu.o obj-$(CONFIG_HAVE_IMX_RPMSG) += imx_rpmsg.o ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7)$(CONFIG_SOC_LS1021A),) AFLAGS_headsmp.o :=-Wa,-march=armv7-a @@ -107,10 +108,10 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o lpddr2_freq_imx6.o AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a AFLAGS_lpddr2_freq_imx6sx.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o ddr3_freq_imx6sx.o \ - lpddr2_freq_imx6sx.o mu.o + lpddr2_freq_imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o mach-imx6ul.o ddr3_freq_imx6sx.o \ lpddr2_freq_imx6sx.o -obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o mach-imx7d.o mu.o +obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o mach-imx7d.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index d8d2620f1ac6..3872420981ea 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -91,7 +91,11 @@ void mcc_send_via_mu_buffer(unsigned int index, unsigned int data); bool imx_mu_is_m4_in_low_freq(void); bool imx_mu_is_m4_in_stop(void); void imx_mu_set_m4_run_mode(void); +#ifdef CONFIG_HAVE_IMX_MU int imx_mu_lpm_ready(bool ready); +#else +static inline int imx_mu_lpm_ready(bool ready) { return 0; } +#endif enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ -- cgit v1.2.3 From 92c77573725e7e7715a724f98c7a60bea34f2f9e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 18 Apr 2016 18:00:11 +0800 Subject: MLK-12675 ARM: dts: imx: keep RTC enabled for software poweroff SRTC needs to be kept enabled during system poweroff, SNVS_LP control register bit 0 SRTC_ENV must be set to enable RTC, for software poweroff, kernel just read the register offset and value from dtb and write to SNVS_LP control register to poweroff system, need to make sure bit 0 SRTC_ENV is set to enable RTC during system poweroff. Previous setting did NOT enable it which will cause RTC stop running if using software poweroff. Signed-off-by: Anson Huang --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/imx7d.dtsi | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 777504753370..706d5154d7a0 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2011-2015 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -812,7 +812,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 3caaa50e7ff6..0cca70d71f7f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -679,7 +679,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 521113d65592..3c708f5c76e3 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -809,7 +809,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 5350727a6be3..cdcda7f739f9 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -719,7 +719,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; }; snvs_pwrkey: snvs-powerkey { diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index a6fc3f0bcabe..5727cc0d7f12 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -678,7 +678,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; }; }; -- cgit v1.2.3 From c0433b106001a90f8768835562e18be5459176a5 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 20 Apr 2016 14:00:21 +0800 Subject: MLK-12685 ARM: dts: imx6sx-sabreauto.dts: improve usdhc4 pad drive strength For imx6sx-sabreauto board, the usdhc4 is used for the sd slot locate on the base board, so need to improve the pad drive strength, otherwise we will meet many CRC error or timeout error when insert a sd card. Signed-off-by: Haibo Chen (cherry picked from commit 1cbfce01e4e076d7f7e3b879c2c41d217d8afa48) --- arch/arm/boot/dts/imx6sx-sabreauto.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 3d34439a7505..4ccba96834ed 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -788,14 +788,14 @@ pinctrl_usdhc4: usdhc4grp { fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17071 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17071 /* WP */ >; }; -- cgit v1.2.3 From 36a8f8120721cffaa4d9c4a0adbc34cd7ac8e9fc Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 25 Apr 2016 10:35:37 +0800 Subject: MLK-12705 ARM: imx: add support for i.mx7d TO1.2 busfreq i.MX7D TO1.2 fix the CKE issue, need to follow TO1.0's precedure for DRAM frequency scaling. Signed-off-by: Anson Huang --- arch/arm/mach-imx/ddr3_freq_imx7d.S | 8 ++++---- arch/arm/mach-imx/lpddr3_freq_imx.S | 13 +++++++++---- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-imx/ddr3_freq_imx7d.S b/arch/arm/mach-imx/ddr3_freq_imx7d.S index bc132d3fa837..0a599ed22e3d 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx7d.S +++ b/arch/arm/mach-imx/ddr3_freq_imx7d.S @@ -176,8 +176,8 @@ ldr r7, [r9, #ANADIG_DIGPROG] and r7, r7, #0x11 - cmp r7, #0x10 - beq 20f + cmp r7, #0x11 + bne 20f ldr r7, =0x0 str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] @@ -311,8 +311,8 @@ ldr r7, [r9, #ANADIG_DIGPROG] and r7, r7, #0x11 - cmp r7, #0x10 - beq 22f + cmp r7, #0x11 + bne 22f ldr r7, =0x40404040 str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S index da85b7cee780..5d868bd53f6f 100644 --- a/arch/arm/mach-imx/lpddr3_freq_imx.S +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -187,8 +187,8 @@ ldr r7, [r9, #ANADIG_DIGPROG] and r7, r7, #0x11 - cmp r7, #0x10 - beq 11f + cmp r7, #0x11 + bne 11f ldr r7, =0x0 str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] @@ -247,6 +247,11 @@ ands r8, r8, #0x4 beq 15f + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 14f + ldr r7, =0x08080808 str r7, [r5, #DDRPHY_CA_DSKEW_CON0] str r7, [r5, #DDRPHY_CA_DSKEW_CON1] @@ -258,8 +263,8 @@ 15: ldr r7, [r9, #ANADIG_DIGPROG] and r7, r7, #0x11 - cmp r7, #0x10 - beq 13f + cmp r7, #0x11 + bne 13f ldr r7, =0x1c1c1c1c str r7, [r5, #DDRPHY_CA_DSKEW_CON0] -- cgit v1.2.3 From d60d208e53db28b7db44f8c54399513d611d069d Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 26 Apr 2016 11:21:02 +0800 Subject: MLK-12706-1 mmc: sdio: add sdio reset function for bcmdhd wifi This patch add function sdio_reset_comm() to support bcmdhd wifi dirver build-in type. Signed-off-by: Haibo Chen --- drivers/mmc/core/sdio.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 3b37f9d1af64..9a03630ebb53 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -786,6 +786,37 @@ err: return err; } +int sdio_reset_comm(struct mmc_card *card) +{ + struct mmc_host *host = card->host; + u32 ocr; + u32 rocr; + int err; + + mmc_claim_host(host); + mmc_go_idle(host); + mmc_set_clock(host, host->f_min); + err = mmc_send_io_op_cond(host, 0, &ocr); + if (err) + goto err; + rocr = mmc_select_voltage(host, ocr); + if (!rocr) { + err = -EINVAL; + goto err; + } + err = mmc_sdio_init_card(host, rocr, card, 0); + if (err) + goto err; + mmc_release_host(host); + return 0; +err: + pr_err("%s: Error resetting SDIO communications (%d)\n", + mmc_hostname(host), err); + mmc_release_host(host); + return err; +} +EXPORT_SYMBOL(sdio_reset_comm); + /* * Host is being removed. Free up the current card. */ -- cgit v1.2.3 From b361e5df9d1fd3405ee7cf5ad25d58abf9bdacaf Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 26 Apr 2016 11:08:32 +0800 Subject: MLK-12706-2 net: bcmdhd: set the bcmdhd driver default build in Bcmdhd wifi driver default build as module, now default build in this wifi driver. To support this build in feature, this patch add flag ENABLE_INSMOD_NO_FW_LOAD, and use extern function sdio_reset_comm() as instead. Signed-off-by: Haibo Chen --- drivers/net/wireless/bcmdhd/Makefile | 4 +++- drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c | 7 +------ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/bcmdhd/Makefile b/drivers/net/wireless/bcmdhd/Makefile index e15f5cc1c01f..c3fea8d3d041 100644 --- a/drivers/net/wireless/bcmdhd/Makefile +++ b/drivers/net/wireless/bcmdhd/Makefile @@ -20,6 +20,8 @@ DHDCFLAGS += -DWL_CFG80211 # Print out kernel panic point of file and line info when assertion happened DHDCFLAGS += -DBCMASSERT_LOG +DHDCFLAGS += -DENABLE_INSMOD_NO_FW_LOAD + # keepalive DHDCFLAGS += -DCUSTOM_KEEP_ALIVE_SETTING=28000 @@ -94,7 +96,7 @@ DHDCFLAGS += -DWL_IFACE_COMB_NUM_CHANNELS # m: module type driver # y: built-in type driver ########################## -DRIVER_TYPE ?= m +DRIVER_TYPE ?= y ######################### # Chip dependent feature diff --git a/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c b/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c index d1d71838fcc1..a2ac5c074ff8 100644 --- a/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c +++ b/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c @@ -59,12 +59,7 @@ static void IRQHandler(struct sdio_func *func); static void IRQHandlerF2(struct sdio_func *func); #endif /* !defined(OOB_INTR_ONLY) */ static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr); - -/* workaround to simply return 0 as suggested by Broadcom */ -static int sdio_reset_comm(struct mmc_card *card) -{ - return 0; -} +extern int sdio_reset_comm(struct mmc_card *card); #define DEFAULT_SDIO_F2_BLKSIZE 512 #ifndef CUSTOM_SDIO_F2_BLKSIZE -- cgit v1.2.3 From a90438ea7226cf80f0bf8c02cbec0cc28b64f340 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 26 Apr 2016 12:26:18 +0800 Subject: MLK-12706-3 arm: imx_v7_defconfig: build in bcmdhd Set bcmdhd as build in type. Signed-off-by: Haibo Chen --- arch/arm/configs/imx_v7_defconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 40e35b997ef8..14931e9cd31c 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -144,10 +144,10 @@ CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m -CONFIG_BCMDHD=m +CONFIG_BCMDHD=y CONFIG_BCMDHD_SDIO=y -CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcm/fw_bcmdhd.bin" -CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcm/bcmdhd.cal" +CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcm/ZP_BCM4339/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcm/ZP_BCM4339/bcmdhd.ZP.SDIO.cal" # CONFIG_RTL_CARDS is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y -- cgit v1.2.3 From efb83ff690d80d1e4888e5b6d4891e54ee188e5f Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Wed, 6 Apr 2016 14:11:01 +0800 Subject: MLK-12620 ARM: imx: correct i.MX7D fuse MAC1_ADDR offset address i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d, otherwise read un-correct MAC address. Signed-off-by: Fugang Duan (cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f) --- arch/arm/mach-imx/common.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/common.c b/arch/arm/mach-imx/common.c index b240b449d889..c375cc4f18e2 100644 --- a/arch/arm/mach-imx/common.c +++ b/arch/arm/mach-imx/common.c @@ -14,6 +14,8 @@ #include #include +#include "hardware.h" + unsigned long iram_tlb_base_addr; unsigned long iram_tlb_phys_addr; @@ -37,7 +39,8 @@ void restore_ttbr1(unsigned long ttbr1) ); } -#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10) +#define OCOTP_MAC_OFF (cpu_is_imx7d() ? 0x640 : 0x620) +#define OCOTP_MACn(n) (OCOTP_MAC_OFF + (n) * 0x10) void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat) { struct device_node *ocotp_np, *enet_np, *from = NULL; @@ -47,7 +50,7 @@ void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat u32 macaddr_high = 0; u32 macaddr1_high = 0; u8 *macaddr; - int i; + int i, id; for (i = 0; i < 2; i++) { enet_np = of_find_compatible_node(from, NULL, enet_compat); @@ -59,6 +62,10 @@ void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat if (of_get_mac_address(enet_np)) goto put_enet_node; + id = of_alias_get_id(enet_np, "ethernet"); + if (id < 0) + id = i; + ocotp_np = of_find_compatible_node(NULL, NULL, ocotp_compat); if (!ocotp_np) { pr_warn("failed to find ocotp node\n"); @@ -72,7 +79,7 @@ void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat } macaddr_low = readl_relaxed(base + OCOTP_MACn(1)); - if (i) + if (id) macaddr1_high = readl_relaxed(base + OCOTP_MACn(2)); else macaddr_high = readl_relaxed(base + OCOTP_MACn(0)); @@ -90,7 +97,7 @@ void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat } macaddr = newmac->value; - if (i) { + if (id) { macaddr[5] = (macaddr_low >> 16) & 0xff; macaddr[4] = (macaddr_low >> 24) & 0xff; macaddr[3] = macaddr1_high & 0xff; -- cgit v1.2.3 From d51a5af59374acf15f3251822f8fbc183c8d4aff Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 21 Mar 2016 10:08:11 +0800 Subject: MLK-12464-1: ASoC: fsl: imx-wm8960: Fix no clock after suspend/resume randomly After suspend and resume, the wm8960 codec will change the state from BIAS_OFF to BIAS_ON, in this time, the hw_free is called, the PLL will be diabled, and next instance is started in rapid sequence, hw_params is called But PLL is not enabled, because the bias state is not BIAS_ON. As PLL is disabled in BIAS_ON->BIAS_STANDBY, so don't need to disable pll in hw_free of machine driver. Signed-off-by: Shengjiu Wang (cherry picked from commit 9b6063efd3966266a1a7616c11b818139933497e) --- sound/soc/fsl/imx-wm8960.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/sound/soc/fsl/imx-wm8960.c b/sound/soc/fsl/imx-wm8960.c index 3154679dde32..d65e7765f077 100644 --- a/sound/soc/fsl/imx-wm8960.c +++ b/sound/soc/fsl/imx-wm8960.c @@ -273,9 +273,7 @@ static int imx_hifi_hw_free(struct snd_pcm_substream *substream) data->is_stream_in_use[tx] = false; - /* Power down PLL to save power*/ if (data->is_codec_master && !data->is_stream_in_use[!tx]) { - snd_soc_dai_set_pll(codec_dai, 0, 0, 0, 0); ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF); if (ret) dev_warn(dev, "failed to set codec dai fmt: %d\n", ret); -- cgit v1.2.3 From af2256b286fba98d0c27e330afa24d6c70acf790 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 21 Mar 2016 13:09:26 +0800 Subject: MLK-12464-2: ASoC: wm8960: fix clock is not correct after suspend/resume After the suspend/resume, hw_params may be called in bias_level is not BIAS_ON, then the PLL is not disable/enabled, if the sample rate is changed, the output clock is not correct. Signed-off-by: Shengjiu Wang (cherry picked from commit cced8358c2202824dfdc1780609539655ae5fec5) --- sound/soc/codecs/wm8960.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 1ca4bec38fa3..28eb426a8356 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -761,8 +761,7 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream, wm8960->is_stream_in_use[tx] = true; - if (codec->dapm.bias_level == SND_SOC_BIAS_ON && - !wm8960->is_stream_in_use[!tx]) + if (!wm8960->is_stream_in_use[!tx]) return wm8960_configure_clocking(codec); return 0; @@ -815,10 +814,6 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, } } - ret = wm8960_configure_clocking(codec); - if (ret) - return ret; - /* Set VMID to 2x50k */ snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80); break; -- cgit v1.2.3 From 20de11d2961c84980a8fcecd6ec7c29fd7c5ef3c Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 29 Mar 2016 16:11:51 +0800 Subject: MLK-12607: ASoC: fsl-asrc: Add the support of 12kHz and 24kHz Remove the pre-processing and post-processing table. use proc_autosel() to select proper parameters. Unify the supported input and output rate. Signed-off-by: Shengjiu Wang (cherry picked from commit 8353ec20bd9950ec98d76423c62321a7ea0c7190) --- sound/soc/fsl/fsl_asrc.c | 102 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 70 insertions(+), 32 deletions(-) diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c index 1650fe71a8d8..6d0f42ebfad7 100644 --- a/sound/soc/fsl/fsl_asrc.c +++ b/sound/soc/fsl/fsl_asrc.c @@ -1,7 +1,7 @@ /* * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver * - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * Author: Nicolin Chen * @@ -30,32 +30,15 @@ #define pair_dbg(fmt, ...) \ dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) -/* Sample rates are aligned with that defined in pcm.h file */ -static const u8 process_option[][12][2] = { - /* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */ - {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */ - {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */ - {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */ - {{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */ - {{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */ - {{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */ - {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */ - {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */ - {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */ - {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */ - {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */ - {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */ - {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */ -}; - /* Corresponding to process_option */ -static int supported_input_rate[] = { - 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, - 96000, 176400, 192000, +static unsigned int supported_asrc_rate[] = { + 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, + 64000, 88200, 96000, 128000, 176400, 192000, }; -static int supported_asrc_rate[] = { - 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000, +static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { + .count = ARRAY_SIZE(supported_asrc_rate), + .list = supported_asrc_rate, }; /** @@ -129,6 +112,47 @@ static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) return ret; } +static int proc_autosel(int Fsin, int Fsout, int *pre_proc, int *post_proc) +{ + bool det_out_op2_cond; + bool det_out_op0_cond; + det_out_op2_cond = (((Fsin * 15 > Fsout * 16) & (Fsout < 56000)) | + ((Fsin > 56000) & (Fsout < 56000))); + det_out_op0_cond = (Fsin * 23 < Fsout * 8); + + /* + * Not supported case: Tsout>16.125*Tsin, and Tsout>8.125*Tsin. + */ + if (Fsin * 8 > 129 * Fsout) + *pre_proc = 5; + else if (Fsin * 8 > 65 * Fsout) + *pre_proc = 4; + else if (Fsin * 8 > 33 * Fsout) + *pre_proc = 2; + else if (Fsin * 8 > 15 * Fsout) { + if (Fsin > 152000) + *pre_proc = 2; + else + *pre_proc = 1; + } else if (Fsin < 76000) + *pre_proc = 0; + else if (Fsin > 152000) + *pre_proc = 2; + else + *pre_proc = 1; + + if (det_out_op2_cond) + *post_proc = 2; + else if (det_out_op0_cond) + *post_proc = 0; + else + *post_proc = 1; + + if (*pre_proc == 4 || *pre_proc == 5) + return -EINVAL; + return 0; +} + /** * Release ASRC pair * @@ -244,8 +268,10 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool p2p_in, bool p2 u32 inrate, outrate, indiv, outdiv; u32 clk_index[2], div[2]; int in, out, channels; + int pre_proc, post_proc; struct clk *clk; bool ideal; + int ret; if (!config) { pair_err("invalid pair config\n"); @@ -269,11 +295,11 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool p2p_in, bool p2 ideal = config->inclk == INCLK_NONE; /* Validate input and output sample rates */ - for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) - if (inrate == supported_input_rate[in]) + for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) + if (inrate == supported_asrc_rate[in]) break; - if (in == ARRAY_SIZE(supported_input_rate)) { + if (in == ARRAY_SIZE(supported_asrc_rate)) { pair_err("unsupported input sample rate: %dHz\n", inrate); return -EINVAL; } @@ -388,11 +414,17 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool p2p_in, bool p2 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), ASRCTR_IDR(index) | ASRCTR_USR(index)); + ret = proc_autosel(inrate, outrate, &pre_proc, &post_proc); + if (ret) { + pair_err("No supported pre-processing options\n"); + return ret; + } + /* Apply configurations for pre- and post-processing */ regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), - ASRCFG_PREMOD(index, process_option[in][out][0]) | - ASRCFG_POSTMOD(index, process_option[in][out][1])); + ASRCFG_PREMOD(index, pre_proc) | + ASRCFG_POSTMOD(index, post_proc)); return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); } @@ -564,7 +596,9 @@ static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(cpu_dai); asrc_priv->substream[substream->stream] = substream; - return 0; + + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); } static void fsl_asrc_dai_shutdown(struct snd_pcm_substream *substream, @@ -604,14 +638,18 @@ static struct snd_soc_dai_driver fsl_asrc_dai = { .stream_name = "ASRC-Playback", .channels_min = 1, .channels_max = 10, - .rates = FSL_ASRC_RATES, + .rate_min = 5512, + .rate_max = 192000, + .rates = SNDRV_PCM_RATE_KNOT, .formats = FSL_ASRC_FORMATS, }, .capture = { .stream_name = "ASRC-Capture", .channels_min = 1, .channels_max = 10, - .rates = FSL_ASRC_RATES, + .rate_min = 5512, + .rate_max = 192000, + .rates = SNDRV_PCM_RATE_KNOT, .formats = FSL_ASRC_FORMATS, }, .ops = &fsl_asrc_dai_ops, -- cgit v1.2.3 From deb84cde0da96c5ccccb7e4c1204ad89ee801eca Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 26 Apr 2016 14:38:35 +0800 Subject: MLK-12722: ASoC: fsl_spdif: clear the validity bit for TX Validity bit is set in default, which means the data is not reliable, The receive device may drop this data. So clear it in default, and provide a mixer interface for user to control this bit. Signed-off-by: Shengjiu Wang (cherry picked from commit 48293e6bf7793de01678ee1426cccc9119998ba1) --- sound/soc/fsl/fsl_spdif.c | 66 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 60 insertions(+), 6 deletions(-) diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index bd5ba1f0ba2b..d84784b91c5b 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -1,7 +1,7 @@ /* * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver * - * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. * * Based on stmp3xxx_spdif_dai.c * Vladimir Barinov @@ -748,7 +748,7 @@ static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, } /* Valid bit infomation */ -static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, +static int fsl_spdif_rx_vbit_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; @@ -760,7 +760,7 @@ static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, } /* Get valid good bit from interrupt status register */ -static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol, +static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); @@ -775,6 +775,46 @@ static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol, return 0; } +static int fsl_spdif_tx_vbit_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + + return 0; +} + +static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); + struct regmap *regmap = spdif_priv->regmap; + u32 val; + + regmap_read(regmap, REG_SPDIF_SCR, &val); + val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; + val = 1 - val; + ucontrol->value.integer.value[0] = val; + + return 0; +} + +static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); + struct regmap *regmap = spdif_priv->regmap; + u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; + + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); + + return 0; +} + /* DPLL lock infomation */ static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) @@ -932,11 +972,21 @@ static struct snd_kcontrol_new fsl_spdif_ctrls[] = { /* Valid bit error controller */ { .iface = SNDRV_CTL_ELEM_IFACE_PCM, - .name = "IEC958 V-Bit Errors", + .name = "IEC958 Rx V-Bit Errors", .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, - .info = fsl_spdif_vbit_info, - .get = fsl_spdif_vbit_get, + .info = fsl_spdif_rx_vbit_info, + .get = fsl_spdif_rx_vbit_get, + }, + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "IEC958 Tx V-Bit", + .access = SNDRV_CTL_ELEM_ACCESS_READ | + SNDRV_CTL_ELEM_ACCESS_WRITE | + SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = fsl_spdif_tx_vbit_info, + .get = fsl_spdif_tx_vbit_get, + .put = fsl_spdif_tx_vbit_put, }, /* DPLL lock info get controller */ { @@ -1289,6 +1339,10 @@ static int fsl_spdif_probe(struct platform_device *pdev) spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; + /*Clear the val bit for Tx*/ + regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SCR, + SCR_VAL_MASK, 1 << SCR_VAL_OFFSET); + pm_runtime_enable(&pdev->dev); /* Register with ASoC */ -- cgit v1.2.3 From cf0a95b8d8a189e497dbf1c4102d575c1c827643 Mon Sep 17 00:00:00 2001 From: Teo Hall Date: Thu, 21 Jan 2016 13:36:02 -0600 Subject: MLK-11262-5: ARM: imx: Change A7 MU ready timing Change when A7 signal M4 to make sure busfreq is always up when the M4 send high bus release. This prevents race condition for Low Power Demo Signed-off-by: Teo Hall --- arch/arm/mach-imx/busfreq-imx.c | 8 +++++++- arch/arm/mach-imx/mu.c | 1 - arch/arm/mach-imx/pm-imx7.c | 1 - 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c index 39fe400a48e2..e36b0ffd5cc3 100644 --- a/arch/arm/mach-imx/busfreq-imx.c +++ b/arch/arm/mach-imx/busfreq-imx.c @@ -923,12 +923,16 @@ static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event, mutex_lock(&bus_freq_mutex); if (event == PM_SUSPEND_PREPARE) { + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(false); high_bus_count++; set_high_bus_freq(1); busfreq_suspended = 1; } else if (event == PM_POST_SUSPEND) { busfreq_suspended = 0; high_bus_count--; + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(true); schedule_delayed_work(&bus_freq_daemon, usecs_to_jiffies(5000000)); } @@ -1180,8 +1184,10 @@ static int busfreq_probe(struct platform_device *pdev) high_bus_count++; } - if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) { high_bus_count++; + imx_mu_lpm_ready(true); + } if (err) { dev_err(busfreq_dev, "Busfreq init of ddr controller failed\n"); diff --git a/arch/arm/mach-imx/mu.c b/arch/arm/mach-imx/mu.c index ae502d9f6428..2a482be450ce 100644 --- a/arch/arm/mach-imx/mu.c +++ b/arch/arm/mach-imx/mu.c @@ -388,7 +388,6 @@ static int imx_mu_probe(struct platform_device *pdev) /* enable the bit26(RIE1) of MU_ACR */ writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(26) | BIT(27), mu_base + MU_ACR); - imx_mu_lpm_ready(true); } else { INIT_DELAYED_WORK(&mu_work, mu_work_handler); diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c index 4ce9e6967f77..8057cfb2fed7 100644 --- a/arch/arm/mach-imx/pm-imx7.c +++ b/arch/arm/mach-imx/pm-imx7.c @@ -772,7 +772,6 @@ static int imx7_pm_enter(suspend_state_t state) /* restore M4 to run mode */ imx_mu_set_m4_run_mode(); /* gpc wakeup */ - imx_mu_lpm_ready(true); } } /* clear LPSR resume address */ -- cgit v1.2.3 From 8ad59887532549d3e9fe9158814ca971854ca12a Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 5 May 2016 18:21:10 +0800 Subject: MLK-12761 ARM: imx: add mu as wakeup source for i.mx7d When A7 platform is in low power mode while M4 is NOT, M4 should be able to send message to wake up A7, so MU must be always as wake up source. Signed-off-by: Anson Huang --- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/gpcv2.c | 17 +++++++++++++++++ arch/arm/mach-imx/mu.c | 3 +++ 3 files changed, 22 insertions(+) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 3872420981ea..510fc2bf10f9 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -143,9 +143,11 @@ int imx_gpc_mf_power_on(unsigned int irq, unsigned int on); #ifdef CONFIG_HAVE_IMX_GPCV2 int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on); void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable); #else static inline int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) { return 0; } static inline void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) {} +static void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) {} #endif void __init imx_gpcv2_check_dt(void); void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode); diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index d52578d6a1e1..e2b7ac389251 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -117,6 +117,23 @@ static u32 gpcv2_mf_request_on[IMR_NUM]; static DEFINE_SPINLOCK(gpcv2_lock); static struct notifier_block nb_mipi, nb_pcie; +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = enable ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int idx = d->hwirq / 32; diff --git a/arch/arm/mach-imx/mu.c b/arch/arm/mach-imx/mu.c index 2a482be450ce..c992e586d8bc 100644 --- a/arch/arm/mach-imx/mu.c +++ b/arch/arm/mach-imx/mu.c @@ -388,6 +388,9 @@ static int imx_mu_probe(struct platform_device *pdev) /* enable the bit26(RIE1) of MU_ACR */ writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(26) | BIT(27), mu_base + MU_ACR); + /* MU always as a wakeup source for low power mode */ + imx_gpcv2_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, + true); } else { INIT_DELAYED_WORK(&mu_work, mu_work_handler); -- cgit v1.2.3 From 07184c531e5035e73358ce6bf87483fac78106fa Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 4 May 2016 14:25:35 +0800 Subject: MLK-12748-1 ARM: dts: imx7d: correct usdhc1 cd pin setting i.MX7D 19x19 LPDDR2 ARM2 board's uSDHC1 CD pin should be LOW active, correct it. Signed-off-by: Anson Huang --- arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts b/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts index aa031e040736..2af374c66615 100644 --- a/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts +++ b/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts @@ -444,8 +444,8 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 0>; - wp-gpios = <&gpio5 1 0>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; no-1-8-v; keep-power-in-suspend; enable-sdio-wakeup; -- cgit v1.2.3 From adfc24cc412df58c81b570259d0aa29b6b957649 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 4 May 2016 10:56:40 +0800 Subject: MLK-12748-2 ARM: imx: remove IOMUXC GPR setting for i.mx7d TO1.2 i.MX7D TO1.2 removes the DDR PAD retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang --- arch/arm/mach-imx/suspend-imx7.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index 2b279795be53..7c85a64a8bb7 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -307,9 +307,9 @@ ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] ldr r7, [r11, #ANADIG_DIGPROG] - and r7, r7, #0x11 - cmp r7, #0x10 - beq 10f + and r7, r7, #0xff + cmp r7, #0x11 + bne 10f /* TO 1.1 */ ldr r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] @@ -402,9 +402,9 @@ str r7, [r2, r6] ldr r7, [r1, #ANADIG_DIGPROG] - and r7, r7, #0x11 - cmp r7, #0x10 - beq 12f + and r7, r7, #0xff + cmp r7, #0x11 + bne 12f /* * TKT262940: -- cgit v1.2.3 From a38a53d401de5d583ca8aca8825ef338cee7f33f Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 8 May 2016 14:26:33 +0800 Subject: MLK-12748-3 ARM: imx: adjust imx7d lpddr3 retention exit flow On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. Signed-off-by: Anson Huang --- arch/arm/mach-imx/pm-imx7.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c index 8057cfb2fed7..ab3714225264 100644 --- a/arch/arm/mach-imx/pm-imx7.c +++ b/arch/arm/mach-imx/pm-imx7.c @@ -212,7 +212,7 @@ static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { { 0x1a4, READ_DATA_FROM_HARDWARE }, { 0x1a8, READ_DATA_FROM_HARDWARE }, { 0x64, READ_DATA_FROM_HARDWARE }, - { 0xd0, 0xc0350001 }, + { 0xd0, READ_DATA_FROM_HARDWARE }, { 0xdc, READ_DATA_FROM_HARDWARE }, { 0xe0, READ_DATA_FROM_HARDWARE }, { 0xe4, READ_DATA_FROM_HARDWARE }, @@ -224,6 +224,7 @@ static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { { 0x110, READ_DATA_FROM_HARDWARE }, { 0x114, READ_DATA_FROM_HARDWARE }, { 0x118, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, { 0x11c, READ_DATA_FROM_HARDWARE }, { 0x180, READ_DATA_FROM_HARDWARE }, { 0x184, READ_DATA_FROM_HARDWARE }, @@ -231,9 +232,10 @@ static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { { 0x194, READ_DATA_FROM_HARDWARE }, { 0x200, READ_DATA_FROM_HARDWARE }, { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, { 0x214, READ_DATA_FROM_HARDWARE }, { 0x218, READ_DATA_FROM_HARDWARE }, - { 0x240, 0x06000601 }, + { 0x240, READ_DATA_FROM_HARDWARE }, { 0x244, READ_DATA_FROM_HARDWARE }, }; @@ -242,6 +244,7 @@ static const u32 imx7d_ddrc_phy_lpddr3_setting[][2] __initconst = { { 0x4, READ_DATA_FROM_HARDWARE }, { 0x8, READ_DATA_FROM_HARDWARE }, { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, { 0x1c, READ_DATA_FROM_HARDWARE }, { 0x9c, READ_DATA_FROM_HARDWARE }, { 0x7c, READ_DATA_FROM_HARDWARE }, @@ -266,8 +269,8 @@ static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { { 0x1a4, READ_DATA_FROM_HARDWARE }, { 0x1a8, READ_DATA_FROM_HARDWARE }, { 0x64, READ_DATA_FROM_HARDWARE }, - { 0x490, 0x00000001 }, - { 0xd0, 0xc0020001 }, + { 0x490, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, { 0xd4, READ_DATA_FROM_HARDWARE }, { 0xdc, READ_DATA_FROM_HARDWARE }, { 0xe0, READ_DATA_FROM_HARDWARE }, @@ -279,7 +282,7 @@ static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { { 0x10c, READ_DATA_FROM_HARDWARE }, { 0x110, READ_DATA_FROM_HARDWARE }, { 0x114, READ_DATA_FROM_HARDWARE }, - { 0x120, 0x03030803 }, + { 0x120, READ_DATA_FROM_HARDWARE }, { 0x180, READ_DATA_FROM_HARDWARE }, { 0x190, READ_DATA_FROM_HARDWARE }, { 0x194, READ_DATA_FROM_HARDWARE }, @@ -287,7 +290,7 @@ static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { { 0x204, READ_DATA_FROM_HARDWARE }, { 0x214, READ_DATA_FROM_HARDWARE }, { 0x218, READ_DATA_FROM_HARDWARE }, - { 0x240, 0x06000601 }, + { 0x240, READ_DATA_FROM_HARDWARE }, { 0x244, READ_DATA_FROM_HARDWARE }, }; @@ -295,6 +298,7 @@ static const u32 imx7d_ddrc_phy_ddr3_setting[][2] __initconst = { { 0x0, READ_DATA_FROM_HARDWARE }, { 0x4, READ_DATA_FROM_HARDWARE }, { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, { 0x9c, READ_DATA_FROM_HARDWARE }, { 0x7c, READ_DATA_FROM_HARDWARE }, { 0x80, READ_DATA_FROM_HARDWARE }, @@ -1000,6 +1004,9 @@ static int __init imx7_suspend_init(const struct imx7_pm_socdata *socdata) ddrc_offset_array[i][0]); else pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1]; + + if (pm_info->ddrc_val[i][0] == 0xd0) + pm_info->ddrc_val[i][1] |= 0xc0000000; } /* initialize DDRC PHY settings */ -- cgit v1.2.3 From 07c9f26b19b3ce05719d5634f1f56790b7ecf6af Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 9 May 2016 14:45:14 +0800 Subject: MLK-12765 ARM: imx: make sure DLL is locked on i.MX7D On i.MX7D, per design team's require, need to make sure DLL is locked after DDR frequency scaled done. Although normally there should be no issue, but it is better to add it. Signed-off-by: Anson Huang --- arch/arm/mach-imx/ddr3_freq_imx7d.S | 2 +- arch/arm/mach-imx/lpddr3_freq_imx.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/ddr3_freq_imx7d.S b/arch/arm/mach-imx/ddr3_freq_imx7d.S index 0a599ed22e3d..ff767c08af44 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx7d.S +++ b/arch/arm/mach-imx/ddr3_freq_imx7d.S @@ -291,7 +291,7 @@ ldr r8, =0x9880 str r7, [r2, r8] - ldr r7, =0x02020070 + ldr r7, =0x1010007e str r7, [r5, #DDRPHY_MDLL_CON0] ldr r7, =0x10000008 diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S index 5d868bd53f6f..71b4e231c4b2 100644 --- a/arch/arm/mach-imx/lpddr3_freq_imx.S +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -224,7 +224,7 @@ ldr r8, =0x9880 str r7, [r2, r8] - ldr r7, =0x02020070 + ldr r7, =0x1010007e str r7, [r5, #DDRPHY_MDLL_CON0] ldr r7, =0x10000008 -- cgit v1.2.3 From 9f0881fc0f0bca372bdf84217748c0599ca5c388 Mon Sep 17 00:00:00 2001 From: Andy Duan Date: Wed, 11 May 2016 14:59:09 +0800 Subject: MLK-12763 ARM: imx7d: iomux: correct uart input sel option value GPIO0~GPIO7 part: - Commit(c8cabda5ab07) add some wrong input sel value for uart, return them to origin setting. - Add uart DTE pin mode setting. UART2_TX_DATA pin part: - RM doc "iMX7D_RM_Rev0_Approval.pdf" (2016.04.25 updated in compass) updated input sel define for UART2_RX_DATA, then set the correct input sel for the pin. Signed-off-by: Fugang Duan (cherry picked from commit: 90a8b06b9735dd5b8d2023ff3b95886441e0e8d9) --- arch/arm/boot/dts/imx7d-pinfunc-lpsr.h | 12 ++++++++---- arch/arm/boot/dts/imx7d-pinfunc.h | 2 +- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h index 5dbd0d117811..378694ee05c2 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h +++ b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h @@ -45,26 +45,30 @@ #define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 #define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 #define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 #define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 #define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 #define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 #define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 #define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 #define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 #define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 #define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 #define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 #define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 #define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 #define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 #define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index 43ecaa930a2b..20ed887b6c50 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -543,7 +543,7 @@ #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 #define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 #define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 -- cgit v1.2.3 From c02abe717ed9f9843d2791d04ef41d6260e4e295 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Mon, 22 Feb 2016 18:04:04 +0800 Subject: MLK-12432-01: ov5640 mipi: support more platform and reduce support mode -Support no power and reset pins platform. -Remove specific power and reset pin setting for ov5640 daughter card. -Put sensor in software power down state when streamoff. -Remove unsupported video modes, keep 640x480, 720x480, 720p, 1080p 30fps video modes in driver. Signed-off-by: Sandor Yu (cherry picked from commit 6a6c44e2406dcd9481e3103ca2710a319265c52a) --- drivers/media/platform/mxc/subdev/ov5640_mipi.c | 385 +++--------------------- 1 file changed, 47 insertions(+), 338 deletions(-) diff --git a/drivers/media/platform/mxc/subdev/ov5640_mipi.c b/drivers/media/platform/mxc/subdev/ov5640_mipi.c index 135eefa550a7..ca9156d2c594 100644 --- a/drivers/media/platform/mxc/subdev/ov5640_mipi.c +++ b/drivers/media/platform/mxc/subdev/ov5640_mipi.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -44,15 +44,11 @@ enum ov5640_mode { ov5640_mode_MIN = 0, ov5640_mode_VGA_640_480 = 0, - ov5640_mode_QVGA_320_240 = 1, - ov5640_mode_NTSC_720_480 = 2, - ov5640_mode_PAL_720_576 = 3, - ov5640_mode_720P_1280_720 = 4, - ov5640_mode_1080P_1920_1080 = 5, - ov5640_mode_QSXGA_2592_1944 = 6, - ov5640_mode_QCIF_176_144 = 7, - ov5640_mode_XGA_1024_768 = 8, - ov5640_mode_MAX = 8, + ov5640_mode_NTSC_720_480 = 1, + ov5640_mode_720P_1280_720 = 2, + ov5640_mode_1080P_1920_1080 = 3, + ov5640_mode_QSXGA_2592_1944 = 4, + ov5640_mode_MAX = 5, ov5640_mode_INIT = 0xff, /*only for sensor init*/ }; @@ -212,55 +208,12 @@ static struct reg_value ov5640_init_setting_30fps_VGA[] = { {0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, - {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300}, + {0x3a1f, 0x14, 0, 0}, {0x3008, 0x42, 0, 0}, {0x3c00, 0x04, 0, 300}, }; static struct reg_value ov5640_setting_30fps_VGA_640_480[] = { - - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_VGA_640_480[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { - - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, + {0x3008, 0x42, 0, 0}, + {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -277,117 +230,12 @@ static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, - {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, - {0x380b, 0x00, 0, 0}, {0x3035, 0x12, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3808, 0x04, 0, 0}, - {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; -static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, + {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0x00, 0, 0}, }; static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { + {0x3008, 0x42, 0, 0}, {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, @@ -406,69 +254,7 @@ static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_PAL_720_576[] = { - {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, - {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_PAL_720_576[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, - {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, + {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, }; static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { @@ -494,27 +280,6 @@ static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, }; -static struct reg_value ov5640_setting_15fps_720P_1280_720[] = { - {0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, - {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, - {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, - {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, - {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0}, - {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0}, - {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, - {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, -}; - static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { {0x3008, 0x42, 0, 0}, {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, @@ -552,43 +317,8 @@ static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { {0x3503, 0, 0, 0}, }; -static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = { - {0x3008, 0x42, 0, 0}, - {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0}, - {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, - {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, - {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0}, - {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, - {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0}, - {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0}, - {0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0}, - {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0}, - {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0}, - {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, - {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0}, - {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0}, - {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0}, - {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0}, - {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, - {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, - {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, -}; - static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { + {0x3008, 0x42, 0, 0}, {0x4202, 0x0f, 0, 0}, /* stream off the sensor */ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, /*disable flip*/ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, @@ -608,53 +338,27 @@ static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70}, + {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70}, {0x3008, 0x02, 0, 0}, {0x4202, 0x00, 0, 0}, /* stream on the sensor */ }; static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { { - {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480, - ov5640_setting_15fps_VGA_640_480, - ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)}, - {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240, - ov5640_setting_15fps_QVGA_320_240, - ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)}, - {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480, - ov5640_setting_15fps_NTSC_720_480, - ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)}, - {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576, - ov5640_setting_15fps_PAL_720_576, - ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)}, - {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720, - ov5640_setting_15fps_720P_1280_720, - ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)}, - {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080, - ov5640_setting_15fps_1080P_1920_1080, - ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)}, + {ov5640_mode_VGA_640_480, -1, 0, 0, NULL, 0}, + {ov5640_mode_NTSC_720_480, -1, 0, 0, NULL, 0}, + {ov5640_mode_720P_1280_720, -1, 0, 0, NULL, 0}, + {ov5640_mode_1080P_1920_1080, -1, 0, 0, NULL, 0}, {ov5640_mode_QSXGA_2592_1944, SCALING, 2592, 1944, ov5640_setting_15fps_QSXGA_2592_1944, ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)}, - {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144, - ov5640_setting_15fps_QCIF_176_144, - ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)}, - {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, - ov5640_setting_15fps_XGA_1024_768, - ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)}, }, { {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480, ov5640_setting_30fps_VGA_640_480, ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)}, - {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240, - ov5640_setting_30fps_QVGA_320_240, - ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)}, {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480, ov5640_setting_30fps_NTSC_720_480, ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)}, - {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576, - ov5640_setting_30fps_PAL_720_576, - ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)}, {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720, ov5640_setting_30fps_720P_1280_720, ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)}, @@ -662,12 +366,6 @@ static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { ov5640_setting_30fps_1080P_1920_1080, ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)}, {ov5640_mode_QSXGA_2592_1944, -1, 0, 0, NULL, 0}, - {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144, - ov5640_setting_30fps_QCIF_176_144, - ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)}, - {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, - ov5640_setting_30fps_XGA_1024_768, - ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)}, }, }; @@ -724,17 +422,22 @@ static const struct ov5640_datafmt static inline void ov5640_power_down(int enable) { - /* 19x19 pwdn pin invert by mipi daughter card */ + if (pwn_gpio < 0) + return; + if (!enable) - gpio_set_value(pwn_gpio, 1); + gpio_set_value_cansleep(pwn_gpio, 0); else - gpio_set_value(pwn_gpio, 0); + gpio_set_value_cansleep(pwn_gpio, 1); msleep(2); } static void ov5640_reset(void) { + if (rst_gpio < 0 || pwn_gpio < 0) + return; + /* camera reset */ gpio_set_value(rst_gpio, 1); @@ -869,6 +572,7 @@ static void OV5640_stream_on(void) static void OV5640_stream_off(void) { ov5640_write_reg(0x4202, 0x0f); + ov5640_write_reg(0x3008, 0x42); } static int OV5640_get_sysclk(void) @@ -1808,31 +1512,35 @@ static int ov5640_probe(struct i2c_client *client, /* ov5640 pinctrl */ pinctrl = devm_pinctrl_get_select_default(dev); - if (IS_ERR(pinctrl)) { - dev_warn(dev, "no pin available\n"); - } + if (IS_ERR(pinctrl)) + dev_warn(dev, "no pin available\n"); /* request power down pin */ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); - if (!gpio_is_valid(pwn_gpio)) { + if (!gpio_is_valid(pwn_gpio)) dev_warn(dev, "no sensor pwdn pin available"); - return -EINVAL; + else { + retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + "ov5640_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } } - retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, - "ov5640_mipi_pwdn"); - if (retval < 0) - return retval; /* request reset pin */ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); - if (!gpio_is_valid(rst_gpio)) { + if (!gpio_is_valid(rst_gpio)) dev_warn(dev, "no sensor reset pin available"); - return -EINVAL; + else { + retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, + "ov5640_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } } - retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, - "ov5640_mipi_reset"); - if (retval < 0) - return retval; /* Set initial values for the sensor struct. */ memset(&ov5640_data, 0, sizeof(ov5640_data)); @@ -1913,6 +1621,7 @@ static int ov5640_probe(struct i2c_client *client, dev_err(&client->dev, "%s--Async register failed, ret=%d\n", __func__, retval); + OV5640_stream_off(); pr_info("camera ov5640_mipi is found\n"); return retval; } -- cgit v1.2.3 From 488fd31c0f0015c077bce098d5e1e46ef1d4bf0c Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Mon, 28 Mar 2016 18:04:40 +0800 Subject: MLK-12432-02: capture: Add support for mipi input Combine csi image setting function for 32-bit,16-bit,8-bit format. For parallel 8-bit sensor input, when bit per pixel is 16, csi image width should been doubled. But for mipi input, the csi image width and height should align with mipi whatever data width. Signed-off-by: Sandor Yu (cherry picked from commit caa8725e713691b42aa112a6e51f12e7d595f139) --- drivers/media/platform/mxc/subdev/mx6s_capture.c | 46 ++++++------------------ 1 file changed, 11 insertions(+), 35 deletions(-) diff --git a/drivers/media/platform/mxc/subdev/mx6s_capture.c b/drivers/media/platform/mxc/subdev/mx6s_capture.c index ed60f8dc72dd..49d4f73c4c24 100644 --- a/drivers/media/platform/mxc/subdev/mx6s_capture.c +++ b/drivers/media/platform/mxc/subdev/mx6s_capture.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -588,33 +588,7 @@ static void csi_dmareq_rff_disable(struct mx6s_csi_dev *csi_dev) __raw_writel(cr3, csi_dev->regbase + CSI_CSICR3); } -static void csi_set_32bit_imagpara(struct mx6s_csi_dev *csi, - int width, int height) -{ - int imag_para = 0; - unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3); - - imag_para = (width << 16) | height; - __raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA); - - /* reflash the embeded DMA controller */ - __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3); -} - -static void csi_set_16bit_imagpara(struct mx6s_csi_dev *csi, - int width, int height) -{ - int imag_para = 0; - unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3); - - imag_para = ((width * 2) << 16) | height; - __raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA); - - /* reflash the embeded DMA controller */ - __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3); -} - -static void csi_set_8bit_imagpara(struct mx6s_csi_dev *csi, +static void csi_set_imagpara(struct mx6s_csi_dev *csi, int width, int height) { int imag_para = 0; @@ -816,6 +790,7 @@ static int mx6s_configure_csi(struct mx6s_csi_dev *csi_dev) { struct v4l2_pix_format *pix = &csi_dev->pix; u32 cr1, cr18; + u32 width; if (pix->field == V4L2_FIELD_INTERLACED) { csi_deinterlace_enable(csi_dev, true); @@ -828,21 +803,22 @@ static int mx6s_configure_csi(struct mx6s_csi_dev *csi_dev) switch (csi_dev->fmt->pixelformat) { case V4L2_PIX_FMT_YUV32: - csi_set_32bit_imagpara(csi_dev, pix->width, pix->height); + case V4L2_PIX_FMT_SBGGR8: + width = pix->width; break; case V4L2_PIX_FMT_UYVY: - csi_set_16bit_imagpara(csi_dev, pix->width, pix->height); - break; case V4L2_PIX_FMT_YUYV: - csi_set_16bit_imagpara(csi_dev, pix->width, pix->height); - break; - case V4L2_PIX_FMT_SBGGR8: - csi_set_8bit_imagpara(csi_dev, pix->width, pix->height); + if (csi_dev->csi_mux_mipi == true) + width = pix->width; + else + /* For parallel 8-bit sensor input */ + width = pix->width * 2; break; default: pr_debug(" case not supported\n"); return -EINVAL; } + csi_set_imagpara(csi_dev, width, pix->height); if (csi_dev->csi_mux_mipi == true) { cr1 = csi_read(csi_dev, CSI_CSICR1); -- cgit v1.2.3 From 517f750e7eb9b04895d05fb02a33e046680c75ce Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Mon, 22 Feb 2016 18:19:44 +0800 Subject: MLK-12432-03: arm: dts: Replace ov5647 mipi sensor with ov5640 ov5647 mipi camera sensor is replaced by ov5640 on imx7D SDB RevB board. Signed-off-by: Sandor Yu (cherry picked from commit aef2ab14e91ccd173086a9849cf64619e078ed6f) --- arch/arm/boot/dts/imx7d-sdb.dts | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 1983250de792..b77baa057698 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -274,7 +274,7 @@ status = "okay"; port { mipi_sensor_ep: endpoint1 { - remote-endpoint = <&ov5647_mipi_ep>; + remote-endpoint = <&ov5640_mipi_ep>; data-lanes = <2>; csis-hs-settle = <13>; csis-wclk; @@ -516,17 +516,18 @@ wlf,shared-lrclk; }; - ov5647_mipi: ov5647_mipi@36 { - compatible = "ovti,ov5647_mipi"; - reg = <0x36>; + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; clocks = <&clks IMX7D_CLK_DUMMY>; clock-names = "csi_mclk"; csi_id = <0>; pwn-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; + AVDD-supply = <&vgen6_reg>; mclk = <24000000>; mclk_source = <0>; port { - ov5647_mipi_ep: endpoint { + ov5640_mipi_ep: endpoint { remote-endpoint = <&mipi_sensor_ep>; }; }; -- cgit v1.2.3 From 9504f7436f6f555ae6616829eed0765699c75a97 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Wed, 20 Apr 2016 17:29:03 +0800 Subject: MLK-12688-01: mipi csi: Add clk_settle setting Add clk_settle variable to compliance more mipi sensor. Mipi controller should setting by followed value according mipi sensor support D-phy version. Slave Clock Lane Control Register for TCLK-SETTLE. 2'b0x = 110 ns to 280ns (v0.87 to v1.00) 2'b10 = 150 ns to 430ns (v0.83 to v0.86) 2'b11 = 60 ns to 140ns (v0.82) Signed-off-by: Sandor Yu (cherry picked from commit 928103ba7d28a7dbddf950892cb9d49ec2b192d3) --- drivers/media/platform/mxc/subdev/mxc_mipi_csi.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c b/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c index a1ed48a9507a..d0e294d7c91a 100644 --- a/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c +++ b/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c @@ -1,7 +1,7 @@ /* * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver * - * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -250,6 +250,7 @@ struct csis_hw_reset { * @flags: the state variable for power and streaming control * @clock_frequency: device bus clock frequency * @hs_settle: HS-RX settle time + * @clk_settle: Clk settle time * @num_lanes: number of MIPI-CSI data lanes used * @max_num_lanes: maximum number of MIPI-CSI data lanes supported * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM @@ -277,6 +278,7 @@ struct csi_state { u32 clk_frequency; u32 hs_settle; + u32 clk_settle; u32 num_lanes; u32 max_num_lanes; u8 wclk_ext; @@ -468,11 +470,14 @@ static void __mipi_csis_set_format(struct csi_state *state) mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val); } -static void mipi_csis_set_hsync_settle(struct csi_state *state, int settle) +static void mipi_csis_set_hsync_settle(struct csi_state *state, + int hs_settle, int clk_settle) { u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); - val = (val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (settle << 24); + val = (val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | + (hs_settle << 24) | (clk_settle << 22); + mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); } @@ -487,7 +492,7 @@ static void mipi_csis_set_params(struct csi_state *state) __mipi_csis_set_format(state); - mipi_csis_set_hsync_settle(state, state->hs_settle); + mipi_csis_set_hsync_settle(state, state->hs_settle, state->clk_settle); val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); if (state->csis_fmt->data_alignment == 32) @@ -942,6 +947,9 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, /* Get MIPI CSI-2 bus configration from the endpoint node. */ of_property_read_u32(node, "csis-hs-settle", &state->hs_settle); + + of_property_read_u32(node, "csis-clk-settle", + &state->clk_settle); state->wclk_ext = of_property_read_bool(node, "csis-wclk"); @@ -1117,9 +1125,10 @@ static int mipi_csis_probe(struct platform_device *pdev) goto e_sd_host; } - dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n", - state->num_lanes, state->hs_settle, state->wclk_ext, - state->clk_frequency); + dev_info(&pdev->dev, + "lanes: %d, hs_settle: %d, clk_settle: %d, wclk: %d, freq: %u\n", + state->num_lanes, state->hs_settle, state->clk_settle, + state->wclk_ext, state->clk_frequency); return 0; e_sd_host: -- cgit v1.2.3 From 3268392176e761ecef35c84e0ebff324fcfa9030 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Wed, 20 Apr 2016 18:16:30 +0800 Subject: MLK-12688-02: arm dts: Add csis-clk-settle property Add csis-clk-settle property to imx7D SDB mipi csi. Signed-off-by: Sandor Yu (cherry picked from commit 01365628fdfadc4f8343722a2d5c69d5d8037540) --- arch/arm/boot/dts/imx7d-sdb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index b77baa057698..40e11178f0b2 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -277,6 +277,7 @@ remote-endpoint = <&ov5640_mipi_ep>; data-lanes = <2>; csis-hs-settle = <13>; + csis-clk-settle = <2>; csis-wclk; }; -- cgit v1.2.3 From b1e060d88f18ee636df74a98e2eba65d7153c824 Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Fri, 29 Apr 2016 10:42:47 +0800 Subject: MLK-12731-1 usb: chipidea: imx: add missing HSIC initialization for imx6qdl/sl This piece of code is existed at imx_3.10, but missing at imx_3.14 and imx_4.1, port it from imx_3.10. Signed-off-by: Peter Chen (cherry picked from commit 901f278a08baf6e5109bcf538f1f78cdbbccd389) --- drivers/usb/chipidea/usbmisc_imx.c | 45 +++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c index 60a4e4ad5869..e62fc732e86c 100644 --- a/drivers/usb/chipidea/usbmisc_imx.c +++ b/drivers/usb/chipidea/usbmisc_imx.c @@ -381,7 +381,7 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data) { struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev); unsigned long flags; - u32 reg; + u32 reg, val; if (data->index > 3) return -EINVAL; @@ -399,6 +399,27 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data) writel(reg | MX6_BM_NON_BURST_SETTING, usbmisc->base + data->index * 4); + /* For HSIC controller */ + if (data->index == 2 || data->index == 3) { + val = readl(usbmisc->base + data->index * 4); + writel(val | MX6_BM_UTMI_ON_CLOCK, + usbmisc->base + data->index * 4); + val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + + (data->index - 2) * 4); + val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON; + writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + + (data->index - 2) * 4); + + /* + * Need to add delay to wait 24M OSC to be stable, + * It is board specific. + */ + regmap_read(data->anatop, ANADIG_ANA_MISC0, &val); + /* 0 <= data->osc_clkgate_delay <= 7 */ + if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val)) + regmap_write(data->anatop, ANADIG_ANA_MISC0_SET, + (data->osc_clkgate_delay) << 26); + } spin_unlock_irqrestore(&usbmisc->lock, flags); usbmisc_imx6q_set_wakeup(data, false); @@ -415,9 +436,9 @@ static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data) usbmisc_imx6q_init(data); + spin_lock_irqsave(&usbmisc->lock, flags); if (data->index == 0 || data->index == 1) { reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4; - spin_lock_irqsave(&usbmisc->lock, flags); /* Set vbus wakeup source as bvalid */ val = readl(reg); writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg); @@ -428,33 +449,17 @@ static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data) val = readl(usbmisc->base + data->index * 4); writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN, usbmisc->base + data->index * 4); - spin_unlock_irqrestore(&usbmisc->lock, flags); } /* For HSIC controller */ if (data->index == 2) { - spin_lock_irqsave(&usbmisc->lock, flags); - val = readl(usbmisc->base + data->index * 4); - writel(val | MX6_BM_UTMI_ON_CLOCK, - usbmisc->base + data->index * 4); val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + (data->index - 2) * 4); - val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON | - MX6SX_BM_HSIC_AUTO_RESUME; + val |= MX6SX_BM_HSIC_AUTO_RESUME; writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + (data->index - 2) * 4); - spin_unlock_irqrestore(&usbmisc->lock, flags); - - /* - * Need to add delay to wait 24M OSC to be stable, - * it's board specific. - */ - regmap_read(data->anatop, ANADIG_ANA_MISC0, &val); - /* 0 <= data->osc_clkgate_delay <= 7 */ - if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val)) - regmap_write(data->anatop, ANADIG_ANA_MISC0_SET, - (data->osc_clkgate_delay) << 26); } + spin_unlock_irqrestore(&usbmisc->lock, flags); return 0; } -- cgit v1.2.3 From e6ea96a8fc8176dbb83484cfedef1ec04daa4ca4 Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Fri, 6 May 2016 14:21:21 +0800 Subject: MLK-12731-2 ARM: dts: Makefile: add dts entry for imx6q-arm2-hsic This dts is only for USB HSIC controller test which needs Validation Port Card on it. Disable controller 3 due to strange signal on it at arm2 board. Signed-off-by: Peter Chen (cherry picked from commit 8bd0739d81719ed8a09ca4e45393bb1c5ce3de83) --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-arm2-hsic.dts | 8 -------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d4f292ac0dc7..863154fe5034 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -286,6 +286,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ imx6q-arm2.dtb \ + imx6q-arm2-hsic.dtb \ imx6q-pop-arm2.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ diff --git a/arch/arm/boot/dts/imx6q-arm2-hsic.dts b/arch/arm/boot/dts/imx6q-arm2-hsic.dts index d2cca3eac3a9..10c95ad96761 100644 --- a/arch/arm/boot/dts/imx6q-arm2-hsic.dts +++ b/arch/arm/boot/dts/imx6q-arm2-hsic.dts @@ -22,11 +22,3 @@ osc-clkgate-delay = <0x3>; status = "okay"; }; - -&usbh3 { - pinctrl-names = "idle", "active"; - pinctrl-0 = <&pinctrl_usbh3_1>; - pinctrl-1 = <&pinctrl_usbh3_2>; - osc-clkgate-delay = <0x3>; - status = "okay"; -}; -- cgit v1.2.3 From 5db98a4109ac40418b9bb825fd2bbe916a80de20 Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Tue, 22 Mar 2016 10:52:27 +0800 Subject: MLK-12420 fix potential head list corruption. The head list may be corrupted when two requests from the same 'pxp_chan' are issued sequentially. So change the issue_pending function to strictly serialized the requests to avoid this kind of issue. Signed-off-by: Fancy Fang (cherry picked from commit 3ed71dcdd8ceeb3725399053f31c1930d2e7a08d) --- drivers/dma/pxp/pxp_dma_v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c index f44045084958..4857c20dd443 100644 --- a/drivers/dma/pxp/pxp_dma_v3.c +++ b/drivers/dma/pxp/pxp_dma_v3.c @@ -1809,6 +1809,8 @@ static void pxp_issue_pending(struct dma_chan *chan) struct pxps *pxp = to_pxp(pxp_dma); unsigned long flags0, flags; + down(&pxp->sema); + spin_lock_irqsave(&pxp->lock, flags0); spin_lock_irqsave(&pxp_chan->lock, flags); @@ -1825,7 +1827,6 @@ static void pxp_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&pxp->lock, flags0); pxp_clk_enable(pxp); - down(&pxp->sema); spin_lock_irqsave(&pxp->lock, flags); pxp->pxp_ongoing = 1; -- cgit v1.2.3 From 8b381036631a5704b4f1fab18ee7fe4184655523 Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Tue, 2 Feb 2016 16:30:50 +0800 Subject: MLK-12371: ARM: imx: suspend-imx7: correct HW_ANADIG_SNVS_MISC_CTRL set To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register , and correct the bit29 setting: --before: write 1 to toggle DDR power pin to high before enter DDR retention, and write 1 again to pull pin to low when exit from DDR retention. --now: write 1 to pull DDR power pin to high and write 0 to low. Signed-off-by: Robin Gong --- arch/arm/mach-imx/suspend-imx7.S | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index 7c85a64a8bb7..5f4e31152a69 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -81,6 +81,8 @@ #define GPC_PGC_C0 0x800 #define GPC_PGC_FM 0xa00 #define ANADIG_SNVS_MISC_CTRL 0x380 +#define ANADIG_SNVS_MISC_CTRL_SET 0x384 +#define ANADIG_SNVS_MISC_CTRL_CLR 0x388 #define ANADIG_DIGPROG 0x800 #define DDRC_STAT 0x4 #define DDRC_PWRCTL 0x30 @@ -336,11 +338,12 @@ ldr r7, [r11, r6] orr r7, r7, #0x1 str r7, [r11, r6] +11: /* turn off ddr power */ ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] ldr r7, =(0x1 << 29) - str r7, [r11, #ANADIG_SNVS_MISC_CTRL] -11: + str r7, [r11, #ANADIG_SNVS_MISC_CTRL_SET] + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] ldr r6, =0x1000 ldr r7, [r11, r6] @@ -367,7 +370,7 @@ /* turn on ddr power */ ldr r7, =(0x1 << 29) - str r7, [r1, #ANADIG_SNVS_MISC_CTRL] + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_CLR] ldr r6, =50 wait_delay @@ -419,7 +422,7 @@ str r7, [r11] 12: ldr r7, =(0x1 << 30) - str r7, [r1, #ANADIG_SNVS_MISC_CTRL] + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_SET] /* need to delay ~5mS */ ldr r6, =0x100000 -- cgit v1.2.3 From 4198b7bad81e6cec30c4008c235945da1f5e7129 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 24 Feb 2016 14:19:23 -0600 Subject: MLK-12448: mtd: gpmi: fix nand double free issue fix the raw_buffer pointer double free issue found by coverify. Signed-off-by: Han Xu --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index b72e5f68ac7a..a234e07cc4f9 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -1008,6 +1008,7 @@ static void gpmi_free_dma_buffer(struct gpmi_nand_data *this) this->cmd_buffer = NULL; this->data_buffer_dma = NULL; + this->raw_buffer = NULL; this->page_buffer_virt = NULL; this->page_buffer_size = 0; } -- cgit v1.2.3 From 83f0dd33f5b9491b32906a2a417674cce98acb7e Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 24 Feb 2016 14:20:25 -0600 Subject: MLK-12449: mtd: gpmi: fix integer overflow issue fix the potential integer overflow issue found by coverify. Signed-off-by: Han Xu --- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index a234e07cc4f9..c799a18eb3d6 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -2115,7 +2115,7 @@ static int mx23_boot_init(struct gpmi_nand_data *this) */ chipnr = block >> (chip->chip_shift - chip->phys_erase_shift); page = block << (chip->phys_erase_shift - chip->page_shift); - byte = block << chip->phys_erase_shift; + byte = (loff_t) block << chip->phys_erase_shift; /* Send the command to read the conventional block mark. */ chip->select_chip(mtd, chipnr); -- cgit v1.2.3 From e3a5bdf8fefbd4feaaebb4a11b9fcac77eb0063d Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Thu, 3 Mar 2016 16:00:54 +0800 Subject: MLK-12509-1 video: mipi_dsi_samsung: create a new dts for mipi dsi. Create a new dts for the 'TFT3P5079E' mipi panel on imx7d sabresd revb board. Signed-off-by: Fancy Fang --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 863154fe5034..18131d041e24 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -390,6 +390,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-gpmi-weim.dtb \ imx7d-sdb-m4.dtb \ imx7d-sdb-qspi.dtb \ + imx7d-sdb-mipi-dsi.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-reva-epdc.dtb \ imx7d-sdb-reva-gpmi-weim.dtb \ diff --git a/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts b/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts new file mode 100644 index 000000000000..2ddf275d97b6 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + #reset-cells = <0>; + }; +}; + +&lcdif { + disp-dev = "mipi_dsi_samsung"; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_epdc0_en>; + lcd_panel = "TRULY-WVGA-TFT3P5079E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; -- cgit v1.2.3 From 00382217e80e04e0d234257f4d860c6a5124a94e Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Fri, 4 Mar 2016 17:27:37 +0800 Subject: MLK-12509-2 video: mipi_dsi_samsung: add 'TFT3P5079E' panel driver. The 'otm8018b' is the Source Driver IC for 'TFT3P5079E' mipi panel. This patch is the kernel driver for 'otm8018b'. No backlight brightness adjustment function, since this is not supported by imx7d sdb revb board. Signed-off-by: Fancy Fang Signed-off-by: Frank Li --- drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c | 266 ++++++++++++++++++++++++++ 1 file changed, 266 insertions(+) create mode 100644 drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c diff --git a/drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c b/drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c new file mode 100644 index 000000000000..fa7db02f37f6 --- /dev/null +++ b/drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include